TWI557853B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI557853B
TWI557853B TW103139187A TW103139187A TWI557853B TW I557853 B TWI557853 B TW I557853B TW 103139187 A TW103139187 A TW 103139187A TW 103139187 A TW103139187 A TW 103139187A TW I557853 B TWI557853 B TW I557853B
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Taiwan
Prior art keywords
layer
semiconductor package
insulating
electronic component
carrier
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TW103139187A
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English (en)
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TW201618246A (zh
Inventor
蔣靜雯
邱承浩
吳政潔
陳光欣
陳賢文
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103139187A priority Critical patent/TWI557853B/zh
Priority to CN201410679766.7A priority patent/CN105702658B/zh
Priority to US14/919,867 priority patent/US9627307B2/en
Publication of TW201618246A publication Critical patent/TW201618246A/zh
Application granted granted Critical
Publication of TWI557853B publication Critical patent/TWI557853B/zh
Priority to US15/455,704 priority patent/US9748183B2/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種具晶圓級線路之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知半導體封裝件1之剖面示意圖，該半導體封裝件1係於一封裝基板18與半導體晶片11之間設置一矽中介板(Through Silicon interposer,TSI)10，該矽中介板10具有導電矽穿孔(Through-silicon via,TSV)100及設於該導電矽穿孔100上之線路重佈結構(Redistribution layer,RDL)15，令該線路重佈結構15藉由複數導電元件17電性結合間距較大之封裝基板18之銲墊180，並形成黏著材12包覆該些導電元件17，而間距較小之半導體晶片 11之電極墊110係藉由複數銲錫凸塊19電性結合該導電矽穿孔100。之後，再形成黏著材12包覆該些銲錫凸塊19。
若該半導體晶片11直接結合至該封裝基板18上，因半導體晶片11與封裝基板18兩者的熱膨脹係數的差異甚大，故半導體晶片11外圍的銲錫凸塊19不易與封裝基板18上對應的銲墊180形成良好的接合，致使銲錫凸塊19自封裝基板18上剝離。另一方面，因半導體晶片11與封裝基板18之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，致使半導體晶片11與封裝基板18之間的電性連接可靠度(reliability)下降，且將造成信賴性測試的失敗。
因此，藉由半導體基材製作之矽中介板10之設計，其與該半導體晶片11的材質接近，故可有效避免上述所產生的問題。
惟，前述習知半導體封裝件1之製法中，於製作該矽中介板10時，需形成該導電矽穿孔100，而該導電矽穿孔100之製程係需於該矽中介板10上挖孔及金屬填孔，致使該導電矽穿孔100之整體製程占整個該矽中介板10之製作成本達約40~50%(以12吋晶圓為例，不含人工成本)，以致於最終產品之成本及價格難以降低。
再者，該矽中介板10之製作技術難度高，致使該半導體封裝件1之生產量相對降低，且製作良率降低。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：絕緣槽體，係具有相對之第一表面與第二表面，且該第一表面上具有開口；絕緣片體，係自該絕緣槽體之第一表面之邊緣向外延伸，且該絕緣片體之厚度小於該絕緣槽體之厚度；電子元件，係設於該開口中，且該電子元件具有相對之作用側與非作用側；介電層，係形成於該絕緣槽體之第一表面、該絕緣片體與該電子元件之作用側上、及該開口中；以及線路層，係設於該介電層上並電性連接該電子元件。
前述之半導體封裝件中，該絕緣片體係與該絕緣槽體一體成形。
本發明復提供一種半導體封裝件之製法，係包括：提供一具有凹部之承載件，且該承載件之表面與該凹部之表面上係形成有一絕緣層；置放至少一電子元件於該凹部中之絕緣層上；形成介電層於該絕緣層與電子元件上，以令該介電層包覆該電子元件；形成線路層於該介電層上，並與該電子元件電性連接；以及移除該承載件，以外露該絕緣層。
前述之製法中，該承載件係為含矽之板體。
前述之製法中，係以濕蝕刻方式移除該承載件，且蝕刻至該絕緣層。
前述之製法中，該承載件具有複數個該凹部，以於移除該承載件後，進行切單製程。
前述之半導體封裝件及製法中，形成該絕緣層(或絕緣槽體、絕緣片體)之材質係為氧化矽或氮化矽。
前述之半導體封裝件及製法中，該電子元件以其非作用側藉由結合層結合至該凹部(或該開口)中。
前述之半導體封裝件及製法中，於移除該承載件後，移除該絕緣槽體之第二表面之部分材質與該結合層，使該電子元件之非作用側外露於該絕緣槽體之第二表面。
前述之半導體封裝件及製法中，該介電層之材質不同於該絕緣層之材質。
前述之半導體封裝件及製法中，復包括於移除該承載件後，移除該絕緣片體之部分材質，使該線路層外露於該絕緣片體。
前述之半導體封裝件及製法中，復包括形成線路重佈結構於該介電層與該線路層上，且該線路重佈結構電性連接該線路層。又包括於移除該承載件後，結合封裝基板至該線路重佈結構上，且該線路重佈結構電性連接該封裝基板。
另外，前述之半導體封裝件及製法中，復包括於移除該承載件後，結合封裝基板至該線路層上，且該線路層電性連接該封裝基板。
由上可知，本發明之半導體封裝件及其製法，藉由該絕緣層之設計，能增加該半導體封裝件之整體結構之剛性，不僅能降低該介電層之厚度，並可避免於製程中因升溫或降溫而發生熱翹曲的現象。
再者，本發明因無需製作習知矽中介板之方式，故不僅能大幅降低該半導體封裝件之製作成本，且能簡化製程，使該半導體封裝件之生產量提高及提高製作良率。
1、2、2’、2”、3‧‧‧半導體封裝件
10‧‧‧矽中介板
100‧‧‧導電矽穿孔
11‧‧‧半導體晶片
110、210‧‧‧電極墊
12‧‧‧黏著材
15、25‧‧‧線路重佈結構
17、27‧‧‧導電元件
18、28‧‧‧封裝基板
180‧‧‧銲墊
19‧‧‧銲錫凸塊
20‧‧‧承載件
200‧‧‧凹部
21、21’‧‧‧電子元件
21a‧‧‧作用側
21b‧‧‧非作用側
211‧‧‧結合層
212‧‧‧結合材
212a、212b‧‧‧晶片
22‧‧‧絕緣層
23‧‧‧介電層
230‧‧‧盲孔
24、34‧‧‧線路層
240‧‧‧導電盲孔
250‧‧‧介電部
251‧‧‧線路部
26‧‧‧絕緣保護層
260‧‧‧開孔
32‧‧‧絕緣槽體
32a‧‧‧第一表面
32b、32b’‧‧‧第二表面
320‧‧‧開口
340‧‧‧導電體
37‧‧‧導電凸塊
42‧‧‧絕緣片體
S‧‧‧切割路徑
T、t、m、h、L‧‧‧厚度
d‧‧‧深度
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2H圖係本發明之半導體封裝件之製法之第一實施例的剖面示意圖；其中，第2B’及2B”圖係第2B圖之其它實施例，第2G’及2G”圖係第2G圖之其它實施例，第2H’及2H”圖係第2H圖之其它實施例；以及第3A至3B圖係本發明之半導體封裝件之製法之第二實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調 整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之半導體封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一具有複數凹部200之承載件20，且該承載件20之表面與該凹部200之表面上係形成有一絕緣層22。
於本實施例中，該承載件20係為含矽之板體，且形成該絕緣層22之材質係為氧化矽(SiO2)或氮化矽(SixNy)。
再者，該凹部200之深度d係至多為該承載件20之厚度T之一半。
如第2B圖所示，置放複數電子元件21於該凹部200中之絕緣層22上。
於本實施例中，該電子元件21係具有相對之作用側21a與非作用側21b，該作用側21a具有複數電極墊210，且該非作用側21b藉由一結合層211將該電子元件21結合至該絕緣層22上，並使該電子元件21未凸伸出該凹部200。其中，該電子元件21之厚度t係為10至300微米(um)，較佳為20至150微米，而該結合層211之厚度m係為5至25微米。
再者，於其它實施例中，如第2B’圖所示，該電子元件21亦可凸伸出該凹部200。
又，該結合層211係如晶片絕緣層(die attach film，簡稱DAF)，其可先形成於該電子元件21之非作用側21b， 再將該電子元件21置放於該凹部200中；或者，該結合層211亦可先形成於該凹部200中(如第2B”圖所示之點膠方式)，再將該電子元件21結合至該凹部200中之結合層211上。
另外，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於此，該電子元件21係為如單一晶片結構之主動元件，且於一凹部200中係置放兩個電子元件21，但不限於置放兩個電子元件21。
於其它實施例中，如第2B”圖所示，該電子元件21’亦可為如多晶片模組之主動元件，例如，先將兩晶片212a,212b以結合材212(如環氧樹脂)相結合成一模組，再將該模組置放於該凹部200中。
如第2C圖所示，接續第2B圖之製程，形成一介電層23於該絕緣層22與電子元件21上，且形成複數盲孔230於該介電層23中，以令該些電極墊210外露於該些盲孔230。
於本實施例中，該介電層23係填入該凹部200中，以令該介電層23包覆該電子元件21。
再者，形成該介電層23之材質係為感光材、聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)或苯環丁烯(Benzocyclclobutene，簡稱BCB)，故形成該介電層23之材質不同於該絕緣層22之材質。
又，可藉由化學(如蝕刻)或物理(如雷射開孔)方 式形成該些盲孔230。
如第2D圖所示，形成一線路層24於該介電層23上，且形成導電盲孔240於該盲孔230中，使該線路層24藉由該些導電盲孔240電性連接該電子元件21之電極墊210。
於本實施例中，該線路層24係為晶圓級線路，而非封裝基板級線路，其中，該封裝基板級線路之最小之線寬與線距為12μm，而半導體製程能製作出3μm以下之線寬與線距之晶圓級線路。
如第2E圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，即形成一線路重佈結構25於該介電層23與該線路層24上，且該線路重佈結構25係電性連接該線路層24。
於本實施例中，該線路重佈結構25係包含相疊之介電部250、線路部251及絕緣保護層26，且該絕緣保護層26形成有複數開孔260，令該線路部251外露於各該開孔260，以供結合如銲球之導電元件27。
如第2F圖所示，移除該承載件20，以外露該絕緣層22。
於本實施例中，以濕蝕刻方式移除該承載件20，且該絕緣層22可作為止蝕層，故蝕刻至該絕緣層22，其中，蝕刻液可為氫氧化四甲基銨(TMAH)或氫氧化鉀(KOH)蝕刻液。
如第2G圖所示，沿如第2F圖所示之切割路徑S進行切單製程，以形成本發明之其中一種半導體封裝件2之態 樣。
於本實施例中，該絕緣層22係定義有一絕緣槽體32與一絕緣片體42，該絕緣槽體32具有相對之第一表面32a與第二表面32b，該第一表面32a具有已設置該電子元件21之一開口320，且該絕緣片體42係自該絕緣槽體32之第一表面32a之邊緣延伸，而該絕緣片體42之厚度h小於該絕緣槽體32之厚度L。
再者，亦可如第2G’圖所示，於進行切單製程後，移除該絕緣槽體32之第二表面32b之部分材質與該結合層211，使該電子元件21之非作用側21b外露於該絕緣槽體32之第二表面32b’。
又，若接續第2B’圖之製程，將得到如第2G”圖所示之半導體封裝件2”。
如第2H圖所示，接續第2G圖之製程，藉由該些導電元件27結合一封裝基板28至該線路重佈結構25上，且該線路重佈結構25之線路部251電性連接該封裝基板28。
再者，如第2H’圖所示，係接續第2D圖所示之製程，於形成該線路層24後，未形成介電部250與線路部251，而形成該絕緣保護層26於該線路層24上，且該絕緣保護層26形成有外露該線路層24之複數開孔260，以形成該些導電元件27於該線路層24之外露處上，再進行切單製程，之後藉由該些導電元件27結合該封裝基板28至該線路層24上，且該線路層24電性連接該封裝基板28。
又，如第2H”圖所示，係接續第2B”圖之製程。
第3A至3B圖係為本發明之半導體封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於該絕緣片體之製程，其它步驟之製程大致相同，故不再贅述相同處。
如第3A圖所示，於製作該線路層24時，係於該絕緣片體42上形成部分線路層34，且該線路層34於該介電層23中形成有導電體340，以於移除該承載件20後，移除該絕緣片體42之部分材質，使該線路層34之導電體340外露於該絕緣片體42。
如第3B圖所示，形成複數導電凸塊37於該導電體340之外露處上，以供結合如半導體晶片之電子裝置(圖略)。
本發明之製法中，由於該介電層23之材質係為感光材、PI、PBO或BCB，故通常需有一定的厚度以具較佳的機械性質(如結構強度)而足以包覆該電子元件21,21’，且該介電層23與該封裝基板28的CTE值差異過大，以致於在接合該封裝基板28並進行其它高溫製程時，容易因CTE不匹配而造成翹曲(warpage)之問題。
因此，本發明藉由該絕緣層22之設計以得到較強的結構，使本發明之半導體封裝件2,2’,2”,3不僅能降低該介電層23之厚度，並可避免於製程中因升溫或降溫而發生熱翹曲的現象。
再者，本發明之製法因無需製作習知矽中介板，故不僅能大幅降低該半導體封裝件2,2’,2”,3之製作成本，且能簡化製程，使該半導體封裝件之生產量提高及提高製作 良率。
又，本發明之半導體封裝件2,2’,2”,3因無習知矽中介板，故相較於習知具矽中介板之封裝件，本發明之半導體封裝件2,2’,2”,3能使最終產品之整體厚度較薄。
另外，本發明之半導體封裝件2,2’,2”,3之電子元件21,21’無需經由習知矽中介板做訊號轉接傳輸，故該電子元件21,21’之傳輸速度更快。
本發明係提供一種半導體封裝件2,2’,2”,3，係包括：一絕緣槽體32、一絕緣片體42、至少一電子元件21,21’、一介電層23、以及設於該介電層23上之一線路層24,34。
所述之絕緣槽體32係具有相對之第一表面32a與第二表面32b，且該第一表面32a上具有開口320。
所述之絕緣片體42係自該絕緣槽體32之第一表面32a之邊緣向外延伸，且該絕緣片體42之厚度h小於該絕緣槽體32之厚度L。
所述之電子元件21,21’係為主動元件、被動元件或其組合者，其設於該開口320中，且該電子元件21,21’具有相對之作用側21a與非作用側21b。
所述之介電層23係設於該絕緣槽體32之第一表面32a、該絕緣片體42與該電子元件21,21’之作用側21a上、及該開口320中，且該介電層23之材質不同於該絕緣槽體32之材質與該絕緣片體42之材質。
所述之線路層24,34係具有位於該介電層23中之複數 導電盲孔240，俾藉其電性連接該電子元件21,21’。
於一實施例中，該絕緣片體42係與該絕緣槽體32一體成形。
於一實施例中，該電子元件21,21’之非作用側21b係藉由結合層211結合至該開口320上。
於一實施例中，該電子元件21之非作用側21b係外露於該絕緣槽體32之第二表面32b’。
於一實施例中，該線路層34係具有穿過該介電層23之導電體340，且該導電體340外露於該絕緣片體42。
於一實施例中，所述之半導體封裝件2,2’,2”,3復包括一線路重佈結構25，係設於該介電層23與該線路層24,34上並電性連接該線路層24,34，且又包括一設於該線路重佈結構25上並電性連接該線路重佈結構25之封裝基板28。
於一實施例中，所述之半導體封裝件2,2’,2”,3復包括一設於該線路層24上並電性連接該線路層24,34之封裝基板28。
綜上所述，本發明之半導體封裝件及其製法，主要藉由該絕緣層之設計，能增加該半導體封裝件之整體結構之剛性，不僅能降低該介電層之厚度，並可避免於製程中因升溫或降溫而發生熱翹曲的現象。
再者，無需製作習知矽中介板之方式，不僅能大幅降低該半導體封裝件之製作成本，且能簡化製程，使該半導體封裝件之生產量提高及提高製作良率。
又，本發明之半導體封裝件因無習知矽中介板之結構，故能使最終產品之整體厚度較薄，且能使該電子元件之傳輸速度更快。
另外，藉由該承載件係為含矽材質之設計，以避免該承載件發生翹曲的現象。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
21‧‧‧電子元件
21a‧‧‧作用側
21b‧‧‧非作用側
22‧‧‧絕緣層
23‧‧‧介電層
24‧‧‧線路層
25‧‧‧線路重佈結構
32‧‧‧絕緣槽體
32a‧‧‧第一表面
32b‧‧‧第二表面
320‧‧‧開口
42‧‧‧絕緣片體
L、h‧‧‧厚度

Claims (21)

  1. 一種半導體封裝件，係包括：絕緣槽體，係具有相對之第一表面與第二表面，且該第一表面上具有開口；絕緣片體，係自該絕緣槽體之第一表面之邊緣向外延伸，且該絕緣片體之厚度小於該絕緣槽體之厚度；電子元件，係設於該開口中，且該電子元件具有相對之作用側與非作用側；介電層，係形成於該絕緣槽體之第一表面、該絕緣片體與該電子元件之作用側上、及該開口中，以包覆該電子元件；以及線路層，係設於該介電層上並電性連接該電子元件。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，形成該絕緣槽體之材質係為氧化矽或氮化矽。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，形成該絕緣片體之材質係為氧化矽或氮化矽。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該絕緣片體係與該絕緣槽體一體成形。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該電子元件之非作用側係藉由結合層結合至該開口上。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該電子元件之非作用側係外露於該絕緣槽體之第二表 面。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路層係穿過該介電層而外露於該絕緣片體。
  8. 如申請專利範圍第1項所述之半導體封裝件，復包括線路重佈結構，係設於該介電層與該線路層上並電性連接該線路層。
  9. 如申請專利範圍第8項所述之半導體封裝件，復包括封裝基板，係設於該線路重佈結構上並電性連接該線路重佈結構。
  10. 如申請專利範圍第1項所述之半導體封裝件，復包括封裝基板，係設於該線路層上並電性連接該線路層。
  11. 一種半導體封裝件之製法，係包括：提供一具有凹部之承載件，且該承載件之表面與該凹部之表面上係形成有一絕緣層；置放至少一電子元件於該凹部中之絕緣層上；形成介電層於該絕緣層與電子元件上，以令該介電層包覆該電子元件；形成線路層於該介電層上，並與該電子元件電性連接；以及移除該承載件，以外露該絕緣層。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該承載件係為含矽之板體。
  13. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該承載件具有複數個該凹部，以於移除該承載 件後，進行切單製程。
  14. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，形成該絕緣層之材質係為氧化矽或氮化矽。
  15. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，係以濕蝕刻方式移除該承載件，且蝕刻至該絕緣層。
  16. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該電子元件係具有相對之作用側與非作用側，且該電子元件以其非作用側藉由結合層結合至該凹部中。
  17. 如申請專利範圍第16項所述之半導體封裝件之製法，復包括於移除該承載件後，移除該絕緣層之部分材質與該結合層，使該電子元件之非作用側外露於該絕緣層。
  18. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括於移除該承載件後，移除該絕緣層之部分材質，使該線路層外露於該絕緣層。
  19. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成線路重佈結構於該介電層與該線路層上，且該線路重佈結構電性連接該線路層。
  20. 如申請專利範圍第19項所述之半導體封裝件之製法，復包括於移除該承載件後，結合封裝基板至該線路重佈結構上，且該線路重佈結構電性連接該封裝基板。
  21. 如申請專利範圍第11項所述之半導體封裝件之製法， 復包括於移除該承載件後，結合封裝基板至該線路層上，且該線路層電性連接該封裝基板。
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US9379041B2 (en) * 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
TWI550783B (zh) * 2015-04-24 2016-09-21 矽品精密工業股份有限公司 電子封裝件之製法及電子封裝結構
US11189576B2 (en) * 2016-08-24 2021-11-30 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US20180166356A1 (en) * 2016-12-13 2018-06-14 Globalfoundries Inc. Fan-out circuit packaging with integrated lid
CN107331627A (zh) * 2017-07-03 2017-11-07 京东方科技集团股份有限公司 一种芯片封装方法及芯片封装结构
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094830A1 (en) * 2000-09-08 2004-05-20 Intel Corporation Integrated core microelectronic package
US20090206470A1 (en) * 2008-02-18 2009-08-20 Shinko Electric Industries, Co., Ltd. Semiconductor device manufacturing method, semiconductor device, and wiring board
US20090302448A1 (en) * 2008-06-05 2009-12-10 Cheng-Tang Huang Chip Stacked Structure and the Forming Method
US20120306100A1 (en) * 2009-10-06 2012-12-06 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US8828802B1 (en) * 2011-11-01 2014-09-09 Amkor Technology, Inc. Wafer level chip scale package and method of fabricating wafer level chip scale package

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2789505B1 (fr) * 1999-02-08 2001-03-09 Gemplus Card Int Procede de fabrication de support de memorisation portable de type carte a puce
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
CN100411123C (zh) * 2005-11-25 2008-08-13 全懋精密科技股份有限公司 半导体芯片埋入基板的结构及制法
CN100561696C (zh) * 2007-03-01 2009-11-18 全懋精密科技股份有限公司 嵌埋半导体芯片的结构及其制法
CN101295650A (zh) * 2007-04-25 2008-10-29 矽品精密工业股份有限公司 半导体装置及其制法
CN101295651A (zh) * 2007-04-26 2008-10-29 矽品精密工业股份有限公司 半导体装置及其制法
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
TWI418269B (zh) * 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
TWI492680B (zh) * 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
TWI446501B (zh) * 2012-01-20 2014-07-21 矽品精密工業股份有限公司 承載板、半導體封裝件及其製法
CN103579145B (zh) * 2012-08-10 2017-12-08 欣兴电子股份有限公司 穿孔中介板及其制法与封装基板及其制法
TWI503928B (zh) * 2012-09-10 2015-10-11 矽品精密工業股份有限公司 半導體封裝件及其製法與中介板結構
TWI483365B (zh) * 2012-09-26 2015-05-01 Ind Tech Res Inst 封裝基板及其製法
TWI497616B (zh) * 2012-11-08 2015-08-21 矽品精密工業股份有限公司 半導體封裝件之製法
US9318404B2 (en) * 2013-02-05 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
US9406590B2 (en) * 2013-04-19 2016-08-02 Xintec Inc. Chip package and manufacturing method thereof
TWI517341B (zh) * 2013-05-10 2016-01-11 矽品精密工業股份有限公司 半導體封裝件及其製法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094830A1 (en) * 2000-09-08 2004-05-20 Intel Corporation Integrated core microelectronic package
US20090206470A1 (en) * 2008-02-18 2009-08-20 Shinko Electric Industries, Co., Ltd. Semiconductor device manufacturing method, semiconductor device, and wiring board
US20090302448A1 (en) * 2008-06-05 2009-12-10 Cheng-Tang Huang Chip Stacked Structure and the Forming Method
US20120306100A1 (en) * 2009-10-06 2012-12-06 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US8828802B1 (en) * 2011-11-01 2014-09-09 Amkor Technology, Inc. Wafer level chip scale package and method of fabricating wafer level chip scale package

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