/1286354 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體積體餅元件，_是有關於半導 體積體晶片之製造領域’其中涉及一種能夠有效阻擔晶圓切 * 割所造成的介電層界面脫層現象的手段的應用。 【先前技術】 * 縣電晶體等半導體元件尺寸的微小化，半導體積體電路的效 旎以及密度也隨之大幅度的提昇。當半導體積體電路的製造水平 達到次微米絲米的技龄級時，電阻_電容輯便成為電路的效 能是否能進-步提昇的瓶頸。藉由降低金助連結線路的線路電 阻或者是降地介電層的電容可以使電阻-電容延遲問題改善。其 中，在降低金屬内連結線路的線路電阻方面，晶片製造業者已經 在製程上採用銅金屬取代電阻率較高的鋁金屬，而在降地介電層 • 的電容方面，則積極地找尋更低介電常數的介電材料。 然而，與過去所使用的氧化矽介電材料相比較，例如氟矽玻璃 或者未摻雜矽玻璃等，目前所採用大部分的低介電常數介電材料 的機械強度仍嫌不足。此外，低介電常數介電材料的另一個問題 是界面間的黏合力差，不論是在兩層相同的低介電常數介電材料 之間的界面，或者是在一層低介電常數介電材料與另一層不同性 質的介電層之間的界面。當進行後續的晶圓處理步驟時，例如晶 圓切割，由於低介電常數的介電材料的黏合力不足，往往發生問題。 .1286354 在進行晶圓切割時，由於是採用機械切刀沿著切割道礙切晶 圓’造成晶圓表面需承受相當大的應力，因此在晶圓切割時或者 晶圓切割後’通常會發現在低介電f數介電材料之間形成界面脫 層現象λϊ衫響到積體電路晶片的可靠度。由此可知，在此技術 •頂域中仍而要種有效的方法，以解決上述的晶圓切割所造成的 界面脫層傳播。 _ 【發明内容】 本發明的主要目的在於提供_财朗加髓構，其被佈設在 曰a圓可#度/貞说墊上，藉以阻擋晶圓切割時產生的介電層界面脫 層的值播。 根據本發明之錄實補’本發明提供—種半導體晶圓，包含 有複數個積體電路晶片區域，各該積體電路晶片區域之周圍由一 籲曰曰圓切割道圍繞；複數個金屬塾，設於該晶圓切割道上，其令該 金屬墊至少包含有—職電路，其設於複數層介電層巾；以及一 強化結構，包含有沿著各該金屬墊的至少—邊上所設置的形成在 2數層介電射賴數齡相。射，該謹_洞可以 匕含有至少-排_鄰制，其中，該複數個介相可以包含至 少一長型孔洞。 根據本㈣之另—麵實施例，本發雜供—種_半導體晶 、方法。首先’於一半導體晶圓上形成複數個積體電路晶片區 6 1286354 域，且各該積體電路晶片區域之周圍由—晶圓切割道圍繞。於該 晶圓切割道中形成複數個测試塾。沿著各該測試塾的至少一邊 上开/成強化結構。最後，沿著該晶圓切割道切割該半歸晶圓。 •—為了使貴審查委員能更進一步了解本發明之特徵及技術内 •容’請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與辅助說明用，並非用來對本發明加以限制者。 【實施方式】 請參閱第1圖以及第2圖，其中第！圖是半導體晶圓的部分切 割道之放大上視示意g ;第2酬是第丨圖中沿著切線w之剖面 示意 1。如第i圖所示，半導體晶圓1〇至少包括有兩相鄰的積體 電路曰曰片12以及積體電路晶片14。在兩相鄰的積體電路晶片u 以及積體電路晶片14之間為晶圓切割道16，且沿著晶圓切割道 16内設有複數個晶圓可靠度測試(waferacc印tancetesting，WAT) 塾或測試墊20。根據本發明之較佳實施例，晶圓可靠度測試塾如 的邊長約為50微米左右。 在積體電路晶片12周圍設有—晶方封環(die卿1_)結構 12a，而在積體電路晶片14周圍設有—晶方封環結構⑷。在每一 積體電路晶片12或14中形成有中心電路(corecircuit),其中包括 有的電路元件’例如電晶體(transist〇r卜電容㈣如㈣、二^ (diode)、摻雜擴散區、記憶體陣列或者金屬内連線等等。 7 .1286354 曰曰:方封環結構12a及14a，包括有複數個金屬層，上下堆疊而 曰為該技術領域常用之結構，用來保護中心電路，使其減輕 :圓切割時產生的應力破壞力。前述的晶方封環結構以及⑷ •疋在製4〜電路的同時，以相同的介電層沈積步驟以及金屬沈 •積餘刻等步驟同時逐步向上堆疊而成。 U在轉縣材巾，例如錄材，會絲餘#雜區域(圖未 響示），然後再將晶方封環結構12a及14a形成在重摻雜區域上，並 =許特=的電壓，例如接地電壓或者&經由重摻雜區域提供給 阳方封％結構12a及14a。最後，在中心電路以及晶圓切割道上覆 蓋一保護層「例如氮化矽或氧化矽。 在第1目中，箭頭22所指方向為晶圓切割方向，❿箭頭％所 指方向’代表_是在晶圓蝴時醜生的應力方向，換言之， •箭頭24代表的也就是晶圓切割時介電層界面脫層的傳播方向。如 前所述，採關齡刀沿著蝴道彻晶圓，造成晶圓表面需承 受相當大的應力，因此在晶圓切割時或者晶圓切割後，通常會發 現在低介電常數介電材料之卿成界峨層現象，而影響到積體 電路晶片的可靠度。 為了避免晶圓切割時所產生的應力破壞，本發明在晶圓可靠度 測試墊20的兩相對側邊上，刻意設置有狹長形的開口⑶〇明〇，其 長度約略等於晶圓可靠度測試塾20的邊長，而其寬度約為〇·5微 1286354 米左右或者更小。狹長形的開口 3〇的配置方式基本上是沿著測試 墊^20的兩相對的侧邊上，平行於箭頭22所指的晶圓切割方向， 也就是說，開口 30的配置方向乃垂直於箭頭24所代表的界面脫 .層傳播方向，藉此達到阻擋界面脫層傳播之目的。此外，在開口 • 30内’設有一金屬阻擋牆5〇,作為強化。 :.'.1 . . 如第2圖所示，金屬阻擋牆50包含有至少一第-鑲嵌金屬結 構52以及一第二鑲嵌金屬結構54。前述的金屬阻擋牆5〇同樣是 在製造中心電路的同時，以相同的介電層沈積步驟以及金 蝕刻等步驟同時逐步向上堆疊而成。 舉例來說’晶圓10的最上層金屬導線為第河利層導線，其下 方金屬導線層為第MN層導線，聯絡第Mn+i層導線與第Mn層導 線之間的是第VN+1層金屬介層(via)，聯絡第％層導線與其下方 _金屬導線層之_是第VN層金屬介層，其中層導線與第 Vn+1層金屬介層可以是利用銅鑲嵌製程形成在第DN+丨層介電層 中，而帛MN層導線與第Vn層金屬介層可以是利用銅镶嵌製程曰形 成在第DN層介電層中。 前述與中心電路的同時製作是指金屬阻擋牆50的第一鑲嵌金 屬結構52係與晶圓10的第Mn+ !層與第Vn+ ι層金屬介層同時形 成，而金屬阻擋牆50的第二鑲嵌金屬結構52與第Mn層、第％ 層金屬介層同時形成。第一鑲嵌金屬結構52的作法是在第Dn+i 1286354 層介電層中以銅鑲嵌製程技術形咸高深寬比的溝渠，然後於溝渠 内填入銅金屬。 根據本發明之較佳實施例，第一鑲嵌金屬結構52與第二鑲嵌 金屬結構54有部分的重疊，且交錯排列，但不限於此。本發明較 •重要之另一特徵在於第一鑲嵌金屬結構52與第二鑲嵌金屬結構 54可以是包覆有空氣之中空構造(void)，這樣的中空結構特別在晶 • 圓切割時可以釋放大部分的應力，而保護晶片的完整性。藉由控 -制前述形成在第DN+1層介電層中的溝渠的深寬比，可以使第一鑲 嵌金屬結構52形成包覆有空氣的中空構造。 • * * · · 此外，本發明較重要之另一特徵在於形成在第1^+1層介電層 中的第一鑲嵌金屬、结構52向下陷入第也層介電層，而形成在第 DN層介電層中的第二鑲嵌金屬結構54向下陷入第層介電層。 根據本發明另一較佳實施例，設置在晶圓可靠度測試墊2〇的 兩相對側邊上的開口 3〇以及形成在開口 3〇内的金屬阻擋牆5〇， 並不限於狹長型，而亦可以是麵狀、波浪狀、複數個相鄰孔洞 或其它不規則狀。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 1286354 【圖式簡單說明】 第1圖是半導體晶圓的部分切割道之放大上視示意圖。 第2圖則是第1圖中沿著切線I-Ι之剖面示意圖。 【主要元件符號說明】. 10 半導體晶圓 12 積體電路晶片 12a 晶方封環結構 14 積體電路晶片 14a 晶方封環結構 16 晶圓切割道 20 晶圓可靠度測試墊 22 晶圓切割方向 24 應力方向 30 開口 50 金屬阻擂牆 52 第一鑲嵌金屬結構 54 第二鑲嵌金屬結構</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The application of the means of delamination of the dielectric layer caused by cutting. [Prior Art] * The size of semiconductor components such as the county's transistor is miniaturized, and the efficiency and density of the semiconductor integrated circuit are greatly improved. When the manufacturing level of the semiconductor integrated circuit reaches the technical level of the sub-micron meter, the resistance-capacitor becomes the bottleneck of whether the circuit's performance can be further improved. The resistance-capacitance delay problem can be improved by reducing the line resistance of the gold-assisted connection line or the capacitance of the lower dielectric layer. Among them, in reducing the line resistance of the metal interconnection line, the chip manufacturer has used copper metal to replace the aluminum metal with higher resistivity in the process, and actively seeks lower capacitance in the dielectric layer of the ground reduction layer. Dielectric material of dielectric constant. However, compared with the cerium oxide dielectric materials used in the past, such as fluorocarbon glass or undoped bismuth glass, the mechanical strength of most of the low dielectric constant dielectric materials currently used is still insufficient. In addition, another problem with low-k dielectric materials is the poor adhesion between the interfaces, either at the interface between two layers of the same low-k dielectric material, or in a low-k dielectric. The interface between the material and another dielectric layer of a different nature. When performing subsequent wafer processing steps, such as wafer dicing, problems often occur due to insufficient adhesion of low dielectric constant dielectric materials. .1286354 In the case of wafer dicing, the use of a mechanical cutter to cut the wafer along the scribe line 'causes the wafer surface to withstand considerable stress, so it is usually found during wafer dicing or after wafer dicing An interface delamination phenomenon is formed between low dielectric f-number dielectric materials to the reliability of the integrated circuit chip. It can be seen that an effective method is still needed in the top field of the technology to solve the above-mentioned interfacial delamination caused by wafer dicing. SUMMARY OF THE INVENTION The main object of the present invention is to provide a _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ broadcast. According to the invention, the invention provides a semiconductor wafer comprising a plurality of integrated circuit wafer regions, each of which is surrounded by a ring-shaped circular cutting track; a plurality of metal crucibles; Provided on the wafer dicing street, the metal pad includes at least a circuit, which is disposed on the plurality of dielectric layers; and a reinforcing structure including at least an edge along each of the metal pads The setting is formed in two layers of dielectric lasing ages. The _ hole may contain at least a row-side system, wherein the plurality of phases may contain at least one elongated hole. According to another embodiment of the present invention, the present invention provides a semiconductor crystal. First, a plurality of integrated circuit chip regions 6 1286354 are formed on a semiconductor wafer, and the periphery of each of the integrated circuit wafer regions is surrounded by a wafer scribe line. A plurality of test turns are formed in the wafer scribe line. The reinforcing structure is opened/extruded along at least one side of each of the test crucibles. Finally, the semi-return wafer is cut along the wafer scribe line. • For a better understanding of the features and techniques of the present invention, please refer to the following detailed description of the invention and the accompanying drawings. The drawings are to be considered in all respects as illustrative and not restrictive. [Embodiment] Please refer to Figure 1 and Figure 2, where the first! The figure is an enlarged top view of a portion of the dicing street of the semiconductor wafer; the second reticle is a cross-sectional view along the tangential line w in the second figure. As shown in Fig. i, the semiconductor wafer 1 includes at least two adjacent integrated circuit chips 12 and integrated circuit chips 14. A wafer dicing street 16 is disposed between the two adjacent integrated circuit chips u and the integrated circuit wafer 14, and a plurality of wafer reliability tests (waferacc printed tasttesting, WAT) are provided along the wafer dicing street 16.塾 or test pad 20. In accordance with a preferred embodiment of the present invention, the wafer reliability test has a side length of about 50 microns. A crystal sealing ring structure 12a is provided around the integrated circuit wafer 12, and a crystal square sealing ring structure (4) is provided around the integrated circuit wafer 14. A core circuit is formed in each of the integrated circuit wafers 12 or 14, including circuit elements such as transistors (transistors, capacitors, etc.), such as (d), diodes, doped diffusion regions, Memory array or metal interconnect, etc. 7.1286354 曰曰: square ring structure 12a and 14a, including a plurality of metal layers, stacked on top of each other and used as a structure commonly used in the technical field to protect the central circuit, To reduce it: the stress destructive force generated during the circular cutting. The aforementioned square sealing ring structure and (4) • while the 4~ circuit is being formed, the same dielectric layer deposition step and metal sinking and accumulation steps are simultaneously performed. Gradually stacking up. U is in the county material, such as the recording material, the wire will be miscellaneous (not shown), and then the square ring structure 12a and 14a are formed on the heavily doped area, and = Hutt = voltage, such as ground voltage or & is provided to the male square structure % structure 12a and 14a via the heavily doped region. Finally, the central circuit and the wafer scribe line are covered with a protective layer "such as tantalum nitride or oxide矽. In the first item, the arrow 2 The direction indicated by 2 is the wafer cutting direction, and the direction indicated by the arrow % indicates that the _ is the ugly stress direction at the wafer, in other words, the arrow 24 represents the delamination of the dielectric layer during wafer dicing. The direction of propagation. As mentioned above, the cutting of the knife along the butterfly path causes the wafer surface to withstand considerable stress, so it is usually found in the low-media during wafer cutting or wafer cutting. The electrical constant dielectric material is a layered phenomenon that affects the reliability of the integrated circuit wafer. To avoid stress damage during wafer dicing, the present invention is on opposite sides of the wafer reliability test pad 20. On the side, a slit (3) opening is intentionally provided, the length of which is approximately equal to the side length of the wafer reliability test 塾20, and the width thereof is about 微·5 micro 1,286,354 m or less. The slit-shaped opening The arrangement of the 3 turns is basically along the opposite sides of the test pad 20, parallel to the wafer cutting direction indicated by the arrow 22, that is, the arrangement direction of the opening 30 is perpendicular to the arrow 24 Interface de-layer propagation In order to achieve the purpose of blocking the delamination of the interface. In addition, a metal barrier wall 5 is provided in the opening 30 as a reinforcement. :. '.1 . . As shown in Fig. 2, the metal barrier wall 50 The at least one first inlaid metal structure 52 and the second inlaid metal structure 54 are included. The foregoing metal barrier wall 5〇 is also formed by the same dielectric layer deposition step and gold etching step simultaneously while manufacturing the central circuit. For example, the uppermost metal wire of the wafer 10 is the first river layer conductor, and the lower metal wire layer is the MN layer wire, which is connected between the Mn+i layer conductor and the Mn layer conductor. It is a VN+1 metal via, and the contact layer of the % layer conductor and the underlying metal wiring layer is the VN metal layer, wherein the layer conductor and the Vn+1 metal layer can be made of copper. The damascene process is formed in the DN+ 介 dielectric layer, and the 帛 MN layer conductor and the Vn layer metal via layer may be formed in the DN layer dielectric layer by using a copper damascene process. The foregoing fabrication with the central circuit means that the first damascene metal structure 52 of the metal barrier wall 50 is formed simultaneously with the Mn+! layer and the Vn+ ι metal layer of the wafer 10, and the second inlay of the metal barrier wall 50. The metal structure 52 is formed simultaneously with the Mn layer and the %th metal layer. The first inlaid metal structure 52 is formed by forming a salt-to-high aspect ratio trench in a dielectric layer of the Dn+i 1286354 layer by a copper damascene process, and then filling the trench with copper metal. In accordance with a preferred embodiment of the present invention, the first damascene metal structure 52 and the second damascene metal structure 54 are partially overlapped and staggered, but are not limited thereto. Another feature that is more important in the present invention is that the first inlaid metal structure 52 and the second inlaid metal structure 54 may be hollow structures coated with air, such hollow structures being particularly large when crystal/circular cutting is performed. Part of the stress while protecting the integrity of the wafer. The first inlaid metal structure 52 can be formed into a hollow structure coated with air by controlling the aspect ratio of the trench formed in the dielectric layer of the DN+1 layer. In addition, another feature of the present invention is that the first damascene metal formed in the first +1 dielectric layer and the structure 52 are immersed downward into the dielectric layer, and are formed in the first The second damascene metal structure 54 in the DN layer dielectric layer sinks down into the first dielectric layer. According to another preferred embodiment of the present invention, the opening 3〇 disposed on the opposite sides of the wafer reliability test pad 2〇 and the metal barrier wall 5〇 formed in the opening 3〇 are not limited to the elongated type. It can also be a face, a wave, a plurality of adjacent holes or other irregularities. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. 1286354 [Simple Description of the Drawing] Fig. 1 is an enlarged schematic top view of a portion of a dicing street of a semiconductor wafer. Fig. 2 is a schematic cross-sectional view taken along line I-Ι in Fig. 1. [Major component symbol description]. 10 Semiconductor wafer 12 Integrated circuit wafer 12a Crystal square ring structure 14 Integrated circuit chip 14a Crystal square ring structure 16 Wafer cutting channel 20 Wafer reliability test pad 22 Wafer cutting direction 24 stress direction 30 opening 50 metal barrier wall 52 first inlaid metal structure 54 second inlaid metal structure