TWI507569B - 單晶銅、其製備方法及包含其之基板 - Google Patents

單晶銅、其製備方法及包含其之基板 Download PDF

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TWI507569B
TWI507569B TW102131258A TW102131258A TWI507569B TW I507569 B TWI507569 B TW I507569B TW 102131258 A TW102131258 A TW 102131258A TW 102131258 A TW102131258 A TW 102131258A TW I507569 B TWI507569 B TW I507569B
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copper
substrate
single crystal
crystal copper
cathode
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Chih Chen
King-Ning Tu
Chia Ling Lu
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Univ Nat Chiao Tung
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Description

單晶銅、其製備方法及包含其之基板
本發明係關於一種單晶銅,採用有別於習知技術的方法,於基板上製備出具有[100]方向之大單晶銅,適合應用於凸塊金屬墊層(UBM,under bump metallization)、半導體晶片之內連線(interconnect)、金屬導線或基板線路。
單晶銅係由一個具有固定結晶方向之晶粒所形成,其擁有良好的物理特性,與多晶銅相比,具有較佳的伸長量及低電阻率,且因橫向晶界的消除促使電遷移壽命大幅提升,再加上(100)表面擴散速度較其他晶面慢,故適合應用為封裝凸塊金屬墊層及積體電路之銅內連線,對於積體電路工業應用發展非常有貢獻。
一般來說,金屬的抗電遷能力影響電子元件的可靠度,過去研究發現可透過三種方法提升銅的抗電遷能力,第一種係改變導線晶格結構,使其內部晶粒結構具有一優選方向;第二種係增加晶粒尺寸,使晶粒邊界數量減少而降低原子遷移路徑;第三種係添加奈米雙晶金屬,減緩原子電遷移到雙晶晶界時的流失速度。
關於第一種及第二種方式,習知技術係以脈衝電鍍技術形成單晶銅結構,然而習知技術卻存在兩大缺失,首先,單晶銅晶粒為塊材,無法直接成長於矽基材進而應用於微電子產業,再者,參考近期由Jun Liu等發表的相關文獻,雖指出優化電鍍摻數的脈衝電鍍法能夠控制銅晶體生長方向,且此方法能夠生長出大晶粒的銅,然而卻仍存在有摻雜小晶粒銅的問題,無法完全成長為單晶銅(參考Jun Liu,Changqing Liu,Paul P Conway,"Growth mechanism of copper column by electrodeposition for electronic interconnections," Electronics Systemintegration Technology Conference,p679-84(2008)以及Jun Liu,Changqing Liu,Paul P Conway,Jun Zeng,Changhai Wang," Growth and Recrystallization of Electroplated Copper Columns," International Conference on Electronic Packaging Technology & High Density Packaging,p695-700(2009))。
有鑑於電子製造業發展日新月異,研發具有高度導電特性、低電阻率極高伸長量之單晶銅已成為當務之急,本案發明人研究出更佳的解決方法,不但能以簡單的製程製作具有特定方向之單晶銅,且能突破習知形成單晶銅晶粒尺寸之限制。
本發明之目的係提供一種藉由單晶銅製備方法製備單晶銅及含有單晶銅之基板,俾能透過特殊製程而獲得具有[100]方向之大單晶銅。
為達上述目的,本發明提供一種單晶銅,其具有[100]之方向,且該單晶銅之體積可介於0.1~4.0×106 間,較佳係介於20~1.0×106 間,更佳係介於450~8×105 間。
本發明單晶銅之粒子形狀無特別限制,可為圓柱狀、線狀、立方體、長方體、不規則狀等,若單晶銅為圓柱狀,則直徑可介於1~500μm,較佳係介於5~300μm,更佳係介於10~100μm,若單晶銅為線狀,則該線狀的長度可達700μm。另外,無論該單晶銅之形狀,其厚度可介於0.1~50μm,較佳係介於1~15μm,更佳係介於5~10μm。
上述單晶銅可應用於凸塊金屬墊層(UBM,under bump metallization)、半導體晶片之內連線(interconnect)、金屬導線或基板線路,但無特別限制。
本發明另提供一種製備單晶銅之方法,主要係透過電鍍法於欲形成單晶銅之基板上先形成高密度且晶粒規則排列之一奈米雙晶銅柱,再透過退火處理使奈米雙晶銅柱利用再結晶方式而使晶粒異常成長,進而產生具有[100]方向之大單晶銅顆粒。本發明製備單晶銅之步驟包括:(A)提供一電鍍裝置,該裝置包括一陽極、一陰極、一電鍍液以及一電力供應源,該電力供應源分別與該陽極及該陰極連接,且該陽極及該陰極係浸泡於該電鍍液中,該電鍍液包括:一銅的鹽化物、一酸以及一氯離子來源;(B)使用該電力供應源提供電力進行電鍍,並於該陰極之一表面成長一奈米雙晶銅柱,其中該奈米雙晶 銅柱包含複數個奈米雙晶銅晶粒;以及(C)將形成有該奈米雙晶銅柱之該陰極於350~600℃下進行0.5~3小時之一退火處理,以獲得一單晶銅,其中該單晶銅結晶方向為[100],且體積係介於0.1~4.0×106 間。
於上述步驟(A)中,該陰極可包括一晶種層,其中該晶種層係一銅層,且厚度係0.1~0.3μm,該晶種層可由一物理氣象沉積法(PDV)形成,但無特別限制。
於上述步驟(B)中,該奈米雙晶銅柱係形成於該晶種層上。
於上述步驟(B)中,該奈米雙晶銅柱之成長速率係介於1~3nm/cycle,較佳係介於1.5~2.5nm/cycle。
於上述步驟(B)中,該奈米雙晶銅之厚度可介於0.1~50μm,較佳係介於1~15μm,更佳係介於5~10μm。
於上述步驟(B)中,電力供應源可為一高速脈衝電鍍供應源,且其操作條件為:Ton /Toff (sec)=0.1/2~0.1/0.5,電流密度為0.01~0.2A/cm2 。基本上除了高速脈衝電鍍供應源外,亦可使用直流電電鍍供應源,或兩者交互使用。
於上述步驟(A)之電鍍液中,氯離子主要功能之一係可用以微調整晶粒成長方向,使雙晶金屬具有結晶優選方向。此外,其酸可為一有機或無機酸,以增加電解質濃度而提高電鍍速度,例如可使用硫酸、甲基磺酸、或其混合,此外,電鍍液中的酸之濃度較佳可為80-120g/L。此外,電鍍液須同時包含有銅離子來源(亦即,銅之鹽化物, 例如,硫酸銅或甲基磺酸銅)。該電鍍液較佳的組成中,也可更包括一添加物係選自由:明膠(gelatin)、介面活性劑、晶格修整劑(lattice modification agent)、及其混合所組成之群組,用以調整此些添加物質可用以微調整晶粒成長方向。
於上述步驟(A)中,該銅的鹽化物較佳為硫酸銅。該酸較佳為硫酸、甲基磺酸或其混合,且該酸之濃度較佳為80~120g/L。該基板可選自由:矽基板、玻璃基板、石英基板、金屬基板、塑膠基板、印刷電路板、三五族材料基板及其混合所組成之群組,無特別限制,較佳為矽基板。
本發明另提供一種具有上述單晶銅之基板,其包括一基板;以及上述本發明之單晶銅,該單晶銅係配置於該基板上,可配置為線路狀,或配置為陣列狀,隨著不同應用或需求而改變。在此,單晶銅以及基板之特性與上述相同,不另贅述。
透過本發明製備方法所製得之單晶銅具有[100]方向之大晶粒,其優秀的機械、電、光和熱穩定性及抗電遷移特性能大幅提升產業應用性。
1‧‧‧電鍍裝置
11‧‧‧陽極
12‧‧‧陰極
13‧‧‧電鍍液
14‧‧‧電力供應源
圖1係本發明實施例之電鍍裝置。
圖2A係直徑為17μm之單顆單晶銅之聚焦離子束(FIB)俯視圖。
圖2B係直徑為17μm之單顆單晶銅之EBSD分析結果 圖。
圖3A係直徑為25μm之單晶銅陣列聚焦離子束(FIB)俯視圖。
圖3B係粒徑為25μm之單顆單晶銅之聚焦離子束(FIB)俯視圖。
圖3C係圖3B之聚焦離子束(FIB)剖面圖。
圖3D係圖3A之EBSD分析結果圖。
圖3E係圖3B之EBSD分析結果圖。
圖4係直徑為50μm之單晶銅陣列之EBSD分析結果圖。
圖5A係直徑為100μm之單晶銅陣列之聚焦離子束(FIB)俯視圖。
圖5B係圖5A之EBSD分析結果圖。
以下係藉由具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。此外,本發明亦可藉由其他不同具體實施例加以施行或應用,在不悖離本發明之精神下進行各種修飾與變更。
提供如圖1所示之電鍍裝置1,該電鍍裝置包括:一陽極11、一陰極12、一電鍍液13以及一電力供應源15,該電力供應源14分別與該陽極11及該陰極12連接,且該陽極11及該陰極12係浸泡於該電鍍液13中。
在此,陽極11係選用純度99.99%的商用純銅 靶材,而陰極12為矽晶片,電鍍液13包括硫酸銅(銅離子濃度為20-60g/L)、氯離子(濃度為10-100ppm)、以及甲基磺酸(濃度為80-120g/L),且可選擇性的添加其他介面活性劑或晶格修整劑(如BASF Lugalvan 1-100ml/L)。此外,電鍍液13中更可包含有機酸(例如甲基磺酸)或明膠等。
上述陰極12矽晶片可透過物理氣象沉積法(PVD)沉積厚度為0.2μm之銅膜作為晶種層,以使電鍍電流源只需接觸矽晶片之邊緣附近,即可把電流均勻的傳導至晶片中央,達到晶種層厚度的均勻性。
本實施例之電力供應源14為高速脈衝電鍍供應源,其操作條件為Ton /Toff (sec)為0.1/2~0.1/0.5(例如0.1/2、0.1/1或0.1/0.5),電流密度為0.01~0.2A/cm2 ,最佳為0.05A/cm2 ,於此條件下,以大約2nm/cycle成長速度成長奈米雙晶銅柱,其厚度為6~10μm。接著,圖案化該奈米雙晶銅柱,以於矽晶片上形成奈米雙晶銅柱圖案。基本上,奈米雙晶銅柱的圖案無特別限制,可為為圓柱狀、線狀、立方體、長方體、不規則狀等,且該些圖案可排列為陣列。
接著將表面形成奈米雙晶銅柱的矽晶片置放於高真空(8×10-7 torr)的退火爐管內,溫度維持於400-450℃,0.5~1小時,進行退火處理,以形成具有大粒徑之[100]結晶方向之單晶銅。
圖2A係直徑為17μm之單顆單晶銅晶粒之聚焦離子束(FIB)俯視圖,圖2B係其之EBSD分析結果圖,圖2A、2B之退火處理條件為450℃,60分鐘。由圖2A、2B 可證實本實施例之單晶銅具有[100]方向,且單顆單晶銅體積為1362μm3
圖3A係直徑為25μm之單晶銅陣列聚焦離子束(FIB)俯視圖,圖3B係直徑為25μm之單顆單晶銅之聚焦離子束(FIB)俯視圖,圖3C係圖3B之聚焦離子束(FIB)剖面圖,圖3D係圖3A之EBSD分析結果圖,圖3E係圖3B之EBSD分析結果圖。圖3A至3E之退火處理條件為450℃,60分鐘,由此結果可發現直徑25μm之單晶銅不摻雜其他晶粒,具有[100]方向,且單顆單晶銅體積為2945μm3
圖4係直徑為50μm之單晶銅陣列EBSD分析結果圖。圖4退火條件為450℃,60分鐘,由此結果同樣證實形成直徑為50μm之具有[100]方向之單晶銅,且該單顆單晶銅體積為1.2×104 μm3
圖5A係直徑為100μm之單晶銅陣列聚焦離子束(FIB)俯視圖,圖5B係圖5A之EBSD分析結果圖。由圖5A、5B結果可發現,由本實施例之方法所製成之直徑為100μm的單晶銅同樣具有[100]方向,且單顆單晶銅體積為4.8×104 μm3
由於單晶銅擁有良好的物理特性,與自前應用的多晶銅相比,具有良好的伸長量和低電阻率,並且消除了橫向晶界,從而大大提電遷移壽命。就此,本發明之單晶銅非常適合用於製造IC之銅內連線與凸塊金屬墊層等等,對於積體電路工業之應用發展非常有貢獻。
上述實施例僅係為了方便說明而舉例而已,本 發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。

Claims (15)

  1. 一種單晶銅,該單晶銅具有[100]方向,且體積係介於0.1~4.0×106 μm3 間以及厚度係介於0.1~50μm。
  2. 如申請專利範圍第1項所述之單晶銅,其體積係介於20~1.0×106 μm3
  3. 如申請專利範圍第1項所述之單晶銅,其係應用於凸塊金屬墊層、半導體晶片之內連線(interconnect)、金屬導線或基板線路。
  4. 一種製備單晶銅之方法,其步驟依序包括:(A)提供一電鍍裝置,該裝置包括一陽極、一陰極、一電鍍液以及一電力供應源,該電力供應源分別與該陽極及該陰極連接,且該陽極及該陰極係浸泡於該電鍍液中,該電鍍液包括:一銅的鹽化物、一酸以及一氯離子來源;(B)使用該電力供應源提供電力進行電鍍,並於該陰極之一表面成長一奈米雙晶銅柱,該奈米雙晶銅柱包含複數個奈米雙晶銅晶粒;以及(C)將形成有該奈米雙晶銅柱之該陰極於350~600℃下進行0.5~3小時之一退火處理,以獲得一單晶銅,其中該單晶銅具有[100]之方向,且體積係介於0.1~4.0×106 μm3 間以及厚度係介於0.1~50μm;其中步驟(A)之該酸之濃度為80~120g/L;其中步驟(B)之該電力供應源係一高速脈衝電鍍供應源,且其操作條件為:Ton/Toff(sec)=0.1/2~0.1/0.5,電流密度為0.01~0.2A/cm2
  5. 如申請專利範圍第4項所述之方法,其中於步驟(A)中,該陰極包括一晶種層,其中該晶種層係一銅層,且厚度係0.1~0.3μm,該晶種層係由一物理氣象沉積法(PVD)形成。
  6. 如申請專利範圍第5項所述之方法,其中於步驟(B)中,該奈米雙晶銅金屬柱係形成於該晶種層上。
  7. 如申請專利範圍第4項所述之方法,於步驟(B)中,該奈米雙晶銅金屬柱之成長速率係介於1~3nm/cycle。
  8. 如申請專利範圍第4項所述之方法,於步驟(B)中,該奈米雙晶銅金屬柱之厚度係5~15μm。
  9. 如申請專利範圍第4項所述之方法,其中該單晶銅之體積係介於20~1.0×106 μm3 間。
  10. 如申請專利範圍第4項所述之方法,其中步驟(A)之該電鍍液更包括一明膠(gelatin)、一介面活性劑、一晶格修飾劑或其混合物。
  11. 如申請專利範圍第4項所述之方法,其中步驟(A)之該銅的鹽化物係硫酸銅。
  12. 如申請專利範圍第4項所述之方法,其中步驟(A)之該酸為硫酸、甲基磺酸、或其混合。
  13. 如申請專利範圍第4項所述之方法,於步驟(A)中,該基板係選自由:矽基板、玻璃基板、石英基板、金屬基板、塑膠基板、印刷電路板、三五族材料基板及其混合所組成之群組。
  14. 一種具有單晶銅之基板,係包括:一基板;以及 一如申請專利範圍第1~3項任一項所述之單晶銅,且該單晶銅晶粒係配置於該基板上。
  15. 如申請專利範圍第14項所述之具有單晶銅之基板,其中該基板係選自由:矽基板、玻璃基板、石英基板、金屬基板、塑膠基板、印刷電路板、三五族材料基板及其混合所組成之群組。
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