TWI443355B - 用於嵌入式基板之邊界掃描測試裝置及方法 - Google Patents

用於嵌入式基板之邊界掃描測試裝置及方法 Download PDF

Info

Publication number
TWI443355B
TWI443355B TW100131886A TW100131886A TWI443355B TW I443355 B TWI443355 B TW I443355B TW 100131886 A TW100131886 A TW 100131886A TW 100131886 A TW100131886 A TW 100131886A TW I443355 B TWI443355 B TW I443355B
Authority
TW
Taiwan
Prior art keywords
test
wafer
embedded
boundary scan
semiconductor wafer
Prior art date
Application number
TW100131886A
Other languages
English (en)
Chinese (zh)
Other versions
TW201224483A (en
Inventor
Hyun Ho Kim
Won Geun Jung
Yul Kyo Chung
Tae Sung Jeong
Original Assignee
Samsung Electro Mech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of TW201224483A publication Critical patent/TW201224483A/zh
Application granted granted Critical
Publication of TWI443355B publication Critical patent/TWI443355B/zh

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW100131886A 2010-09-27 2011-09-05 用於嵌入式基板之邊界掃描測試裝置及方法 TWI443355B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100093133A KR101222737B1 (ko) 2010-09-27 2010-09-27 내장형 기판의 경계 스캔 테스트 장치 및 그 방법

Publications (2)

Publication Number Publication Date
TW201224483A TW201224483A (en) 2012-06-16
TWI443355B true TWI443355B (zh) 2014-07-01

Family

ID=45804928

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100131886A TWI443355B (zh) 2010-09-27 2011-09-05 用於嵌入式基板之邊界掃描測試裝置及方法

Country Status (3)

Country Link
KR (1) KR101222737B1 (ko)
DE (1) DE102011113305A1 (ko)
TW (1) TWI443355B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453442B (zh) * 2012-10-18 2014-09-21 Inventec Corp 基於邊界掃描的晶片連接測試系統及其方法
CN111027057B (zh) * 2019-01-31 2023-12-26 安天科技集团股份有限公司 一种芯片隐藏硬件的检测方法、装置及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW253097B (ko) * 1992-03-02 1995-08-01 At & T Corp
KR100213230B1 (ko) * 1997-01-29 1999-08-02 윤종용 코어 및 메모리 내장 회로용 테스트 방법
US5793778A (en) * 1997-04-11 1998-08-11 National Semiconductor Corporation Method and apparatus for testing analog and digital circuitry within a larger circuit
AU2001232778A1 (en) * 2000-01-21 2001-07-31 Sun Microsystems, Inc. A printed circuit assembly with configurable boundary scan paths
JP2009169896A (ja) 2008-01-21 2009-07-30 Sharp Corp サーバ、システム、及びコンテンツ表示制御方法

Also Published As

Publication number Publication date
KR101222737B1 (ko) 2013-01-15
KR20120031644A (ko) 2012-04-04
DE102011113305A1 (de) 2012-03-29
TW201224483A (en) 2012-06-16

Similar Documents

Publication Publication Date Title
US7098682B2 (en) Testing method and tester for semiconductor integrated circuit device comprising high-speed input/output element
KR101177133B1 (ko) 모의 웨이퍼, 시스템 및 자동 테스트 장비를 조정하는 방법
KR101384714B1 (ko) 반도체 검사장치
TWI432755B (zh) 測試系統及印刷電路板組件之測試方法
JP2008517267A (ja) 半導体デバイステスタのためのインターフェース装置
JP2011128159A (ja) 信号測定方法及び装置
TW201539637A (zh) 測試分選機及其推進裝置、測試托盤以及測試機用接口板
US6343365B1 (en) Large-scale integrated circuit and method for testing a board of same
KR20130042076A (ko) 반도체 장치
US20200174073A1 (en) Device inspection method
Renbi et al. Contactless testing of circuit interconnects
TWI443355B (zh) 用於嵌入式基板之邊界掃描測試裝置及方法
US8860448B2 (en) Test schemes and apparatus for passive interposers
JP2004069650A (ja) 変換装置
KR20140078170A (ko) 제이택 인터페이스 보드
JP2007322127A (ja) 基板検査方法及び基板検査装置
KR102216917B1 (ko) 피검사 장치와의 무선 주파수 신호 접속성 확인 시스템 및 방법
JP5319907B2 (ja) ソケット基板上にスイッチ素子を有するテスト装置
JP2007114163A (ja) マルチチップパッケージｌｓｉ
JP2011185746A (ja) プリント基板の検査方法及びこれに用いる検査装置
US9341668B1 (en) Integrated circuit package testing
JP6520127B2 (ja) 基板検査装置、基板検査方法及び基板検査用治具
JP4525125B2 (ja) マルチチップ型半導体装置
KR100979502B1 (ko) 프로브카드용 기판
JP4137082B2 (ja) 半導体装置の試験装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees