TWI443355B - Boundary scan test apparatus and method for embedded substrate - Google Patents
Boundary scan test apparatus and method for embedded substrate Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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Description
本申請案主張於2010年9月27日向韓國智慧財產局所提出之韓國專利申請案10-2010-0093133號，案名“用於嵌入式基板之邊界掃描測試裝置及方法(Boundary Scan Test Apparatus and Method for Embedded Substrate)”之優先權，該案之整個內容在此一併提出以供參考。This application claims Korean Patent Application No. 10-2010-0093133 filed on Sep. 27, 2010, to the Korean Intellectual Property Office, entitled "Boundary Scan Test Apparatus and Method for Embedded Substrates" For Embedded Substrate), the entire content of the case is hereby incorporated by reference.
本發明係關於用於嵌入式基板之邊界掃描測試裝置及方法。The present invention relates to a boundary scan test apparatus and method for an embedded substrate.
一般而言，表示於基板上貼裝組件之技術的電子組件表面貼裝技術(SMT)可說廣布於幾乎所有電子產品(譬如家電設備、電腦、通訊裝置、航空工業等)的半導體領域之核心技術。In general, the surface mount technology (SMT) of electronic components, which means the technology of mounting components on a substrate, can be said to be widely distributed in the semiconductor field of almost all electronic products (such as home appliances, computers, communication devices, aviation industry, etc.). Core Technology.
於此表面貼裝技術，依照持續的需求最小化板之大小，為了增加於相同基板上組件之貼裝密度，近來已經發展了半導體晶片等嵌入於基板中之嵌入式基板。In this surface mount technology, the size of the board is minimized in accordance with the continuous demand, and in order to increase the mounting density of the components on the same substrate, an embedded substrate in which a semiconductor wafer or the like is embedded in the substrate has recently been developed.
依照先前技術，於嵌入式基板中，為了確認於完成表面貼裝製程後各組件是否滿意地正常安裝於基板上，係透過電阻測量而主要執行短路/斷接測試。According to the prior art, in the embedded substrate, in order to confirm whether the components are satisfactorily mounted on the substrate after completion of the surface mount process, the short-circuit/disconnection test is mainly performed through the resistance measurement.
依照先前技術於短路/斷接測試情況，主要實行於嵌入式基板之電路圖案之短路/斷接測試，而非於嵌入式基板之半導體晶片上之功能測試。因此，依照先前技術很難對於嵌入式基板上之功能測試上施予短路/斷接測試。According to the prior art, in the short circuit/disconnection test case, the short circuit/disconnection test of the circuit pattern of the embedded substrate is mainly performed, instead of the functional test on the semiconductor wafer of the embedded substrate. Therefore, it is difficult to apply a short/disconnection test to the functional test on the embedded substrate in accordance with the prior art.
本發明致力於提供一種用於嵌入式基板之邊界掃描測試裝置和方法，於此裝置和方法中藉由令使可在嵌入於基板中半導體晶片上作邊界掃描測試而可以快速和可靠地執行於嵌入式基板上之功能測試，該裝置和方法將使用具有邊界掃描測試功能之晶片執行。The present invention is directed to a boundary scan test apparatus and method for an embedded substrate that can be quickly and reliably performed by enabling boundary scan testing on a semiconductor wafer embedded in a substrate. Functional testing on an embedded substrate, the device and method will be performed using a wafer with boundary scan test functionality.
依照本發明之第一個較佳實施例，提供一種用於嵌入式基板之邊界掃描測試裝置，該邊界掃描測試裝置包含：具有半導體晶片嵌入於其中之嵌入式基板，該半導體晶片為待測試之目標物；測試晶片，執行在嵌入於該嵌入式基板中之該半導體晶片之邊界掃描測試；以及測試控制器，控制該測試晶片以讓該邊界掃描測試在嵌入於該嵌入式基板中之該半導體晶片上執行。According to a first preferred embodiment of the present invention, a boundary scan test apparatus for an embedded substrate is provided. The boundary scan test apparatus includes: an embedded substrate having a semiconductor wafer embedded therein, the semiconductor wafer being tested a target wafer; performing a boundary scan test on the semiconductor wafer embedded in the embedded substrate; and a test controller controlling the test wafer to allow the boundary scan to test the semiconductor embedded in the embedded substrate Executed on the wafer.
當設置有複數個嵌入式基板時，可以設置對應於該複數個嵌入式基板之複數個測試晶片，而該複數個測試晶片之測試輸入端子和測試輸出端子可以彼此連接由此形成一鏈路(chain)。When a plurality of embedded substrates are disposed, a plurality of test wafers corresponding to the plurality of embedded substrates may be disposed, and the test input terminals and the test output terminals of the plurality of test chips may be connected to each other to form a link ( Chain).
該測試晶片可包含：第一探測器，連接至該嵌入式基板之一個表面上之接觸點用於該嵌入式基板上該邊界掃描測試；以及第二探測器，連接至該嵌入式基板之另一個表面上之接觸點用於該嵌入式基板上該邊界掃描測試。The test wafer may include: a first detector, a contact point connected to one surface of the embedded substrate for the boundary scan test on the embedded substrate; and a second detector connected to the embedded substrate A contact point on a surface is used for the boundary scan test on the embedded substrate.
當複數個半導體晶片嵌入於該嵌入式基板中時，其輸入和輸出端子可以彼此連接由此形成一鏈路。When a plurality of semiconductor wafers are embedded in the embedded substrate, their input and output terminals can be connected to each other thereby forming a link.
該測試晶片可嵌入於該嵌入式基板中。The test wafer can be embedded in the embedded substrate.
該測試控制器可於該測試晶片控制半導體晶片之狀態對對該測試晶片施用測試資料，以便使輸入和輸出端子與該半導體晶片之內部核心邏輯彼此分離，而令使施用的測試資料經由半導體晶片輸出，由此測試基板連接狀態。The test controller can apply test data to the test wafer in a state in which the test wafer controls the semiconductor wafer to separate the input and output terminals from the internal core logic of the semiconductor wafer, and cause the applied test data to pass through the semiconductor wafer. Output, thereby testing the substrate connection state.
該測試控制器可對該測試晶片施用功能執行命令，並且接收該半導體晶片依照施用功能執行命令之執行結果，由此執行該半導體晶片之功能測試。The test controller can apply a function execution command to the test wafer and receive a result of execution of the semiconductor wafer in accordance with an application function execution command, thereby performing a functional test of the semiconductor wafer.
依照本發明之第二個較佳實施例，提供一種用於嵌入式基板之邊界掃描測試方法，該邊界掃描測試方法包含：(A)藉由電性連接嵌入於該嵌入式基板中之該半導體晶片、測試晶片、和測試控制器而建立邊界掃描測試環境；(B)令使該測試控制器可於該輸入和輸出端子與該半導體晶片之內部核心邏輯彼此分離之狀態下對該測試晶片施用測試資料，藉此測試基板連接狀態；以及(C)令使該測試控制器可對該測試晶片施用功能執行命令，由此執行該半導體晶片之功能測試。According to a second preferred embodiment of the present invention, a boundary scan test method for an embedded substrate is provided. The boundary scan test method includes: (A) electrically connecting the semiconductor embedded in the embedded substrate a wafer, a test wafer, and a test controller to establish a boundary scan test environment; (B) enabling the test controller to apply the test wafer to the input and output terminals and the internal core logic of the semiconductor wafer Test data, thereby testing the substrate connection state; and (C) enabling the test controller to apply a function execution command to the test wafer, thereby performing a functional test of the semiconductor wafer.
該測試晶片可嵌入於該嵌入式基板中。The test wafer can be embedded in the embedded substrate.
步驟(B)可以包含：(B-1)令使該測試控制器可對該測試晶片施用外部邊界掃描測試模式選擇訊號；(B-2)令使該測試晶片可以控制該半導體晶片以便使輸入和輸出端子與該內部核心邏輯彼此分離；(B-3)令使該測試控制器可對該測試晶片施用該測試資料；(B-4)令使該測試晶片可對該半導體晶片施用該測試資料，接收反應訊號至該測試資料，並且傳送該測試之資料至該測試控制器；以及(B-5)令使該測試晶片可以將施用於該半導體晶片之該測試資料與該反應訊號彼此比較，由此測試基板連接狀態。Step (B) may comprise: (B-1) enabling the test controller to apply an external boundary scan test mode selection signal to the test wafer; (B-2) enabling the test wafer to control the semiconductor wafer for input And the output terminal and the internal core logic are separated from each other; (B-3) enabling the test controller to apply the test data to the test wafer; (B-4) enabling the test wafer to apply the test to the semiconductor wafer Receiving a response signal to the test data, and transmitting the test data to the test controller; and (B-5) enabling the test wafer to compare the test data applied to the semiconductor wafer with the reaction signal Thereby, the substrate connection state is tested.
於步驟(B-4)，當複數個半導體晶片嵌入於該嵌入式基板中且彼此連接為一鏈路時，該測試資料可以輸出為通過該複數個半導體晶片至該測試晶片的反應訊號。In step (B-4), when a plurality of semiconductor wafers are embedded in the embedded substrate and connected to each other as a link, the test data may be output as a reaction signal passing through the plurality of semiconductor wafers to the test wafer.
步驟(C)可以包含：(C-1)令使該測試控制器對該測試晶片施用內部邊界掃描測試模式選擇訊號；(C-2)令使該測試控制器對該測試晶片施用該功能執行命令；(C-3)令使該測試晶片對該半導體晶片施用該功能執行命令，接收執行之結果，並且傳送該接收之執行結果至該測試控制器；以及(C-5)令使該測試晶片將施用於該半導體晶片之該功能執行命令與該執行結果做比較，由此執行該功能測試。Step (C) may comprise: (C-1) causing the test controller to apply an internal boundary scan test mode selection signal to the test wafer; (C-2) causing the test controller to perform the function execution on the test wafer Command (C-3) causing the test wafer to apply the function execution command to the semiconductor wafer, receiving the result of the execution, and transmitting the received execution result to the test controller; and (C-5) ordering the test The function compares the function execution command applied to the semiconductor wafer with the execution result, thereby performing the function test.
於步驟(C-3)，當複數個半導體晶片嵌入於該嵌入式基板中和彼此連接為一鏈路時，該功能執行命令可以輸出為該執行結果通過該複數個半導體晶片至該測試晶片。In step (C-3), when a plurality of semiconductor wafers are embedded in the embedded substrate and connected to each other as a link, the function execution command may output the result of the execution through the plurality of semiconductor wafers to the test wafer.
本說明書和申請專利範圍中使用的詞語和文字應該不解釋為限制於典型的含意或字典定義，而是應該解釋為根據依照發明者可以適當地定義該詞語之概念之最適當說明他(或她)所知道實施本發明之最佳方法之規則之具有相關於本發明之技術範圍之含意和概念。Words and characters used in the specification and claims should not be construed as limited to a typical meaning or dictionary definition, but rather should be interpreted as the most appropriate description of the concept of the word according to the inventor. It is to be understood that the rules for carrying out the best mode of the invention have the meaning and concept of the technical scope of the invention.
由下列之詳細說明結合所附圖式，本發明之上述和其他目的、特徵和優點將變得更清楚了解。除了遍及圖式中諸組件之元件符號外，應該注意到即使組件顯示於不同的圖式中，相同之元件符號係表示相同之組件。再者，當判定相關於本發明之已知技術之詳細說明也許模糊了本發明之要旨時，則將省略其詳細說明。The above and other objects, features and advantages of the present invention will become more apparent from In addition to the component symbols of the components in the drawings, it should be noted that even if the components are shown in different drawings, the same component symbols represent the same components. Further, when it is determined that the detailed description of the known art related to the present invention may obscure the gist of the present invention, the detailed description thereof will be omitted.
下文中，將參照所附圖式詳細說明本發明之較佳實施例。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第1圖為依照本發明之較佳實施例用於嵌入式基板之邊界掃描測試裝置之組構圖。1 is a block diagram of a boundary scan test apparatus for an embedded substrate in accordance with a preferred embodiment of the present invention.
依照如第1圖中所示之本發明之第一個較佳實施例用於嵌入式基板之邊界掃描測試裝置包含具有半導體晶片嵌入於其中之複數個嵌入式基板1，該半導體晶片為待測試之目標物，複數個測試晶片2執行在嵌入於該複數個嵌入式基板1中之半導體晶片之邊界掃描測試，以及測試控制器3控制該複數個測試晶片2以讓該邊界掃描測試在嵌入於該複數個嵌入式基板中1之該半導體晶片上執行。A boundary scan test apparatus for an embedded substrate according to a first preferred embodiment of the present invention as shown in FIG. 1 includes a plurality of embedded substrates 1 having a semiconductor wafer embedded therein, the semiconductor wafer being tested Targets, a plurality of test wafers 2 perform boundary scan tests on semiconductor wafers embedded in the plurality of embedded substrates 1, and a test controller 3 controls the plurality of test wafers 2 to allow the boundary scan test to be embedded in Executing on the semiconductor wafer of one of the plurality of embedded substrates.
於此種組構中，嵌入式基板1包含複數個嵌入於其中之半導體晶片，其中該嵌入於該嵌入式基板1中之該半導體晶片包含沒有邊界掃描測試功能之半導體晶片。In this configuration, the embedded substrate 1 includes a plurality of semiconductor wafers embedded therein, wherein the semiconductor wafer embedded in the embedded substrate 1 includes a semiconductor wafer having no boundary scan test function.
嵌入式基板1之一個例子顯示於第2圖中。顯示於第2圖中之嵌入式基板由絕緣材料製成，並且包含第一絕緣層10，該第一絕緣層10包含嵌入於其中之複數個半導體晶片20a至20c和形成於其中之複數個貫通孔12；第一電路層11a和11b形成在該第一絕緣層10之二個側邊；第二絕緣層13a和13b疊置在該第一電路層11a和11b上並且包含複數個貫通孔15a和15b形成於其中；第二電路層14a和14b形成在該第二絕緣層13a和13b上；第三絕緣層16a和16b疊置在該第二電路層14a和14b上並且包含複數個貫通孔18a和18b形成於其中；第三電路層17a和17b形成於該第三絕緣層16a和16b上，以及阻焊層19a和19b覆蓋該第三電路層17a和17b。An example of the embedded substrate 1 is shown in Fig. 2. The embedded substrate shown in FIG. 2 is made of an insulating material and includes a first insulating layer 10 including a plurality of semiconductor wafers 20a to 20c embedded therein and a plurality of through-holes formed therein a hole 12; first circuit layers 11a and 11b are formed on two sides of the first insulating layer 10; second insulating layers 13a and 13b are stacked on the first circuit layers 11a and 11b and include a plurality of through holes 15a And 15b are formed therein; second circuit layers 14a and 14b are formed on the second insulating layers 13a and 13b; third insulating layers 16a and 16b are stacked on the second circuit layers 14a and 14b and include a plurality of through holes 18a and 18b are formed therein; third circuit layers 17a and 17b are formed on the third insulating layers 16a and 16b, and solder resist layers 19a and 19b cover the third circuit layers 17a and 17b.
嵌入式基板1包含6個網路形成於其中，如第2圖中虛線所示。於此種組構中，因為網路1、2、和4未連接至嵌入之半導體晶片20a至20c，因此即使施行依照先前技術之斷接/短路測試，亦可以獲得於基板連接狀態所希望之測試結果。The embedded substrate 1 includes six networks formed therein as indicated by a broken line in FIG. In this configuration, since the networks 1, 2, and 4 are not connected to the embedded semiconductor wafers 20a to 20c, even if the disconnection/short-circuit test according to the prior art is performed, it is possible to obtain the desired connection state of the substrate. Test Results.
然而，因為網路3、5、和6連接至半導體晶片20a至20c，因此藉由依照先前技術之斷接/短路測試不可以獲得於基板連接狀態所希望之測試結果。於網路3、5、和6之情況，依照本發明之較佳實施例之測試晶片被使用來執行邊界掃描測試，從而有可能於半導體晶片20a至20c上確認基板連接狀態並且亦執行功能測試。However, since the networks 3, 5, and 6 are connected to the semiconductor wafers 20a to 20c, the desired test results in the substrate connection state are not obtained by the disconnect/short test according to the prior art. In the case of the networks 3, 5, and 6, the test wafer according to the preferred embodiment of the present invention is used to perform the boundary scan test, thereby making it possible to confirm the substrate connection state on the semiconductor wafers 20a to 20c and also perform the functional test. .
欲達此目的，當設置複數個半導體晶片20a至20c時，他們必須彼此連接藉此形成一鏈路。回到第2圖，由元件符號20a表示之半導體晶片和由元件符號20b表示之半導體晶片藉由網路5彼此連接而由此形成鏈路，以及由元件符號20b表示之半導體晶片和由元件符號20c表示之半導體晶片藉由網路6彼此連接而由此形成鏈路。To this end, when a plurality of semiconductor wafers 20a to 20c are provided, they must be connected to each other to form a link. Returning to Fig. 2, the semiconductor wafer indicated by the component symbol 20a and the semiconductor wafer indicated by the component symbol 20b are connected to each other by the network 5, thereby forming a link, and the semiconductor wafer and the component symbol represented by the component symbol 20b. The semiconductor wafers indicated by 20c are connected to each other by the network 6, thereby forming a link.
因此，當測試晶片之輸入訊號施用於由元件符號20a表示之半導體晶片和對測試晶片之輸入訊號之反應訊號於由元件符號20c所表示之半導體晶片中被接收和分析時，則可以確認半導體晶片之間之連接狀態或半導體晶片之功能是否平穩執行。Therefore, when the input signal of the test wafer is applied to the semiconductor wafer indicated by the component symbol 20a and the reaction signal to the test chip is received and analyzed in the semiconductor wafer indicated by the component symbol 20c, the semiconductor wafer can be confirmed. Whether the connection state or the function of the semiconductor wafer is smoothly performed.
同時，該複數個測試晶片2包含上部探測器2-1，該上部探測器2-1可以接觸用於測試嵌入式基板1之上表面之接點，和下部探測器2-2，該下部探測器2-2可以接觸用於測試嵌入式基板1之下表面之接點。Meanwhile, the plurality of test wafers 2 include an upper detector 2-1 which can contact a contact for testing the upper surface of the embedded substrate 1, and a lower detector 2-2, the lower detector The device 2-2 can contact the contacts for testing the lower surface of the embedded substrate 1.
此外，複數個測試晶片2包含邊界掃描測試功能，並且透過該上部和下部探測器2-1和2-2連接至嵌入於該嵌入式基板1中之該半導體晶片，由此執行邊界掃描測試。Further, a plurality of test wafers 2 include a boundary scan test function, and are connected to the semiconductor wafer embedded in the embedded substrate 1 through the upper and lower detectors 2-1 and 2-2, thereby performing a boundary scan test.
測試晶片2之一個例子顯示於第3圖中。測試晶片2包含核心邏輯21用於獨特的運作，和複數個邊界掃描單元22彼此結合用來測試其中之輸入和輸出端子之間。於一般之邊界掃描測試操作中，資料可以通過核心邏輯21與訊號接腳之間之邊界掃描單元22通過測試晶片而不受核心邏輯21之影響。An example of test wafer 2 is shown in Figure 3. Test wafer 2 includes core logic 21 for unique operation, and a plurality of boundary scan units 22 are used in conjunction with one another to test between the input and output terminals therein. In a typical boundary scan test operation, data can pass through the test wafer through the boundary scan unit 22 between the core logic 21 and the signal pins without being affected by the core logic 21.
於邊界掃描測試操作過程中，測試資料通過測試資料輸入(TDI)接腳輸入至測試晶片2，通過邊界掃描單元22之鏈路，並且通過測試資料輸出(TDO)接腳從測試晶片2輸出。During the boundary scan test operation, the test data is input to the test wafer 2 through a test data input (TDI) pin, through the link of the boundary scan unit 22, and output from the test wafer 2 through a test data output (TDO) pin.
複數個測試晶片2藉由耦接TDO接腳之輸出至TDI接腳之輸入而彼此結合，如第1圖中所示。A plurality of test wafers 2 are coupled to each other by coupling the outputs of the TDO pins to the inputs of the TDI pins, as shown in FIG.
測試晶片2可以定位於嵌入式基板30之外側，該嵌入式基板30包含嵌入於其絕緣層31中之半導體晶片32a和32b和形成於其二個表面之電路層31a和31b，如第4圖中所示。此處，由元件符號32a表示之半導體晶片之輸出端子連接至由元件符號32b表示之半導體晶片之輸入端子，而令使半導體晶片32a和32b形成鏈路。測試晶片2可以施用訊號至由元件符號32a表示之半導體晶片，並且接收從由元件符號32b表示之半導體晶片來之訊號施用的結果，反之亦然。The test wafer 2 may be positioned on the outer side of the embedded substrate 30, the embedded substrate 30 including the semiconductor wafers 32a and 32b embedded in the insulating layer 31 thereof and the circuit layers 31a and 31b formed on the two surfaces thereof, as shown in FIG. Shown in . Here, the output terminal of the semiconductor wafer indicated by the component symbol 32a is connected to the input terminal of the semiconductor wafer indicated by the component symbol 32b, so that the semiconductor wafers 32a and 32b are formed into a link. The test wafer 2 can apply a signal to the semiconductor wafer indicated by the component symbol 32a and receive the result of the signal application from the semiconductor wafer indicated by the component symbol 32b, and vice versa.
同時，不像上述情況，測試晶片2可以嵌入於該嵌入式基板30中，該嵌入式基板30包含嵌入於其絕緣層31中之半導體晶片32a和32b和形成於其二個表面之電路層31a和31b，如第5圖中所示。Meanwhile, unlike the above case, the test wafer 2 may be embedded in the embedded substrate 30, which includes the semiconductor wafers 32a and 32b embedded in the insulating layer 31 thereof and the circuit layer 31a formed on the two surfaces thereof. And 31b, as shown in Figure 5.
其次，測試控制器3可以於複數個嵌入式基板上執行測試，同時控制複數個測試晶片2。Second, the test controller 3 can perform tests on a plurality of embedded substrates while controlling a plurality of test wafers 2.
複數個測試控制器3為了令使測試晶片2可以是在測試模式而提供測試模式選擇(test mode select，TMS)訊號至測試晶片2，並且為了透過掃描單元之鏈路移位資料而提供測試時脈(test clock，TCK)。A plurality of test controllers 3 provide a test mode select (TMS) signal to the test chip 2 in order to enable the test chip 2 to be in the test mode, and provide test time for shifting the data through the link of the scan unit. Test clock (TCK).
將說明如上述用於嵌入式基板之邊界掃描測試裝置之操作。The operation of the boundary scan test apparatus for an embedded substrate as described above will be explained.
首先，測試控制器3為了令使測試晶片2可以是在測試模式而提供TMS訊號至測試晶片2，並且為了透過掃描單元之鏈路移位資料而提供TCK。此外，測試控制器3施測試晶片2施用用於TDI接腳之測試或診斷的資料。First, the test controller 3 provides a TMS signal to the test wafer 2 in order to enable the test wafer 2 to be in the test mode, and provides a TCK for shifting the data through the link of the scan unit. Further, the test controller 3 applies the test wafer 2 to apply data for testing or diagnosis of the TDI pin.
然後，各個測試晶片2係用作為移位暫存器，而令使資料位元從一個測試晶片2移位至次一個測試晶片2。Then, each test wafer 2 is used as a shift register to shift the data bits from one test wafer 2 to the next test wafer 2.
於掃描移位期間可以透過其關聯於輸出或雙向訊號之訊號接腳而監視各自的測試晶片2之狀態。The state of the respective test wafer 2 can be monitored during its scan shift by its signal pins associated with the output or bidirectional signals.
舉例而言，於邊界掃描測試過程中，當資料位元藉由測試控制器3通過邊界掃描路由而移位時，可以透過關聯之訊號接腳監視各自測試晶片2之狀態。For example, during the boundary scan test, when the data bits are shifted by the test controller 3 through the boundary scan route, the status of the respective test wafers 2 can be monitored through the associated signal pins.
於資料通過邊界掃描路由之移位期間，各自的測試晶片2通常將執行邏輯高位準和邏輯低位準之間之多次反轉。當有缺陷時(譬如無連接訊號接腳)，測試控制器3可以於預定的時間不偵測期望於對應單元之狀態，由此導致測試失敗。於此設計中可以偵測缺陷的訊號連接。During the shift of the data through the boundary scan route, the respective test wafer 2 will typically perform multiple inversions between the logic high level and the logic low level. When there is a defect (such as no connection signal pin), the test controller 3 may not detect the state expected of the corresponding unit at a predetermined time, thereby causing the test to fail. Defective signal connections can be detected in this design.
於輸入訊號中，測試資料可以通過關聯之訊號接腳移動入測試晶片2中，並且於通過連接之測試晶片2移位後可以通過TDO接腳被監視。於測試控制器3與測試晶片2之間透過上述過程協作下，可以執行於嵌入於該嵌入式基板1中之該半導體晶片上測試。In the input signal, the test data can be moved into the test wafer 2 through the associated signal pin, and can be monitored through the TDO pin after being shifted by the connected test wafer 2. Between the test controller 3 and the test wafer 2, the semiconductor wafer embedded in the embedded substrate 1 can be tested by cooperation with the above process.
詳言之，藉由測試控制器3執行於嵌入式基板2上基板連接狀態測試和功能測試。In detail, the substrate connection state test and the functional test on the embedded substrate 2 are performed by the test controller 3.
為了執行基板連接狀態測試，測試控制器3選擇邊界掃描測試模式作為外部邊界掃描測試(EXTEST)模式，而令使嵌入於該嵌入式基板1中之該半導體晶片之內部核心邏輯藉由測試晶片2之控制而與輸入和輸出端子分離。In order to perform the substrate connection state test, the test controller 3 selects the boundary scan test mode as the external boundary scan test (EXTEST) mode, and causes the internal core logic of the semiconductor wafer embedded in the embedded substrate 1 to pass the test wafer 2 It is controlled to be separated from the input and output terminals.
當測試控制器3於邊界掃描測試模式選擇為外部邊界掃描測試模式之狀態下，透過測試資料輸入端子對測試晶片2輸入用於基板連接狀態測試之預定的測試資料時，該測試資料被載入至嵌入式基板1之半導體晶片，然後經由半導體晶片之內側(於其中該複數個半導體晶片被嵌入於該嵌入式基板1中並且彼此連接為鏈路之情況經由複數個嵌入式半導體晶片)輸出該測試晶片。When the test controller 3 selects the predetermined test data for the substrate connection state test on the test wafer 2 through the test data input terminal in the state where the boundary scan test mode is selected as the external boundary scan test mode, the test data is loaded. The semiconductor wafer to the embedded substrate 1 is then output via the inner side of the semiconductor wafer (in the case where the plurality of semiconductor wafers are embedded in the embedded substrate 1 and connected to each other as a link via a plurality of embedded semiconductor wafers) Test the wafer.
因此，測試晶片2透過該測資料輸出端子輸出接收之反應訊號至該測試控制器3。Therefore, the test chip 2 outputs the received reaction signal to the test controller 3 through the data output terminal.
然後，測試控制器3比較通過測試晶片2輸入至嵌入於該嵌入式基板1中之該半導體晶片之測試資料與從嵌入於該嵌入式基板1中之該半導體晶片輸出之測試資料，由此測試嵌入式半導體晶片之間連接狀態。Then, the test controller 3 compares the test data input to the semiconductor wafer embedded in the embedded substrate 1 through the test wafer 2 with the test data output from the semiconductor wafer embedded in the embedded substrate 1, thereby testing The state of connection between embedded semiconductor wafers.
其次，為了執行功能測試，測試控制器3選擇邊界掃描測試模式作為內部邊界掃描測試模式，而令使嵌入於該嵌入式基板1中之該半導體晶片之內部核心邏輯維持於其連接至輸入和輸出端子之狀態。Secondly, in order to perform the functional test, the test controller 3 selects the boundary scan test mode as the internal boundary scan test mode, so that the internal core logic of the semiconductor chip embedded in the embedded substrate 1 is maintained at its connection to the input and output. The status of the terminal.
當測試控制器3輸入測試資料，也就是，測試功能執行命令用於預定的功能測試通過測試資料輸入端子至測試晶片2，於其中邊界掃描測試模式被選擇為內部邊界掃描測試模式之狀態，該測試晶片2通過嵌入於該嵌入式基板1中之該半導體晶片之輸入端子轉移該測試功能執行命令至該半導體晶片之內部核心邏輯。When the test controller 3 inputs the test data, that is, the test function execution command is used for the predetermined function test through the test data input terminal to the test wafer 2, wherein the boundary scan test mode is selected as the state of the internal boundary scan test mode, The test wafer 2 transfers the test function execution command to the internal core logic of the semiconductor wafer through an input terminal of the semiconductor chip embedded in the embedded substrate 1.
因此，半導體晶片之內部核心邏輯依照轉移之測試功能執行命令執行對應的功能，並且通過輸出端子輸出執行之結果至該測試晶片2，並且接收執行結果之測試晶片2傳送該執行之結果至測試控制器3。此處，當於嵌入式基板1中之複數個半導體晶片彼此連接於鏈路形式，而其功能彼此機構地耦接時，則重複上述過程，而令使於最末端之半導體晶片通過其輸出端子傳送執行結果至測試晶片2。Therefore, the internal core logic of the semiconductor wafer executes the command in accordance with the transferred test function to execute the corresponding function, and outputs the executed result to the test wafer 2 through the output terminal, and the test wafer 2 that receives the execution result transmits the result of the execution to the test control. Device 3. Here, when a plurality of semiconductor wafers in the embedded substrate 1 are connected to each other in a link form, and their functions are mechanically coupled to each other, the above process is repeated, and the semiconductor chip at the end is passed through its output terminal. The execution result is transferred to the test wafer 2.
然後，測試控制器3決定是否獲得適合用於輸入功能執行命令之結果，由此決定是否嵌入於該嵌入式基板中之該半導體晶片被正常操作。Then, the test controller 3 decides whether or not a result suitable for the input function execution command is obtained, thereby determining whether or not the semiconductor wafer embedded in the embedded substrate is normally operated.
第6圖為依照本發明之較佳實施例用於嵌入式基板之邊界掃描測試方法之流程圖。Figure 6 is a flow chart of a boundary scan test method for an embedded substrate in accordance with a preferred embodiment of the present invention.
參照第6圖，於依照本發明之較佳實施例用於嵌入式基板之邊界掃描測試方法中，首先藉由定位具有邊界掃描測試功能之測試晶片之上部和下部探測器於嵌入式基板之對應之接觸點以電性連接在嵌入式基板內之半導體晶片與測試晶片彼此，並且透過連接器等電性連接測試晶片與測試控制器彼此而建立測試環境(S100)。Referring to FIG. 6, in a boundary scan test method for an embedded substrate according to a preferred embodiment of the present invention, first, by mapping a top and bottom detector of a test wafer having a boundary scan test function to an embedded substrate The contact point is electrically connected to the semiconductor wafer and the test wafer in the embedded substrate, and the test environment is established by electrically connecting the test wafer and the test controller to each other through a connector or the like (S100).
此處，當設置複數個嵌入式基板時，複數個測試晶片彼此連接為鏈路由此令使其可於複數個嵌入式基板上執行邊界掃描測試。Here, when a plurality of embedded substrates are provided, a plurality of test wafers are connected to each other as a link, thereby making it possible to perform a boundary scan test on a plurality of embedded substrates.
當用於邊界掃描測試之測試時脈、測試模式選擇訊號、和測試資料於待測試之嵌入式基板、測試晶片、和測試控制器彼此連接狀態被輸入至測試晶片時，該測試晶片施用測試時脈、控制訊號、和測試資料至該嵌入式基板之半導體晶片，而令使執行基板連接狀態測試(S200)和功能測試(S300)。When the test clock for the boundary scan test, the test mode selection signal, and the test data are input to the test wafer when the embedded substrate, the test wafer, and the test controller to be tested are connected to each other, the test wafer is applied during the test. The pulse, the control signal, and the test data are sent to the semiconductor wafer of the embedded substrate, and the substrate connection state test (S200) and the functional test (S300) are performed.
更具體言之，對於基板連接狀態測試(S200)，測試控制器首先對測試晶片施用選擇邊界掃描測試模式之測試模式選擇訊號作為外部邊界掃描測試(ETEST)模式(S202)。More specifically, for the substrate connection state test (S200), the test controller first applies the test mode selection signal of the selected boundary scan test mode to the test wafer as the external boundary scan test (ETEST) mode (S202).
然後，測試晶片依照外部邊界掃描測試模式傳送控制訊號至嵌入式基板之半導體晶片，由此分離半導體晶片之輸入和輸出端子與半導體晶片之內部核心邏輯(S204)。於此狀態，測試控制器通過測試資料輸入端子輸入用於基板連接狀態測試之測試資料至測試晶片(S206)。Then, the test wafer transmits the control signal to the semiconductor wafer of the embedded substrate in accordance with the external boundary scan test mode, thereby separating the input and output terminals of the semiconductor wafer and the internal core logic of the semiconductor wafer (S204). In this state, the test controller inputs the test data for the substrate connection state test to the test wafer through the test data input terminal (S206).
因此，測試晶片通過半導體晶片之輸入端子輸入接收之測試資料至半導體晶片(S208)。當半導體晶片通過其輸入端子接收從測試晶片來之測試資料時，其通過與內部核心邏輯分離之訊號路由輸出反應訊號至其輸出端子。Therefore, the test wafer inputs the received test data to the semiconductor wafer through the input terminal of the semiconductor wafer (S208). When the semiconductor wafer receives test data from the test wafer through its input terminal, it outputs a reaction signal to its output terminal through a signal separated from the internal core logic.
此處，當複數個半導體晶片在嵌入式基板內彼此以鏈路形式連接時，重複上述過程，而令使於最末端之半導體晶片透過其輸出端子傳送反應訊號至該測試晶片。Here, when a plurality of semiconductor wafers are connected to each other in a link form in an embedded substrate, the above process is repeated, so that the semiconductor chip at the end is transmitted to the test wafer through its output terminal.
測試晶片接收來自半導體晶片之反應訊號至透過上述過程施用之測試資料，通過測試資料輸出端子傳送該反應訊號至測試控制器(S210)。The test wafer receives the reaction signal from the semiconductor wafer to the test data applied through the above process, and transmits the reaction signal to the test controller through the test data output terminal (S210).
然後，測試控制器比較輸入至該測試晶片之測試資料與透過測試資料輸出端子輸出自測試晶片之反應訊號彼此，由此確認安裝在嵌入式基板中複數個半導體晶片之間之連接狀態，也就是說，譬如在基板內引線之狀態、圖案之間斷接/短路之狀態、襲擊在0、襲擊在1故障、等等之基板連接狀態(S212)。Then, the test controller compares the test data input to the test chip with the reaction signals output from the test chip through the test data output terminal, thereby confirming the connection state between the plurality of semiconductor wafers mounted on the embedded substrate, that is, For example, the state of the leads in the substrate, the state of disconnection/short circuit between the patterns, the attack at 0, the attack at 1 failure, and the like, the substrate connection state (S212).
其次，對於功能測試(S300)，測試控制器對測試晶片施用測試模式選擇訊號選擇邊界掃描測試模式作為內部邊界掃描測試(INTEST)模式(S302)。Next, for the functional test (S300), the test controller applies a test mode selection signal selection boundary scan test mode to the test wafer as an internal boundary scan test (INTEST) mode (S302).
然後，測試晶片依照內部邊界掃描測試模式傳送控制訊號至嵌入式基板之半導體晶片，由此令使半導體晶片之內部核心邏輯被維持於其連接至半導體晶片之輸入和輸出端子之狀態。於此狀態，測試控制器輸入測試資料用於功能測試，也就是說，功能透過測試資料輸入端子執行用於預定功能測試之命令至測試晶片(S304)，並且該測試晶片令使該功能可以通過譬如GPIO、GPO、GPI、等等接腳執行待載入至半導體晶片之內部核心邏輯之命令(S306)。The test wafer then transmits control signals to the semiconductor wafer of the embedded substrate in accordance with the internal boundary scan test mode, thereby enabling the internal core logic of the semiconductor wafer to be maintained in its state of being connected to the input and output terminals of the semiconductor wafer. In this state, the test controller inputs the test data for the function test, that is, the function performs a command for the predetermined function test to the test chip through the test data input terminal (S304), and the test chip enables the function to pass. For example, GPIO, GPO, GPI, etc. pins execute commands to be loaded into the internal core logic of the semiconductor wafer (S306).
當測試功能執行命令如上述所示輸入至半導體晶片之內部核心邏輯時，對應半導體晶片之內部核心邏輯依照執行命令之輸入測試功能執行功能，並且通過輸出端子輸出執行之結果至外側(S308)。When the test function execution command is input to the internal core logic of the semiconductor wafer as described above, the internal core logic of the corresponding semiconductor wafer performs a function in accordance with the input test function of the execution command, and outputs the executed result to the outside through the output terminal (S308).
此處，當複數個於嵌入式基板中之半導體晶片彼此連接於鏈路形式並且其功能彼此機構地耦接時，則重複上述過程，而令使於最末端之半導體晶片通過其輸出端子傳送執行結果至測試晶片。Here, when a plurality of semiconductor wafers in an embedded substrate are connected to each other in a link form and their functions are mechanically coupled to each other, the above process is repeated, and the semiconductor chip at the end is transferred through its output terminal. The result is to the test wafer.
測試晶片接收來自半導體晶片之執行結果至透過上述過程施用之測試資料，通過測試資料輸出端子傳送該接收之執行結果至測試控制器(S310)。The test wafer receives the execution result from the semiconductor wafer to the test data applied through the above process, and transmits the received execution result to the test controller through the test data output terminal (S310).
然後，測試控制器比較輸入至該測試晶片之測試資料與透過測試資料輸出端子輸出自測試晶片之執行結果彼此，以決定安裝在嵌入式基板中之複數個半導體晶片之功能執行狀態，由此判定功能是否平穩地執行(S312)。Then, the test controller compares the test data input to the test chip with the execution result output from the test chip through the test data output terminal to determine the function execution state of the plurality of semiconductor wafers mounted in the embedded substrate, thereby determining Whether the function is performed smoothly (S312).
如上述提出之說明，依照本發明之較佳實施例，透過嵌入於該嵌入式基板中之該半導體晶片執行功能測試，藉此可改善對於半導體晶片之可靠性。As described above, in accordance with a preferred embodiment of the present invention, functional testing is performed through the semiconductor wafer embedded in the embedded substrate, whereby reliability for the semiconductor wafer can be improved.
此外，依照本發明之較佳實施例，於複數個嵌入式基板上之邊界掃描測試透過測試晶片之鏈路而執行，藉此可快速和有效地於複數個嵌入式基板上執行測試。Moreover, in accordance with a preferred embodiment of the present invention, boundary scan testing on a plurality of embedded substrates is performed through the links of the test wafers, whereby testing can be performed quickly and efficiently on a plurality of embedded substrates.
雖然為了說明之目的已揭示了本發明之較佳實施例，但是熟悉此項技術將了解到可以作各種修改、添加和替代而不偏離所附申請專利範圍中揭示之範圍和精神。因此應了解到此等修改、添加和替代亦落於本發明之申請專利範圍內。Although the preferred embodiment of the present invention has been disclosed for purposes of illustration, it will be understood that Therefore, it should be understood that such modifications, additions and substitutions are also within the scope of the invention as claimed.
1、30．．．嵌入式基板1, 30. . . Embedded substrate
2．．．測試晶片2. . . Test chip
2-1．．．上部探測器2-1. . . Upper detector
2-2．．．下部探測器2-2. . . Lower detector
3．．．控制器3. . . Controller
10．．．第一絕緣層10. . . First insulating layer
11a、11b．．．第一電路層11a, 11b. . . First circuit layer
12、18a、18b．．．通孔12, 18a, 18b. . . Through hole
13a、13b．．．第二絕緣層13a, 13b. . . Second insulating layer
14a、14b．．．第二電路層14a, 14b. . . Second circuit layer
16a、16b．．．第三絕緣層16a, 16b. . . Third insulating layer
17a、17b．．．第三電路層17a, 17b. . . Third circuit layer
20a至20c、32a、32b．．．半導體晶片20a to 20c, 32a, 32b. . . Semiconductor wafer
21．．．核心邏輯twenty one. . . Core logic
22．．．邊界掃描單元twenty two. . . Boundary scan unit
31．．．絕緣層31. . . Insulation
31a、31b．．．電路層31a, 31b. . . Circuit layer
S100、S200、S202、S204、…、S212、S300、S302、S100, S200, S202, S204, ..., S212, S300, S302,
S304、…、S312．．．步驟S304,...,S312. . . step
第1圖為依照本發明之較佳實施例用於嵌入式基板之邊界掃描測試裝置之組構圖；1 is a block diagram of a boundary scan test apparatus for an embedded substrate in accordance with a preferred embodiment of the present invention;
第2圖為顯示第1圖之嵌入式基板之圖式；Figure 2 is a diagram showing the embedded substrate of Figure 1;
第3圖為第1圖之測試晶片之內部方塊式；Figure 3 is an internal block diagram of the test wafer of Figure 1;
第4圖為顯示第1圖之嵌入式基板與測試晶片之間之耦接關係之圖式；以及4 is a view showing a coupling relationship between the embedded substrate and the test wafer of FIG. 1;
第5圖為顯示測試晶片嵌入於第1圖之嵌入式基板中狀態之圖式；Figure 5 is a diagram showing a state in which a test wafer is embedded in the embedded substrate of Figure 1;
第6圖為依照本發明之較佳實施例用於嵌入式基板之邊界掃描測試方法之流程圖。Figure 6 is a flow chart of a boundary scan test method for an embedded substrate in accordance with a preferred embodiment of the present invention.
1．．．嵌入式基板1. . . Embedded substrate
2．．．測試晶片2. . . Test chip
2-1．．．上部探測器2-1. . . Upper detector
2-2．．．下部探測器2-2. . . Lower detector
3．．．控制器3. . . Controller
Claims (12)
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| KR1020100093133A KR101222737B1 (en) | 2010-09-27 | 2010-09-27 | Boundary scan testing apparatus for embedded-type substrate and method thereof |
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| TWI443355B true TWI443355B (en) | 2014-07-01 |
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| DE (1) | DE102011113305A1 (en) |
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| TWI453442B (en) * | 2012-10-18 | 2014-09-21 | Inventec Corp | Detecting system for chip connection based on boundary scan and method thereof |
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| KR100213230B1 (en) * | 1997-01-29 | 1999-08-02 | 윤종용 | Test method for core and embedded memory circuit |
| US5793778A (en) * | 1997-04-11 | 1998-08-11 | National Semiconductor Corporation | Method and apparatus for testing analog and digital circuitry within a larger circuit |
| AU2001232778A1 (en) * | 2000-01-21 | 2001-07-31 | Sun Microsystems, Inc. | A printed circuit assembly with configurable boundary scan paths |
| JP2009169896A (en) | 2008-01-21 | 2009-07-30 | Sharp Corp | Server, system, and content display control method |
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2010
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| DE102011113305A1 (en) | 2012-03-29 |
| TW201224483A (en) | 2012-06-16 |
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