TWI405300B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI405300B
TWI405300B TW094136656A TW94136656A TWI405300B TW I405300 B TWI405300 B TW I405300B TW 094136656 A TW094136656 A TW 094136656A TW 94136656 A TW94136656 A TW 94136656A TW I405300 B TWI405300 B TW I405300B
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film
bonding pad
region
bonding
disposed
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TW200620547A (en
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Seiichi Suzuki
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Spansion Llc
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Description

半導體裝置及其製造方法
本發明係關於半導體裝置，更詳而言之，係關於用以避免半導體裝置之接合墊與互連線(interconnection line)間之電性短路的技術。
已知設置在半導體基材上的連接墊(接合墊(bonding pad，或稱為銲墊))及電極以互連線連接之半導體裝置。然而，因互連線與保護膜間之熱膨脹係數不同而可能造成熱應力(thermal stress)。此等應力可能造成互連線及保護膜產生裂縫。
日本專利申請案第2004－22653號遂揭露一種解決方法以解決上述問題。由此，在連接墊及突起電極周圍之重回路由圖案(rerouting pattern)設置狹縫。狹縫的作用在於分散及消除當突起電極壓力接觸該連接墊或該突起電極所產生之應力，以使短路及斷路故障的發生減至最低。
然而，現今半導體裝置因先進設計規範(advanced design rules)已使接合墊附近之佈局元件(layout element)小型化。舉例來說，必須使接合墊、接合墊與鈍化膜(passivation film)間重疊部份之寬度、鄰近金屬互連線間之間距縮小。而縮小尺寸則可能因為用於互連之材料之金屬原子(諸如金原子及鋁原子)之擴散而造成裂縫或短路。當應用習知設計規範不會造成此種裂縫。
更詳而言之，因金接合線之金原子擴散至鋁互連層導致鋁互連層熱膨脹而可能在鈍化層造成裂縫。這可能是起因於組裝過程中金屬化製程後的熱樹脂壓模(thermal resin molding)處理以及其他應用該半導體裝置時所產生之熱應力。也可能是因互連金屬之金屬原子進入裂縫而與鄰近互連層發生電性短路。
第1(a)圖至第1(c)圖說明解決上述問題之技術。更詳而言之，第1(a)圖係接合墊11與鄰近互連層12間之位置關係之平面圖，第1(b)圖及第1(c)圖分別顯示沿第1(a)圖所示之線C－C’所截之截面圖。第1(b)圖顯示接合線(bonding wire，或稱為銲線)16接合至接合墊11前之狀態，第1(c)圖顯示接合後之狀態。該裝置包含保護表面之鈍化膜13、形成在半導體基材15上之絕緣膜14、以及設置在接合墊11中之接合用開孔之窗口(opening window)18。元件符號17表示在鈍化膜13中所產生之裂縫。
利用標準的微影技術，在以化學氣相沉積法(CVD)依次成長於p型半導體基材15上之絕緣膜14上形成接合墊11及互連層12。接著，沉積鈍化膜13以覆蓋部分該接合墊11及該互連層12。可假定該接合墊11及該互連層12皆由鋁製成，而與接合墊11中之接合窗口18連接之接合線16為金。接合線16用以電性連接接合墊11至設置於晶片(圖中未顯示)外部之導線架(leadframe)。
在接合線16後，以壓模樹脂密封晶片。因為在密封過程中及應用半導體裝置時之環境溫度所施加之熱，而使在接合線16與接合墊11間之接合區(連接區)中，接合線16之金原子擴散和進入至鋁接合墊11。進入至鋁接合墊11之金原子很快地依其濃度而擴散其中而造成體積膨脹。
若該膨脹過程及接合墊11與互連層12間之厚度差超過一定之臨界值(threshold value)，則會在鈍化膜13中產生裂縫17，如第1(c)圖所示。造成體積膨脹之金及鋁原子從接合墊11進入至裂縫17。若這些原子延伸至互連層12，則接合墊11及互連層會發生電性短路。此外，四周空氣之濕氣經由裂縫17進入會造成互連層12之腐蝕。
進入裂縫之金屬原子程度(進入量和其長度)依所加溫度及時間而定而有所不同。為避免因金屬原子擴散造成之裝置故障，可以在接合線16至接合墊11之連接位置配置邊界區(margin)，以使連接位置與連接墊11之邊緣分隔(如顯示於第1(c)圖之L1至少為8微米)，或使接合墊11與互連層12間之空隙超過一定值(如L2至少為15微米)。然而，該種解決方式將增加晶片尺寸。
本發明提供一種適用於先進設計規範以及避免接合墊與互連層間短路之半導體裝置及其製造方法。
該半導體裝置包括：接合墊；以及接近該接合墊之互連線，其中該接合墊具有空隙區(gap region)，該空隙區設置於鄰近互連線的區域且順著與接合墊之面對該互連線的邊緣延伸之方向實質上相同方向延伸。
該半導體裝置可設成使該接合墊具有至少三個設置於鄰近互連線的區域及排列成向同方向延伸之空隙區。該半導體裝置復可包括覆蓋互連線及接合墊之一部份之單一保護膜(protection film)，其中位於接合墊之該一部份之空隙區由該保護膜之一部份所填充。此情況下，可能應用之結構為：該接合墊具有設置於其內部區域且用以接合接合線之窗口(window)；以及任一該至少三個空隙區設置於該窗口。
該保護膜可為具有比較軟之第一絕緣膜及比較硬之第二絕緣膜之多層膜，設置於該空隙區的該部分保護膜可包含有部份第一絕緣膜。第一絕緣膜可為SOG(旋塗玻璃，spin on glass)膜，第二絕緣膜可為氮化矽膜。該半導體裝置復可包含設置於空隙區周圍之接合墊側壁上之側壁。該側壁可由鈦或含鈦合金所製成。該半導體裝置復可包含覆蓋埋置互連圖案之氧化矽膜，其中該接合墊及該互連線設置於氧化矽膜上。
本發明包含一種半導體裝置之製造方法，包括：設置導電層於絕緣層上；將導電層圖案化成接合墊及接近該接合墊之互連線，以使該接合墊具有設置於鄰近互連線之區域且順著與接合墊之面對該互連線之邊緣延伸之方向實質上相同之方向延伸之空隙區。該方法復可包含形成設置於接合墊內部區域且用以接合接合線之窗口。
本發明包含一種半導體裝置之製造方法，包括：形成以絕緣膜覆蓋之埋置互連圖案；在絕緣層上設置導電層；以及將導電層圖案化成接合墊及接近接合墊之互連線，以使該接合墊具有設置於鄰近互連線之區域且順著與接合墊之面對該互連線之邊緣延伸之方向實質上相同之方向延伸之空隙區。
以下本發明之詳述僅作為具體範例而非用以限定本發明或本發明之應用及用途。再者，前述之先前技術及下述之本發明詳述並非用以限定本發明。
第2(a)圖至第2(c)圖顯示根據本發明第一實施例之半導體裝置之接合墊及鄰近接合墊之互連層之範例佈局(layout)。更詳而言之，第2(a)圖係顯示配置成相互鄰接之接合墊101及互連層102間之位置關係，第2(b)圖係沿第2(a)圖所示之線A－A’所截之截面圖。圖中顯示用以保護表面之鈍化膜103、形成於半導體基材105上之絕緣膜104、以及設置於接合墊101之接合用之開孔之窗口(opening window)108。接合線106連接至接合用之窗口108。
該半導體裝置具有用以定義窗口108之沿接合墊101各側設置之狹縫形之空隙區107a至107d。所述實施例假定互連層(圖中未顯示)設置於接合墊101之較上方、較下方及右側上。因此，沿接合墊101之四邊之每一邊設置空隙區107a至107d。然而，實際上，只沿實際配置有互連層於上面之接合墊之一側設置空隙區為足夠的。因此，若配置互連線102接近接合墊101，只需設置空隙區107a。
第2(b)圖係沿第2(a)圖之線A－A’所截之形成有空隙區107a之接合墊101之截面圖。如圖所示，接合墊101分為位於窗口108一側之區域101a及較靠近鄰接互連層102一側之區域101b，空隙區107a形成為區域101a及101b間之邊界。設置於接合線層102一側之區域101b以空隙區107a之寬度而與區域101a分隔。此外，空隙區107a以部份鈍化膜103所填充。因此，空隙區107a的作用在阻擋連接密封接合線106後之密封處理(sealing process)(如200℃，5小時)所加之熱以及接合線106之金屬分子由於該半導體裝置時之周圍溫度而擴散至區域101b。因此，幾乎不會發生擴散。因體積膨脹而造成之裂縫可能會發生在空隙區107a。然而，裂縫產生會降低體積膨脹以及避免在互連線102中產生之裂縫。
利用下述小型化處理可實現上述佈局。藉由在電阻率20 Ω．m之p型半導體基材105之主要表面上成長氮化矽膜(約800奈米(nm)厚)以形成絕緣膜104。之後利用標準的微影技術在絕緣膜104上形成接合墊101及互連層102。可利用PVD成長AlCu合金(Cu之重量百分比為0.5)至厚度約500奈米以及將AlCu合金膜圖案化成各別的形狀以形成接合墊101及互連層102。在圖案化處理中，在特定位置(如接合窗口108周圍之四邊)部分去除接合墊101之金屬以形成空隙區107a至107d。
接著，以CVD成長氮化矽膜至厚度約1000奈米，且在特定位置以鈍化膜103塗覆(coat)。然後，利用蝕刻之方式部份去除該膜以形成接合窗口108於接合墊101之內部。之後，將接合線106接合至經由窗口108而外露之接合墊101之內部區域。該接合線106可為直徑如30奈米之金線。
在如第2(a)至2(c)圖所示之具體結構中，窗口108各邊約為90微米厚。在接合墊101中窗口108一側之區域101a的寬度W1約為2微米，而空隙區107a的寬度W2約為1微米。在互連線102一側之區域101b的寬度W3約為2微米。
如第2(c)圖所示，可視所需將含有鈦或鈦合金之側壁109及110設置於接近用以接合接合墊101之窗口108之區域101a之側邊以及靠近互連層102之區域101b之側邊。對本發明佈局之半導體裝置進行加速試驗(acceleration test)(150℃，1000小時)，並比較其與習知佈局之半導體裝置的試驗結果，以檢驗本發明之半導體裝置之可靠度。
第3(a)圖及第3(b)圖係上述加速試驗後半導體裝置之截面圖(第3(a)圖顯示本發明佈局之半導體裝置，第3(b)圖顯示習知佈局之半導體裝置)。在習知半導體裝置中，加熱造成裂縫，而金屬從接合墊進入至鄰近互連層而造成短路。反之，參照第3(a)圖，空隙區107a至d吸收及分散應力，在接近互連層102之接合墊101之區域101b之不同金屬接合處抑制金屬移動。因此，接合處作用為作為金屬原子擴散之障壁，而沒有裂縫延伸至互連層102。可如第4圖所示設置空隙區於接合墊101中之窗口108內。空隙區107a至107d的寬度各約為1微米，長度約為20微米。
第5(a)圖及第5(b)圖為根據本發明第二實施例之具有接合墊及鄰近接合墊之互連層之佈局之俯視圖及截面圖。更詳而言之，第5(a)圖係顯示接合墊101及互連層102之空間關係之平面示意圖，第5(b)圖係沿第5(a)圖所示之線B－B’所截之截面圖。該裝置顯示有以熱氧化處理成長的氧化矽膜111，形成在以CVD成長之氧化矽膜104上的互連圖案112，及以CVD成長的氧化矽膜。用於敘述第一實施例之相似編號代表相似部份。
如第5(a)圖所示，彼此以已定距離分隔之複數對狹縫形空隙區(107a至107h)設置於接合墊101之一側以圍繞窗口108，而單狹縫形空隙區107i至107l設置於窗口108中，各個單狹縫形空隙區107i至107l相當於被空隙區107a至107h之相聯對(associated pair)所包夾在中間之一個居間區域(intermediate region)。即空隙區(107a至107h)及空隙區(107i至107l)交替排列成曲折結構(zigzag formation)。曲折排列(zigzag arrangment)作用為當接合金接合線至接合墊101而使金原子因此擴散時，增長接合線之金原子擴散之有效長度，以及相應狀況時，增長鋁分子擴散之有效長度。因此，曲折排列可縮短接合墊101與互連層102間之距離。而符合半導體裝置之接合墊及互連層間之小型化及短路之要求。
本發明佈局假定設置互連層(圖中未顯示)於接合墊101之較高、較低及右側，因此，設置幾對空隙區至接合墊101之四個外部邊緣。實際上，可在接合墊各側設有互連層處設置空隙區。若互連層102只配置緊鄰接合墊101，只需採用成對空隙區107a與107b以及只需在窗口108中設置與其相聯之空隙區107i。
利用下述小型化處理可實現上述佈局。在電阻率約20Ω‧m之p型半導體基材105之主要表面上成長氧化矽膜111(約300奈米厚)。接著，利用CVD在氧化矽膜111上成長氧化矽膜(厚度約為700奈米)之絕緣膜104。利用PVD成長AlCu合金(Cu之重量百分比為0.5)至厚度約500奈米及利用標準微影技術將其圖案化以形成互連圖案112。
利用CVD成長氧化矽膜113(厚度約為900奈米)以覆蓋互連圖案112，再次利用標準微影技術在氧化矽膜113上形成接合墊101及互連層102。可利用PVD成長AlCu合金(Cu之重量百分比為0.5)至厚度約500奈米及將AlCu合金膜圖案化成無關的形狀以形成接合墊101及互連層102。圖案化時，形成接合墊101之空隙區107a至1071。在第5(a)圖和第5(c)圖所示之實例中，各個空隙區寬約2微米而長約20微米。
接著，依序成長SOG膜(旋塗玻璃(Spin On Glass)：厚度約500奈米)及氮化矽膜(厚度約700奈米)以作為鈍化膜103。成長SOG時，上述空隙區以SOG填充。鈍化膜103具有雙層結構，以較軟的SOG填塞空隙區而有效吸收因後來處理中體積膨脹造成之應力，以防止裂縫產生。之後以蝕刻方式部份去除鈍化膜103，在接合墊101中形成窗口108。
當蝕刻窗口108時，在互連層102側之空隙區107a至107h覆蓋有鈍化膜103。空隙區107a至107h之SOG材料未被蝕刻而保留其中。反之，形成在窗口108中之接合墊101之空隙區107i至107l並無被鈍化膜108覆蓋。因此，在空隙區107i至107l之SOG材料藉由蝕刻而去除。最後，經由窗口108將接合線(圖中未顯示)接合至接合墊101。
空隙區107a至107l作用在於吸收和分散與接合線106連接後進行密封處理(sealing process)(如200℃，5小時)時所加之熱以及使用該半導體裝置時周圍之熱所造成之體積膨漲。尤其，因為該空隙區為“空的”(即無充滿SOG)及接近分子移動來源之接合線區，所以空隙區107i至107l吸收大部份體積膨脹。此外，可大幅抑制金屬原子從窗口108一側之區域擴散至互連層102一側之區域，以及大幅減少裂縫產生之頻率。因此可避免因應力而產生的裂縫，即使互連圖案112埋置於設有接合墊101及互連層102之平面下。
以上敘述為具有狹縫形形狀之空隙區。然而，該空隙區不限定為狹縫形形狀。該空隙區必須具有作為障壁(barrier)的作用，以鬆弛及分散因體積膨脹所造成之應力以及避免金屬原子從接合墊擴散至互連層。因此，明顯地，可視空隙區位置而修改空隙區之形狀、排列及數目。
如上所述，根據本發明，提供一種對裝置小型化及可避免在接合墊中短路之技術是可行的。
以上本發明之詳述已提出至少一個實施例，需明白仍有多種改變。需明白具體實施例只作為範例，而非用以限定本發明之範疇、應用或構造。此外，以上詳述將提供相關領域熟悉此技術者便利的準則以實行本發明之實施例，在實施例所述元件之作用及排列所作之各種改變，仍不脫離下述本發明申請專利範圍之範疇。
11．．．接合墊
12．．．互連層
13．．．鈍化膜
14．．．絕緣膜
15．．．半導體基材
16．．．接合線
17．．．裂縫
18．．．窗口
101．．．接合墊
101a至101b．．．區域
102．．．互連層
103．．．鈍化膜
104．．．絕緣膜
105．．．半導體基材
106．．．接合線
107a至1071．．．空隙區
108．．．窗口
109．．．側壁
110．．．側壁
111．．．氧化矽膜
112．．．互連圖案
113．．．氧化矽膜
以下將以所附圖式說明本發明，其中相似編號代表相似元件。
第1(a)、1(b)及1(c)圖說明先前技術之問題，其中第1(a)圖係接合墊與鄰近互連層間之位置關係之平面圖，第1(b)圖及第1(c)圖分別顯示沿第1(a)圖所示之線C－C’所截之截面圖。第1(b)圖顯示接合線接合至接合墊前之狀態，第1(c)圖顯示接合後之狀態；第2(a)、2(b)及2(c)圖說明根據本發明之具有接合墊及鄰近互連層之半導體裝置，其中第2(a)圖係相互鄰近之接合墊及互連層間位置關係之平面圖，第2(b)及2(c)圖分別為沿第2圖所示之線A－A’所截之截面圖；第3(a)圖及第3(b)圖係加速試驗後半導體裝置之截面圖，其中第3(a)圖顯示具有本發明佈局之半導體裝置，第3(b)圖顯示具有習知佈局之半導體裝置；第4圖係說明空隙區設置於接合窗口中之配置平面圖；以及第5(a)圖及第5(b)圖係說明根據本發明之另一半導體裝置之接合墊及鄰近互連層之佈局，其中第5(a)圖係相互鄰近之接合墊及互連層間位置關係之平面圖，第5(b)圖係沿第5(a)圖所示之線B－B’所截之截面圖。
101．．．接合墊
102．．．互連層
101a至101b．．．區域
103．．．鈍化膜
104．．．絕緣膜
105．．．半導體基材
106．．．接合線
107a至107d．．．空隙區
108．．．窗口
109．．．側壁
110．．．側壁

Claims (9)

  1. 一種半導體裝置，包括：接合墊；接近該接合墊之互連線；以及覆蓋該互連線及該接合墊之一部份之單一保護膜，其中，該接合墊具有空隙區，該空隙區設置於鄰近該互連線之區域且順著與該接合墊之面對該互連線的邊緣延伸之方向實質上相同方向延伸、位於該接合墊之該一部分之空隙區為該保護膜之一部份所填充、該保護膜係具有比較軟之第一絕緣膜及比較硬之第二絕緣膜之多層膜、設置於該空隙區之該保護膜之該一部份包括該第一絕緣膜之一部份、該第一絕緣膜係SOG膜、該第二絕緣膜係形成在該SOG膜上方的氮化矽膜、以及該空隙區為該SOG膜所填充。
  2. 如申請專利範圍第1項之半導體裝置，其中，該接合墊具有至少三個設置於鄰近該互連線且排列成向同方向延伸之空隙區。
  3. 如申請專利範圍第2項之半導體裝置，其中：該接合墊具有設置於其內部區域且用以接合接合線(wire)之窗口；以及任一該至少三個空隙區係設置於該窗口。
  4. 如申請專利範圍第1項之半導體裝置，復包括側壁，該側壁係設置於該空隙區周圍之該接合墊之側壁上。
  5. 如申請專利範圍第4項之半導體裝置，其中該側壁係以 鈦或含鈦合金所製成。
  6. 如申請專利範圍第1項之半導體裝置，復包括覆蓋埋置互連圖案之氧化矽膜，其中該接合墊及該互連線係設置於該氧化矽膜上。
  7. 一種製造半導體裝置之方法，包括下列步驟：在絕緣層上設置導電層；以及將該導電層圖案化為接合墊及接近該接合墊之互連線，以使該接合墊具有設置於鄰近該互連線之區域且順著與該接合墊之面對該互連線之邊緣延伸之方向實質上相同之方向延伸之空隙區，其中，該空隙區為該保護膜之一部份所填充、該保護膜係具有比較軟之第一絕緣膜及比較硬之第二絕緣膜之多層膜、設置於該空隙區之該保護膜之該一部份包括該第一絕緣膜之一部份、該第一絕緣膜係SOG膜、該第二絕緣膜係形成在該SOG膜上方的氮化矽膜、以及該空隙區為該SOG膜所填充。
  8. 如申請專利範圍第7之方法，復包括形成設置於該接合墊內部區域且用於接合接合線之窗口。
  9. 一種製造半導體裝置之方法，包括下列步驟：形成由絕緣層覆蓋之埋置互連圖案；在該絕緣層上設置導電層；以及將該導電層圖案化為接合墊及接近該接合墊之互連線，以使該接合墊具有設置於鄰近該互連線之區域且順著與該接合墊之面對該互連線之邊緣延伸之方向實 質上相同之方向延伸之空隙區，其中，該空隙區為該保護膜之一部份所填充、該保護膜係具有比較軟之第一絕緣膜及比較硬之第二絕緣膜之多層膜、設置於該空隙區之該保護膜之該一部份包括該第一絕緣膜之一部份、該第一絕緣膜係SOG膜、該第二絕緣膜係形成在該SOG膜上方的氮化矽膜、以及該空隙區為該SOG膜所填充。
TW094136656A 2004-10-29 2005-10-20 半導體裝置及其製造方法 TWI405300B (zh)

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JP5452064B2 (ja) * 2009-04-16 2014-03-26 ルネサスエレクトロニクス株式会社 半導体集積回路装置
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JP5926988B2 (ja) * 2012-03-08 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US9331019B2 (en) 2012-11-29 2016-05-03 Infineon Technologies Ag Device comprising a ductile layer and method of making the same
JP2016092061A (ja) * 2014-10-30 2016-05-23 株式会社東芝 半導体装置および固体撮像装置
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JP2020155659A (ja) * 2019-03-22 2020-09-24 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法
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