KR100419813B1 - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100419813B1 KR100419813B1 KR1020010062635A KR20010062635A KR100419813B1 KR 100419813 B1 KR100419813 B1 KR 100419813B1 KR 1020010062635 A KR1020010062635 A KR 1020010062635A KR 20010062635 A KR20010062635 A KR 20010062635A KR 100419813 B1 KR100419813 B1 KR 100419813B1
- Authority
- KR
- South Korea
- Prior art keywords
- wiring
- wiring layer
- film
- bonding pad
- insulating film
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 248
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 100
- 239000010931 gold Substances 0.000 claims description 100
- 229910052737 gold Inorganic materials 0.000 claims description 100
- 229910052751 metal Inorganic materials 0.000 claims description 84
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 44
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- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
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- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
Description
Claims (20)
- 반도체 소자가 형성된 영역인 활성 영역을 갖는 반도체 기판과,상기 반도체 기판 상에 형성되고, 상기 활성 영역과 전기적으로 접속된 제1 배선층과,상기 제1 배선층 상에 층간 절연막을 통해 형성된 제2 배선층과,적어도 일부가 상기 활성 영역과 중첩되도록 형성된, 외부와의 전기적 접속을 위한 본딩 패드를 구비하며,상기 제2 배선층은, 상기 본딩 패드와 중첩되는 영역 내에 복수의 배선을 갖고,상기 배선의 일부가 본딩 패드와 접합되어 있는 한편, 다른 배선과 본딩 패드 사이에 절연막이 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 절연막은, 본딩 패드측으로부터 제2 배선층에 가해지는 충격을 완화시키기 위한 유기 고분자막을 포함하는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 유기 고분자막이 폴리이미드막인 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 유기 고분자막의 두께가 2∼5㎛의 범위 내인 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 유기 고분자막의 빅커스 경도가 본딩 패드의 빅커스 경도(vickers hardness)의 2/3 이상인 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 유기 고분자막은, 상기 제2 배선층 배선의 일부와 상기 본딩 패드를 접합하기 위한 개구부를 갖고, 또한 상기 개구부를 둘러싼 내벽이, 상기 본딩 패드에 근접함에 따라 외측으로 넓어지는 방향으로 경사져 있는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 유기 고분자막은, 상기 제2 배선층의 배선의 일부와 상기 본딩 패드를 접합하기 위한 개구부를 갖고 있으며,상기 개구부의 개구 직경이 반도체 기판으로부터 멀어짐에 따라 넓어지는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 유기 고분자막은, 상기 제2 배선층의 배선의 일부와 상기 본딩 패드를 접합하기 위한 개구부를 갖고 있으며,상기 개구부 주위의 본딩 패드와 유기 고분자막과의 경계면은, 본딩 패드측으로 돌출하는 원호형상인 것을 특징으로 하는 반도체 장치.
- 제6항에 있어서,상기 유기 고분자막의 개구부 단면이 새의 부리 형상으로 되어 있는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 절연막은, 상기 유기 고분자막과 제2 배선층 사이에 협지된, 무기 절연 재료로 이루어지는 보호막을 더 포함하고,상기 제2 배선층 상의 보호막에 있어서의 유기 고분자막측의 표면에는, 상기 다른 배선에 대응한 볼록부가 형성되어 있는 것을 특징으로 하는 반도체 장치
- 제10항에 있어서,상기 볼록부는 오버행 형상인 것을 특징으로 하는 반도체 장치.
- 제11항에 있어서,기판면에 평행한 방향을 따라 있는 볼록부의 최대외형 치수를 X, 상기 방향을 따라 있는 볼록부의 최하부의 치수를 Y로 했을 때,상기한 치수 X 및 Y가,0.05㎛≤(X-Y)/2≤0.2㎛의 관계를 충족시키는 것을 특징으로 하는 반도체 장치.
- 제10항에 있어서,상기 다른 배선은, 본딩 패드와 중첩되는 영역 내에 있어서의 본딩 패드와 접합되어 있는 배선의 양측에, 각각 복수개 배치되어 있는 것을 특징으로 하는 반도체 장치.
- 제10항에 있어서,상기 제2 배선층에 있어서의 본딩 패드와 중첩되는 영역 내에 존재하는 배선간의 간격이 7㎛ 미만인 것을 특징으로 하는 반도체 장치.
- 제13항에 있어서,상기 다른 배선은, 반도체 장치 본체 또는 외부 장치의 동작에 관여하는 동작용 배선 외에, 반도체 장치 본체나 외부 장치의 동작에 관여하지 않은 더미 배선을 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 본딩 패드는,상기 배선과의 접합 부분에 형성된 고융점 금속층과,고융점 금속층 상에 형성되고, 표면에 노출된 금층을 포함하는 것을 특징으로 하는 반도체 장치.
- 반도체 기판 상에 반도체 소자를 형성하는 공정과,일부가 반도체 소자에 접합되도록 제1 배선층을 형성하는 공정과,상기 제1 배선층 상에, 비아홀을 갖는 층간 절연막을 형성하는 공정과,상기 층간 절연막 상 및 상기 비아홀 내에 제2 배선층을 형성하는 공정과,상기 제2 배선층 상에 절연막을 형성하는 공정과,상기 절연막에 개구부를 형성하는 공정과,상기 절연막 상과 상기 개구부내에 금속막을 형성함으로써, 외부와의 전기적 접속을 위한 본딩 패드를 형성하는 공정을 포함하고,제2 배선층을 형성하는 공정에서는 복수의 배선을 형성하고,절연막을 형성하는 공정에서는 복수의 배선을 피복하도록 절연막을 형성하며,개구부를 형성하는 공정에서는, 절연막으로 피복된 복수의 배선 중 일부의 배선만이 노출되도록 개구부를 형성하고,본딩 패드를 형성하는 공정에서는, 적어도 일부가 상기 반도체 소자와 중첩되고, 또한 절연막으로 피복된 배선 중 적어도 1개와 중첩되도록 본딩 패드를 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제17항에 있어서,제1 배선층을 형성하는 공정 전에, 상기 반도체 기판 상에 절연막을 형성하는 공정과,상기 절연막에 컨택트홀을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제17항에 있어서,절연막을 형성하는 공정이 보호막으로서의 무기 절연막을 형성하는 공정이고,개구부를 형성하는 공정이 무기 절연막에 제1 개구부를 형성하는 공정이며,상기 개구부를 형성하는 공정 후에, 본딩 시에 본딩 패드측으로부터 제2 배선층에 가해지는 충격을 완화시키기 위한 유기 고분자막을 상기 무기 절연막 상에 형성하는 공정과,상기 유기 고분자막에 대하여, 상기 무기 절연막의 제1 개구부를 포함하고, 또한, 그 개구부보다 넓은 제2 개구부를 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제19항에 있어서,본딩 패드를 형성하는 공정은, 상기 유기 고분자막 상, 무기 절연막의 제1 개구부 내, 및 유기 고분자막의 제2 개구부 내에 고융점 금속을 포함하는 금속막을 형성하는 공정과,상기 무기 절연막의 제1 개구부를 피복하고, 또한 제2 개구부보다 넓은 면적에 도금에 의해 금 범프를 형성하는 공정과,상기 금 범프를 마스크로 하여 불필요한 부분의 금속막을 제거하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
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Also Published As
Publication number | Publication date |
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US20020043723A1 (en) | 2002-04-18 |
TW511200B (en) | 2002-11-21 |
JP2002198374A (ja) | 2002-07-12 |
KR20020030258A (ko) | 2002-04-24 |
US6538326B2 (en) | 2003-03-25 |
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