TWI384590B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI384590B TWI384590B TW096147111A TW96147111A TWI384590B TW I384590 B TWI384590 B TW I384590B TW 096147111 A TW096147111 A TW 096147111A TW 96147111 A TW96147111 A TW 96147111A TW I384590 B TWI384590 B TW I384590B
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- 239000004065 semiconductor Substances 0.000 title claims description 72
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 229920005989 resin Polymers 0.000 claims description 165
- 239000011347 resin Substances 0.000 claims description 165
- 238000007789 sealing Methods 0.000 claims description 11
- 230000000717 retained effect Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 description 51
- 239000002184 metal Substances 0.000 description 16
- 238000009434 installation Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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Description
本發明係關於囊封於晶片大小的封裝中之半導體裝置及其製造方法。
本申請案要求日本專利申請案第2006-335688號之優先權,其內容以引用的方式併入本文中。
隨著電子裝置(例如可攜式終端機裝置)最近獲得改良而設計成實現多個功能及極複雜的功能,迫切需要半導體裝置不僅減小大小及尺度而且還能夠執行高速的處理。囊封於晶圓級晶片大小封裝(WL-CSP)中的半導體裝置近來已引起關注。在各囊封於WL-CSP中的半導體裝置之製造中,將再接導線及電極端子形成於晶圓級,而讓形成於一晶圓表面上之IC接受樹脂密封(或封裝)以便保護其在晶圓級不受熱、光及物理撞擊之影響;接著,在最終階段將該晶圓分成個別的片塊。因此,可以使得封裝後的半導體裝置大小實質上與IC晶片之大小匹配。此使得可以實現半導體裝置大小之一明顯縮小。
傳統上已知的各囊封於WL-CSP中之半導體裝置並非總係設計成使得藉由一樹脂密封僅一基板之表面(即,從一晶圓分割之一個別的片塊)。例如,日本未經審核專利申請公告案第2000-243729號教導其側區域同樣係藉由一樹脂密封之一半導體裝置;而日本未經審核專利申請公告案第2001-144121號教導其側區域與背面同樣係藉由一樹脂
密封之一半導體裝置。前述技術之每一技術係設計用於藉由樹脂密封在切割期間發生的缺陷(例如破碎)來保護一基板;因此,可以在該半導體裝置中減少缺陷或者減小缺陷大小。
但是,當在前述半導體裝置之角部發生一強烈撞擊時,塗布該基板之樹脂部分地破碎或部分地剝離,而該基板係部分地曝露於該表面。因此,需要在運輸期間或在安裝進電子裝置期間對其小心地加以處置。即,前述技術在高速運輸及高速安裝方面存在缺點。
本發明之一目的係提供一種在運輸及安裝期間可以容易地加以處置之半導體裝置,而且其中塗布該基板之樹脂幾乎不會破碎或剝離。
本發明之另一目的係提供一種半導體裝置之製造方法。
在本發明之一第一方面,具有一矩形外觀之一半導體裝置包括:一基板,其具有用以配置一積體電路之一表面;至少一再接導線,其係經由至少一焊墊電極電性連接至該積體電路;至少一電極端子,其係形成於該再接導線上;以及一樹脂層,其以一方式完全密封包括該再接導線之基板而使得該電極端子係曝露於該外部,其中該樹脂層具有在該樹脂層的背面與側面之間的角部形成之複數個傾斜面。可以另外在該樹脂層的表面與側面之間的樹脂層之角部形成其他傾斜面。
由於形成從該樹脂層之背面傾斜之傾斜面(或斜面),因
此可以可靠地防止密封該基板背面的樹脂層破碎或剝離而與在該半導體裝置中的樹脂層之角部發生之一撞擊無關。在藉由使用一筒夾承納及固持不形成該等電極端子的基板背面來進行該半導體裝置之運輸期間,甚至在該筒夾與該樹脂層之角部碰撞時亦可以可靠地防止該樹脂層破碎或剝離。由於形成從該樹脂層之表面傾斜之傾斜面(或斜面),因此可以可靠地防止密封該基板表面的樹脂層破碎或剝離;因此,可以可靠地防止該等再接導線及電極端子意外地曝露於該外部以及意外地受損。
此外,可以對應於該樹脂層之前述傾斜面而在該基板的背面與側面之間的角部形成傾斜面。還可以對應於該樹脂層之其他傾斜面而在該基板的表面與側面之間的角部形成其他傾斜面。由於形成該基板之傾斜面(及其他傾斜面),因此可以確保該樹脂層在其角部具有足夠的厚度;因此,可以藉由該樹脂層來可靠地保護該基板。
上文中,該樹脂層係由一用以密封該基板的背面之一第一樹脂層與用以密封該基板的表面及側面之一第二樹脂層組成,而其中該樹脂層之前述傾斜面係相對於該第一樹脂層與該第二樹脂層二者而形成。即,即使在該樹脂層的背面與側面之間的角部發生一撞擊,亦可以防止應力集中於該第一樹脂層與該第二樹脂層之間的邊界;因此,可以有效地防止該第一樹脂層從該第二樹脂層剝離。
在本發明之一第二方面,提供一種半導體裝置之製造方法,其中適用於提供具有一表面之一晶圓,複數個積體電
路係形成於該表面上形成而且係經由複數個焊墊電極電性連接至複數個再接導線,而且其中在該等再接導線上形成複數個電極端子,而接著將該晶圓分成複數個個別的片塊。在此,在形成該等再接導線及該等電極端子之前及之後,形成一第一樹脂層以密封該晶圓之背面;在形成該等再接導線及該等電極端子及該第一樹脂層後在該晶圓表面上朝該晶圓之背面執行第一次切割以使得部分地切除該第一樹脂層,從而形成分割該等積體電路之複數個切割通道;在形成該等切割通道後形成一第二樹脂層以密封該等切割通道及該晶圓之表面;在形成該等第一及第二樹脂層後讓該晶圓之背面接受切割以便以一方式在該第一樹脂層中形成複數個V形通道以使得該等V形通道與該等切割通道在該晶圓之厚度方向上重疊;接著;以一方式執行第二次切割以使得對因該第一次切割而接受分割的該晶圓之側面進行密封的該第二樹脂層仍然保留並以一方式使得該等V形通道部分地保留而形成複數個傾斜面,該等傾斜面係從密封該晶圓背面的第一樹脂層之背面傾斜,從而將該晶圓分成個別的片塊。
上文中,在形成該第二樹脂層後而在該第二次切割之前藉由在該晶圓表面上執行的切割而在該第二樹脂層中另外形成複數個V形通道以使得與該等切割通道重疊,其中形成於該第二樹脂層中的V形通道藉由該第二次切割而部分地保留,從而形成從密封該晶圓表面的第二樹脂層之表面傾斜的複數個傾斜面。
如上所述,該等傾斜面係形成於密封該基板背面的第一樹脂層之角部以及密封該基板表面的第二樹脂層之角部;因此,可以可靠地防止該樹脂層破碎或剝離而與在該第一及第二樹脂層之角部發生之一撞擊無關。
此外,可以在形成該第一樹脂層之前以一方式在該晶圓之背面中形成複數個V形通道以使得形成於該晶圓之背面中的V形通道與形成於該第一樹脂層中的V形通道在該晶圓之厚度方向上重疊,其中藉由該第一樹脂層將形成於該晶圓之背面中的V形通道與該晶圓之背面密封在一起。在此,形成於該晶圓之背面中的V形通道藉由該第二次切割而部分地保留,以使得形成在該晶圓之厚度方向上與該第一樹脂層的傾斜面重疊之傾斜面。此使得可以確保該樹脂層在形成該傾斜面的第一樹脂層之角部具有足夠的厚度;因此,可以藉由該樹脂層來可靠地保護該基板。
如上所述,由於在該樹脂層之角部形成該等傾斜面,因此可以可靠地防止該樹脂層破碎或剝離而與發生於該等角部之一撞擊無關。此使得容易在運輸期間及在安裝進一電子裝置期間處置該半導體裝置。因此,可以針對本發明之半導體裝置實現高速運輸及高速安裝。
將參考附圖,藉由範例來進一步詳細說明本發明。
依據本發明之一較佳具體實施例,將參考圖1至7來詳細說明一半導體裝置1及其一製造方法。該半導體裝置1係設計成使其可以安裝於一可攜式終端機裝置或另一電子裝置
中。特定言之,該半導體裝置1係囊封於WL-CSP中而在晶圓級接受再接線與樹脂密封。
如圖1所示,該半導體裝置1具有一矩形外觀,其中其包括:一薄矩形基板2(或來自一晶圓之一個別的片塊),其具有一表面2a以在該表面2a上配置一積體電路3;再接導線5,其係經由焊墊電極4電性連接至該積體電路3;柱狀電極端子(或金屬欄柱)6,其係形成於該等再接導線5上;以及一樹脂層7,其以一方式完全密封包括該等再接導線5之基板2而使得該等電極端子6之上面6a曝露於該外部。該半導體裝置1還包括突出電極(或凸塊)8,其從該等電極端子6的上面6a向上突出。
該基板2之側面2c(其係藉由第一次切割來定義)實質上係垂直於該表面2a及一背面2b(其係與該表面2a相對而定位)而置。從該基板2的背面2b向側面2c傾斜之傾斜面(或斜面)2d係形成於該基板2的背面2b與側面2c之間的角部。
該樹脂層7具有一表面7a、一背面7b及側面7c,該等面(側)係實質上與該基板2之表面2a、背面2b及側面2c平行而形成。密封該基板2的表面2a之樹脂層7之厚度係以一方式決定以使得該表面7a形成於實質上與該等金屬欄柱6的上面6a相同之平面上。此外,從該樹脂層7的背面7b向側面7c傾斜之傾斜面(或斜面)7d係形成於該樹脂層7的背面7b(密封該基板2的背面2b)與該樹脂層7的側面7c(密封該基板2的側面2c)之間。該樹脂層7之傾斜面7d係對應於該基板2之傾斜面2d而形成,其中較佳的係使該等傾斜面7d與
該等傾斜面2d形成為互相平行。
該樹脂層7係由密封該基板2的背面2b與傾斜面2d之一第一樹脂層9與密封該基板2的表面2a與側面2c之一第二樹脂層10構成。該第一樹脂層9與該第二樹脂層10係藉由一製造方法而彼此獨立地形成,下面將對此進行說明。例如,兩者皆係由一環氧樹脂組成。此項具體實施例係設計成使得僅在該第一樹脂層9中形成該等傾斜面7d,而該等傾斜面不會到達該第二樹脂層10。
接下來,將詳細說明具有前述組成之半導體裝置1之製造方法。
首先,提供具有一表面2a(對應於基板2之表面2a)之一碟片形狀的晶圓(對應於該基板2)(在其上面形成複數個積體電路3)與一背面2b(對應於該基板2之背面2b),如圖2所示。讓該晶圓2之背面2b沿劃線接受切割,以個別地定義該等積體電路3,從而形成V形通道11,每一V形通道皆具有一深度較小的V形區段。接下來,在該晶圓2的表面2a上形成連接至該等焊墊電極4之再接導線5,而接著在該等再接導線5上形成該等柱狀金屬欄柱6。該等再接導線5係藉由蝕刻形成。
接下來,如圖3所示,形成該第一樹脂層9以密封該晶圓2的背面2b與該等V形通道11。明確言之,該晶圓2係安裝於一形成該第一樹脂層9的樹脂薄片上而使其背面2b係與該樹脂薄片相對而定位;接著熔化該樹脂薄片並因此將其附著於該晶圓2之背面2b,其中藉由一熔化的樹脂來填充
該等V形通道11。此使得可以容易地將該第一樹脂層9之背面7b定位成實質上平行於該晶圓2之背面2b。
在形成該第一樹脂層9後,如圖4所示,在從該晶圓2的表面2a至背面2b之一方向上以一到達該第一樹脂層9的規定部分之深度來執行第一次切割,從而形成在該晶圓2的厚度方向上與該等V形通道11部分地重疊之切割通道12。由於該第一次切割,該晶圓2係沿該等切割通道12分成個別的片塊,每一片塊對應於該基板2,而藉由該第一樹脂層9將複數個基板2整合地固定在一起。
該切割通道12之寬度小於該V形通道11之寬度。在此,該切割通道12係形成用於在該V形通道11的寬度方向上僅切除其中心部分。該等V形通道11之其餘部分形成該基板2之傾斜面2d。
接下來,如圖5所示,該第二樹脂層10係形成用於同時密封該等切割通道12與該晶圓2之表面2a,以使得該樹脂層7之表面7a係與該晶圓2之表面2a平行而置。在此,藉由該第二樹脂層10來填充該等切割通道12,而藉由該第二樹脂層10來密封該晶圓2之表面2a、該等再接導線5及該等金屬欄柱6。明確言之,首先將該等金屬欄柱6完全嵌入該第二樹脂層10,而接著將該第二樹脂層10部分地拋光成將該等金屬欄柱6之上面6a曝露於該外部。
在該第二樹脂層10之形成完成後,如圖6所示,讓該晶圓2之一背面2b接受切割以在該第一樹脂層9之背面7b上形成V形通道13,每一V形通道具有一V形區段,其中該等V
形通道13係定位成令該等切割通道12與該等V形通道11的其餘部分在該晶圓2之厚度方向上重疊。
接下來,如圖7所示,該等凸塊8係附著到該等金屬欄柱6之上面6a(其係曝露於該第二樹脂層10之表面7a上)上。此外,將一切割帶15黏附於密封該晶圓2之背面2b的第一樹脂層9之背面7b上。然後,在該晶圓2之表面2a(對應於該第二樹脂層10之表面7a)上執行第二次切割,從而以一到達該切割帶15的規定部分之深度切除該等切割通道12。在此階段,將該晶圓2分成個別的片塊,每一片塊對應於該半導體裝置1。
由於該第二次切割而產生的切割寬度小於該切割通道12的寬度及該V形通道13的寬度,以使得該第二樹脂層10部分地保留於該切割通道12之內部壁上以便密封該基板2之側面2c。由於該第二次切割,僅切除該V形通道13在其寬度方向上的中心部分,以使得該V形通道13之其餘部分形成該樹脂層7之傾斜面7d。
最後,向外拖曳該切割帶15並因此使其拉伸,從而使得該"個別分割的"半導體裝置1係隔離而同時仍黏附於該切割帶15。因此,可以完成該半導體裝置1之製造。
依據該半導體裝置1及其製造方法,該等傾斜面7d係形成於在該樹脂層7的背面7b與側面7c之間的角部,從而可以可靠地防止該樹脂層7破碎或剝離而與向該等角部施加的撞擊無關。在運輸期間,使用一筒夾來承納與固持該半導體裝置1之背面7b(在其上面不形成任何金屬欄柱6及凸
塊8),其中即使在該樹脂層7的背面7b與側面7c之間的角部意外地與該筒夾碰撞時亦可以可靠地防止該樹脂層7在該等角部破碎或剝離。此使得容易在運輸期間及在安裝進一電子裝置及類似物期間處置該半導體裝置1。因此,可以針對本發明之半導體裝置1實現高速度運輸及高速度安裝。
此外,對應於該樹脂層7之背面7b之傾斜面7d而在該基板2之背面2b之角部上形成傾斜面2d。此確保該樹脂層7在該樹脂層7之背面7b之角部具有一足夠的厚度;因此,可以藉由該樹脂層7來可靠地保護該基板2。
在此項具體實施例中,在形成該等再接導線5及該等金屬欄柱6之後形成該第一樹脂層9;但此並非一限制。僅需要在形成該等V形通道11後形成該第一樹脂層9。換言之,可以在形成該等V形通道11之前形成該等再接導線5及該等金屬欄柱6。或者,其可以係在形成該第一樹脂層9之後形成。
此外,在該第一樹脂層9的背面7b上形成之V形通道13不一定係在形成該第二樹脂層10後形成。其僅需要在形成該第一樹脂層9後而在該第二次切割之前形成。
如上所述,可以一方式將該半導體裝置1之製造步驟改變成使得在該晶圓2之背面2b上形成該等V形通道11;在該第一樹脂層9中形成該等V形通道13;在該晶圓2之表面2a上形成該等再接導線5及該等金屬欄柱6;在從該晶圓2的表面2a至背面2b之一方向上形成該等切割通道12;在該晶
圓2之背面2b上形成該第二樹脂層10;而接著在從該晶圓2的表面2a至背面2b之一方向上執行該第二次切割。在此情況下,可以在讓該晶圓2之背面2b共同接受前述程序之後讓該晶圓2之表面2a接受處理;因此,可以針對該半導體裝置1而提高製造效率。
本發明不一定受限於上述半導體裝置1;因此,可以在隨附申請專利範圍所定義的本發明範疇內以各種方式對其進行修改。
此項具體實施例以一方式設計使得在該基板2的背面2b與側面2c之間的角部形成該等傾斜面2d。圖8顯示依據一第一變化方案之一半導體裝置21,其中該樹脂層7具有傾斜面7d,以替代該基板2具有傾斜面2d。該第一變化方案之半導體裝置21不需要在該製造期間於該半導體裝置1中形成該等V形通道11;因此,可以針對該半導體裝置21而提高製造效率。
此外,該半導體裝置21具有該第一樹脂層9,該第一樹脂層9係僅形成於該晶圓2之背面2b上。僅在類似於此項具體實施例之第一變化方案中,可以在該第一樹脂層9中形成該樹脂層7之傾斜面7d。但是,較佳的係在該第一樹脂層9與該第二樹脂層10二者中形成該等傾斜面7d。在該半導體裝置21之製造中,較佳的係將該等V形通道13形成為深達該第二樹脂層10。即,即使向該樹脂層7的背面7b與側面7c之間的角部施加一強烈撞擊,亦可以防止額外的應
力集中於該第一樹脂層9與該第二樹脂層10之間的邊界處;因此,可以有效地防止該第一樹脂層9意外地與該第二樹脂層10分離。
接下來,將參考圖9說明依據一第二變化方案之一半導體裝置31,其中與圖1所示半導體裝置1中所使用的該些零件類似之零件係指定為相同的參考數字;因此,將省略其相關說明。
該第二變化方案之半導體裝置31之特徵為,除在該第一樹脂層9的背面7b與側面7c之間的角部形成傾斜面7d外,還在該第二樹脂層10的表面7a與側面7c之間的角部形成傾斜面7e。
此外,除在該基板2的背面2b與側面2c之間的角部形成傾斜面2d外,還額外地在該基板2的表面2a與側面2c之間的角部形成傾斜面2e。對應於鄰近該第二樹脂層10的表面7a而定位之傾斜面7e,來形成鄰近該基板2的表面2a而定位之傾斜面2e,其中較佳的係該等傾斜面2e與7e係形成為互相平行。
可以藉由適用於該半導體裝置1的前述製造方法來形成該第二變化方案之半導體裝置31。明確言之,在形成該等再接導線5及金屬欄柱6之後並且在形成該等切割通道12之前,以一方式將鄰近該基板2的表面2a而定位之傾斜面2e形成為使得在該晶圓2的表面2a上形成V形通道32(類似於在該半導體裝置1的製造中使用的V形通道11),而接著藉
由該第一次切割的方式僅切除該等V形通道32之置於寬度方向上的中心部分。即,在該第一次切割後,該等V形通道32之其餘部分形成鄰近該基板2的表面2a而定位之傾斜面2e。
在形成該第二樹脂層10之後而在該第二次切割之前,以一方式將鄰近該第二樹脂層10的表面7a而定位之傾斜面7e形成為使得在該第二樹脂層10的表面7a上形成V形通道33(類似於在該半導體裝置1的製造中使用的V形通道13),而接著藉由該第二次切割的方式僅切除該等V形通道33之置於寬度方向上的中心部分。即,在該第二次切割後,該等V形通道33之其餘部分形成鄰近該第二樹脂層10的表面7a而定位之傾斜面7e。
該第二變化方案之半導體裝置31可以顯示與藉由該半導體裝置1實現的前述效果類似之效果。由於在該樹脂層7的表面7a與側面7c之間的角部形成該等傾斜面7e,因此可以可靠地防止密封該基板2的表面2a之第二樹脂層10意外地破碎或剝離;因此可以可靠地防止該等再接導線5及該等金屬欄柱6曝露於該外部及受損。此使得容易在運輸期間及在安裝進一電子裝置期間處置該半導體裝置31。因此,可以實現高速度運輸及高速度安裝。
該第二變化方案之半導體裝置31以一方式設計使得該等傾斜面2e係形成為鄰近該基板2的表面2a;但此並非一限制。即,僅該等傾斜面7e可以係形成為鄰近該第二樹脂層10之表面7a。
該第二變化方案之半導體裝置31之設計方式使得在該背面7b上形成該等傾斜面7d,而在該表面7a上形成該等傾斜面7e;但此亦非一限制。即,僅該等傾斜面7e可以係形成為鄰近該第二樹脂層10之表面7a。
最後,可以在隨附申請專利範圍所定義的本發明範疇內實現其他修改方案及其他變化方案。
1‧‧‧半導體裝置
2‧‧‧薄矩形基板
2a‧‧‧表面
2b‧‧‧背面
2c‧‧‧側面
2d‧‧‧傾斜面
2e‧‧‧傾斜面
3‧‧‧積體電路
4‧‧‧焊墊電極
5‧‧‧再接導線
6‧‧‧柱狀電極端子(或金屬欄柱)
6a‧‧‧上面
7‧‧‧樹脂層
7a‧‧‧表面
7b‧‧‧背面
7c‧‧‧側面
7d‧‧‧傾斜面
7e‧‧‧傾斜面
8‧‧‧突出電極(或凸塊)
9‧‧‧第一樹脂層
10‧‧‧第二樹脂層
11‧‧‧V形通道
12‧‧‧切割通道
13‧‧‧V形通道
15‧‧‧切割帶
21‧‧‧半導體裝置
31‧‧‧半導體裝置
32‧‧‧V形通道
33‧‧‧V形通道
已參考以下圖式詳細說明本發明之此等及其他目的、方面及具體實施例,圖式中:圖1係顯示依據本發明之一較佳具體實施例之一半導體裝置之組成的一斷面圖;圖2係用以說明該半導體裝置之一製造方法之一第一步驟的一縱向斷面圖,其中在一晶圓之表面上形成再接導線及金屬欄柱,而在該晶圓之背面上形成V形通道;圖3係用以說明該半導體裝置之製造方法之一第二步驟的一縱向斷面圖,其中在該晶圓之背面上形成一第一樹脂層;圖4係用以說明在該半導體裝置之製造方法之一第三步驟的一縱向斷面圖,其中藉由第一次切割在該晶圓中形成切割通道;圖5係用以說明該半導體裝置之製造方法之一第四步驟的一縱向斷面圖,其中在該晶圓之表面上形成一第二樹脂層;圖6係用以說明該半導體裝置之製造方法之一第五步驟
的一縱向斷面圖,其中在該第一樹脂層之背面上形成V形通道;圖7係用以說明該半導體裝置之製造方法之一第六步驟的一縱向斷面圖,其中執行第二次切割以便將該晶圓分成個別的片塊,每一片塊對應於該半導體裝置;圖8係顯示依據一第一變化方案之一半導體裝置之組成的一斷面圖;以及圖9係顯示依據一第二變化方案之一半導體裝置之組成的一斷面圖。
1‧‧‧半導體裝置
2‧‧‧薄矩形基板
2a‧‧‧表面
2b‧‧‧背面
2c‧‧‧側面
2d‧‧‧傾斜面
3‧‧‧積體電路
4‧‧‧焊墊電極
5‧‧‧再接導線
6‧‧‧柱狀電極端子(或金屬欄柱)
6a‧‧‧上面
7‧‧‧樹脂層
7a‧‧‧表面
7b‧‧‧背面
7c‧‧‧側面
7d‧‧‧傾斜面
8‧‧‧突出電極(或凸塊)
9‧‧‧第一樹脂層
10‧‧‧第二樹脂層
Claims (4)
- 一種半導體裝置之製造方法,其特徵在於:提供具有一表面之一晶圓,複數個積體電路係形成於該表面上且係經由複數個焊墊電極電性連接至複數個再接導線,而且其中在該複數個再接導線上形成複數個電極端子,而接著將該晶圓分成複數個個別的片塊,該製造方法包含以下步驟:在形成該等再接導線及該等電極端子之前或在形成該等再接導線及該等電極端子之後,形成一第一樹脂層以密封該晶圓之一背面;在形成該等再接導線及該等電極端子之後以及在形成該第一樹脂層之後,在該晶圓之該表面上朝該晶圓之該背面執行第一次切割,以使得部分地切除該第一樹脂層,從而形成分割該複數個積體電路之複數個切割通道;在形成該等切割通道之後,形成用以連續密封該複數個切割通道及該晶圓的該表面之一第二樹脂層;在形成該第一樹脂層之後以及在形成該第二樹脂層之後,將該晶圓之該背面切割成在該第一樹脂層中形成複數個V形通道而使得該複數個V形通道與該複數個切割通道在該晶圓之厚度方向上重疊;以及在該晶圓之該表面上執行第二次切割以使得對因該第一次切割而受到分割的該晶圓之側面進行密封之該第二樹脂層仍然留下且該複數個V形通道部份地留下,以便 形成複數個傾斜面,該等傾斜面係從密封該晶圓的該背面之該第一樹脂層之一背面傾斜,從而將該晶圓分割成該複數個個別的片塊。
- 如請求項1之半導體裝置之製造方法,其中在形成該第一樹脂層之前,另外在該晶圓之該背面中形成複數個V形通道以使得於該晶圓之厚度方向上與形成於該第一樹脂層中的該複數個V形通道重疊,而其中藉由該第一樹脂層將在該晶圓之該背面中形成的該複數個V形通道與該晶圓之該背面密封在一起。
- 如請求項1之半導體裝置之製造方法,其中在形成該第二樹脂層之後並且在該第二次切割之前,藉由在該晶圓之該表面上執行的切割而在該第二樹脂層中形成複數個V形通道以使得與該複數個切割通道重疊,並且其中形成於該第二樹脂層中的該複數個V形通道藉由該第二次切割而部分地保留,從而形成從密封該晶圓的該表面之該第二樹脂層之該表面傾斜的複數個傾斜面。
- 如請求項2之半導體裝置之製造方法,其中在形成該第二樹脂層之後並且在該第二次切割之前,藉由在該晶圓之該表面上執行的切割而在該第二樹脂層中形成複數個V形通道以使得與該複數個切割通道重疊,而其中形成於該第二樹脂層中的該複數個V形通道藉由該第二次切割而部分地保留,從而形成從密封該晶圓的該表面之第二樹脂層之該表面傾斜的複數個傾斜面。
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