JP5685012B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- JP5685012B2 JP5685012B2 JP2010147950A JP2010147950A JP5685012B2 JP 5685012 B2 JP5685012 B2 JP 5685012B2 JP 2010147950 A JP2010147950 A JP 2010147950A JP 2010147950 A JP2010147950 A JP 2010147950A JP 5685012 B2 JP5685012 B2 JP 5685012B2
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- 239000004065 semiconductor Substances 0.000 title claims description 119
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000011347 resin Substances 0.000 claims description 64
- 229920005989 resin Polymers 0.000 claims description 64
- 238000007789 sealing Methods 0.000 claims description 62
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 230000003014 reinforcing effect Effects 0.000 claims description 7
- 208000031872 Body Remains Diseases 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 26
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000011159 matrix material Substances 0.000 description 3
- 238000005422 blasting Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01005—Boron [B]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
1a 電極
2,30 封止樹脂部
3 再配線パターン
4 はんだバンプ
5 ソルダレジスト
10 シリコンウェハ
12 半導体チップ
12a 電極
14 メタルバンプ
16 ダイアタッチフィルム
20 ダミーウェハ
20a 凹部
22 マスク
24 支持体
30 封止樹脂部
32 再配線パターン
34 ソルダレジスト
36 はんだバンプ
40 半導体パッケージ
Claims (4)
- 複数の半導体チップを、互いに離間して整列した状態で、電極面を上にして支持体上の凹部に搭載し、
前記半導体チップを前記支持体上で絶縁樹脂により封止して封止樹脂部を形成し、
前記封止樹脂部の上面に再配線パターンを形成し、
前記再配線パターン上に外部接続端子を形成し、
前記支持体の補強部材を残して、前記支持体の前記凹部の底面を前記封止樹脂部からバックグラインドにより除去し、
前記半導体チップの背面が露出し、前記支持体の前記凹部の内側面を形成していた前記支持体の一部が前記半導体チップの周囲に枠状に残っている状態で前記バックグラインドを止め、
前記補強部材の外側に沿って前記封止樹脂部を切断し個片化する
ことを特徴とする半導体パッケージの製造方法。 - 請求項1記載の半導体パッケージの製造方法であって、
シリコンウェハの表面に、前記複数の半導体チップを個別に収容する前記凹部を形成することで前記支持体を形成することを特徴とする半導体パッケージの製造方法。 - 請求項2記載の半導体パッケージの製造方法であって、
前記シリコンウェハにマスクを施してからウェットブラスト処理することにより前記凹部を形成することを特徴とする半導体パッケージの製造方法。 - 請求項1乃至3のうちいずれか一項記載の半導体パッケージの製造方法であって、
前記複数の半導体チップを前記支持体の前記凹部に搭載してから、前記半導体チップの電極上にメタルバンプを形成することを特徴とする半導体パッケージの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010147950A JP5685012B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージの製造方法 |
US13/170,319 US8779573B2 (en) | 2010-06-29 | 2011-06-28 | Semiconductor package having a silicon reinforcing member embedded in resin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010147950A JP5685012B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージの製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012015191A JP2012015191A (ja) | 2012-01-19 |
JP2012015191A5 JP2012015191A5 (ja) | 2013-05-16 |
JP5685012B2 true JP5685012B2 (ja) | 2015-03-18 |
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JP2010147950A Active JP5685012B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージの製造方法 |
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US (1) | US8779573B2 (ja) |
JP (1) | JP5685012B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI476841B (zh) * | 2012-03-03 | 2015-03-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9768038B2 (en) * | 2013-12-23 | 2017-09-19 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of making embedded wafer level chip scale packages |
JP6495692B2 (ja) * | 2015-03-11 | 2019-04-03 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
US9899285B2 (en) * | 2015-07-30 | 2018-02-20 | Semtech Corporation | Semiconductor device and method of forming small Z semiconductor package |
WO2018003565A1 (ja) | 2016-06-28 | 2018-01-04 | 日本ゼオン株式会社 | 半導体パッケージ製造用支持体、半導体パッケージ製造用支持体の使用、及び半導体パッケージの製造方法 |
US10811298B2 (en) * | 2018-12-31 | 2020-10-20 | Micron Technology, Inc. | Patterned carrier wafers and methods of making and using the same |
WO2022210598A1 (ja) | 2021-03-29 | 2022-10-06 | 味の素株式会社 | 回路基板の製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4013452B2 (ja) * | 2000-05-24 | 2007-11-28 | 松下電器産業株式会社 | 樹脂封止型半導体装置の製造方法 |
JP2001345411A (ja) * | 2000-05-31 | 2001-12-14 | Matsushita Electric Ind Co Ltd | リードフレームとそれを用いた半導体装置及びその生産方法 |
JP4934900B2 (ja) | 2000-12-15 | 2012-05-23 | イビデン株式会社 | 多層プリント配線板の製造方法 |
JP3609737B2 (ja) * | 2001-03-22 | 2005-01-12 | 三洋電機株式会社 | 回路装置の製造方法 |
JP2003347741A (ja) * | 2002-05-30 | 2003-12-05 | Taiyo Yuden Co Ltd | 複合多層基板およびそれを用いたモジュール |
JP3888267B2 (ja) | 2002-08-30 | 2007-02-28 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP3951854B2 (ja) | 2002-08-09 | 2007-08-01 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP4199588B2 (ja) * | 2003-04-25 | 2008-12-17 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法 |
JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP4592413B2 (ja) * | 2004-12-27 | 2010-12-01 | 三洋電機株式会社 | 回路装置 |
JP5117692B2 (ja) * | 2006-07-14 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20080142946A1 (en) * | 2006-12-13 | 2008-06-19 | Advanced Chip Engineering Technology Inc. | Wafer level package with good cte performance |
CN102106198B (zh) * | 2008-07-23 | 2013-05-01 | 日本电气株式会社 | 半导体装置及其制造方法 |
JP4420965B1 (ja) | 2008-10-30 | 2010-02-24 | 新光電気工業株式会社 | 半導体装置内蔵基板の製造方法 |
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2010
- 2010-06-29 JP JP2010147950A patent/JP5685012B2/ja active Active
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2011
- 2011-06-28 US US13/170,319 patent/US8779573B2/en active Active
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Publication number | Publication date |
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US8779573B2 (en) | 2014-07-15 |
JP2012015191A (ja) | 2012-01-19 |
US20110316152A1 (en) | 2011-12-29 |
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