TWI382499B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI382499B
TWI382499B TW095112023A TW95112023A TWI382499B TW I382499 B TWI382499 B TW I382499B TW 095112023 A TW095112023 A TW 095112023A TW 95112023 A TW95112023 A TW 95112023A TW I382499 B TWI382499 B TW I382499B
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lead
sealing resin
groove
semiconductor device
semiconductor wafer
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TW200644191A (en
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Tsunemori Yamaguchi
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Rohm Co Ltd
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H—ELECTRICITY
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
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    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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Description

半導體裝置
本發明係關於一種樹脂密封半導體晶片而製造的半導體裝置，特別係關於表面實裝型的半導體裝置。
近年來，為了在布線基板上高密度實裝半導體裝置，故大多使用可在布線基板上表面實裝之表面實裝型封裝。此表面實裝型封裝係例如眾所皆知的QFN(Quad Flat Non-leaded Package)(無引線四方扁平封裝)或SON(Small Outlined Non-leaded Package)(小外型無引線封裝)等，除去從樹脂封裝延伸出之引線，在樹脂封裝下表面露出引線(外引線)，即所謂的無引線封裝。
如此封裝係藉由在引線框架上樹脂密封半導體晶片等後，從引線框架之框部切除而形成。
具體說明，引線框架係對帶狀的銅板實施精密壓板加工後，對其表面實施焊錫鍍敷而製造，並且具有將對應複數個半導體裝置之各單位部分相連設置於銅板之長度方向之構造。對應1個半導體裝置之單位部分係例如圖6所示，包含有支持半導體晶片之矩形狀晶片墊101、包圍此晶片墊101之框部102、及對應晶片墊101於銅板長度方向之兩側，與其長度方向正交之方向且按大致相等間隔配設複數條引線103於與其長度方向正交之方向間隔幾乎相等間距配置之複數條引線103。晶片墊101係經由未圖示之連結部接合於框部102。並且，各引線103的基端部乃接合於框部102， 形成朝向晶片墊101延伸之長尺形狀。然後，將半導體晶片晶粒結著於晶片墊101上，並以接合線105(參照圖7)連接此半導體晶片之端子與引線103上面後，藉由密封樹脂106(參照圖7)密封由二點虛線所示之密封區域104內。其後，藉由沿著虛線所示之切斷線107切斷引線103，並且從框部102切離晶片墊101及各引線103，即可獲得無引線型之封裝(SON)。
引線103之密封於密封樹脂106內之部分，係藉由接合線105，做為與半導體晶片電性連接之內引線之功能。另外，引線103之下表面(連接接合線105之面與相反側之面)108係如圖7所示，從密封樹脂106之下表面露出，做為焊接於布線基板109上之接島(布線圖案)110之外引線而功能。於接島110上塗有膏狀焊錫111，藉由膏狀焊錫111將引線103下表面108接合於接島110，即可達成對半導體裝置之布線基板109之表面實裝。
[專利文獻1]
日本特開2001-156233號公報
但是，接島110上之膏狀焊錫111係僅密著於引線103表面之已焊錫鍍敷之部分。亦即，引線框架之狀態，雖然已對引線103之整體表面實施焊錫鍍敷，但因沿著切斷線107切斷引線103，故引線103之端面(沿著切斷線107之切斷面)，構成引線框架基體之銅板將會露出。因此，接島110上之膏狀焊錫111係不會密著於引線103之端面。
引線103與接島110接合(焊接)狀態之外觀檢查(良否判定)，係以引線103之端面側是否有形成膏狀焊錫111之突起，即是否有形成所謂的焊點為基準。因此，膏狀焊錫111不會密著於引線103端面，故若於引線103之端面側未形成焊點，則難以外觀檢查引線103與接島110之接合狀態。
因此，本發明之目的係在於提供一種可易於外觀檢查引線與布線基板接島之接合狀態之半導體裝置。
此發明一形態之半導體裝置係包含半導體晶片、密封此半導體晶片之密封樹脂，與以於前述密封樹脂內與前述半導體晶片電性連接，且其下表面至少一部分從前述密封樹脂之下表面露出，其端面從前述密封樹脂之側面露出之方式，與前述半導體晶片同時密封於前述密封樹脂之引線。然後，於前述引線下表面從前述密封樹脂露出之部分，形成到達前述引線外端面之凹溝。
藉由此構造，在引線從密封樹脂露出之部分形成到達引線外端面之凹溝。因此，於布線基板表面實裝半導體裝置時，引線從密封樹脂露出之下表面係與於布線基板接島上塗上膏狀焊錫接合時，其膏狀焊錫係鉗入至形成在引線下表面之凹溝內。藉由此，膏狀焊錫係成為於引線外端面側突起之狀態，亦即於引線外端面側形成焊點。因此，可易於外觀檢查引線與布線基板之接島之接合(焊接)狀態。
前述凹溝之內面係最好有實施焊錫鍍敷。
藉由此構造，因於凹溝內面實施焊錫鍍敷，故鉗入至凹 溝內之膏狀焊錫係可對凹溝內面發揮良好之密著性。因此，也可增加引線對接島之接合強度。此外，也可確實達成引線與接島之電性連接。
前述引線係最好形成於前述凹溝之前述端面側以外之周圍，且含有防止前述密封樹脂進入前述凹溝之堰堤部。
藉由此構造，因於凹溝周圍形成堰堤部，故於組裝半導體裝置時，可防止密封樹脂進入凹溝，且可防止凹溝受到密封樹脂填埋。因此，實裝半導體裝置時，可確實將接島上之膏狀焊錫混入凹溝內，故可確實形成焊點。
本發明中之上述或其他目的、特徵及效果，係可參照添附圖面且經由下述之實施形態之說明而了解。
以下，參照添附圖面詳細說明此發明之實施形態。
圖1為例示此發明實施形態之半導體裝置構造之圖解剖面圖。此外，圖2為圖1所示之半導體裝置之底面圖(例示對布線基板之接合面之圖)；圖3為例示其半導體裝置一角之立體圖。
此半導體裝置為適用於無引線型SON(Small Outlined Non-leaded Package)(小外型無引線封裝)之半導體裝置；且包含半導體晶片1、支持此半導體晶片1之晶片墊2、與半導體晶片1電性連接之複數引線3與密封此等之大致四角錐台形狀之密封樹脂4。
半導體晶片1係在形成其功能元件側之表面(裝置形成面)朝向上方之狀態，晶粒結著於晶片墊2。並且，藉由從 將布線層之一部分形成於最表面之表面保護膜露出，於半導體晶片1之表面形成複數個墊(未圖示)。各墊係藉由接合線5連接於引線3。
晶片墊2係形成平面視矩形狀。晶片墊2之下表面係從密封樹脂4之下表面4a露出。
於晶片墊2之一方端緣側與其相反側之另一端緣側各設有相同數量之(於此實施形態中為各8個)引線3；於各側，於沿著各方端緣及下方端緣之方向按特定間隔而排列著。
各引線3係於與引線3之排列方向正交之方向(與晶片墊2相反方向)形成長尺之平面視長方形狀。另外，各引線3係具備一體形成的本體部6，與於晶片墊2側端部，從下表面側實施軌碎加工而形成之防止脫落部7。
本體部6之下表面6a係從密封樹脂4之下表面4a露出，外端面6b係從密封樹脂4之側面露出。從密封樹脂4下表面4a露出之本體部6下表面6a，係功能做為焊接於後述布線基板10上之接島(布線圖案)11之外引線。於本體部6之下表面6a，形成到達本體部6外端面6b之凹溝8。另外，本體部6所密封於密封樹脂4內之部分係功能做為內引線，且將接合線5連接於其上面。
防止脫落部7係比本體部6較薄形成，於本體部6上面附近，與晶片墊2側及引線3之長度方向正交之兩側突出。與半導體晶片1相同地樹脂密封引線3之狀態，由於密封樹脂4將回繞至防止脫落部7的下方，故可達成防止引線3從密封樹脂4脫落。
組裝此半導體裝置時，晶片墊2與引線3乃與共通框部(未圖示)結合之引線框架狀態，於晶片墊2上晶片接著半導體晶片1，以接合線5連接半導體晶片1之墊與引線3之上面後，5/11藉由密封樹脂4密封此等半導體晶片1、晶片墊2、引線3及接合線5。此時，形成在各引線3之凹溝8周圍底面視略為U字狀之部分9，係功能做為防止密封樹脂4進入凹溝8之堰堤部。其後，沿著密封樹脂4(封裝)之側面切斷各引線3，使晶片墊2及各引線3從引線框架之框部切離開。如此，即可獲得無引線型之SON半導體裝置。
引線框架係例如對板厚0.2 mm之銅板進行精密壓板加工而形成晶片墊2、引線3及框部後，對各引線3之下表面，藉由進行軋碎加工形成防止脫落部7，尚且藉由進行蝕刻加工形成凹溝8，更進一步對其整體表面進行焊錫鍍敷而製成。因此，在引線框架之狀態，於各引線3之表面全面形成焊錫鍍敷層。但是，從引線框架之框部切離晶片墊2及各引線3後(切出半導體裝置之單體後)，藉由切斷各引線3，構成引線框架之基體之銅板乃露出於各引線3之本體部6之外端面6b(各引線3之切斷面)。
圖4為例示此半導體裝置之實裝狀態之圖解剖面圖。此半導體裝置係對布線基板10之表面，亦即對形成接島(布線圖案)11之面，朝向著引線3所露出之面來表面實裝。
接島11上塗有膏狀焊錫12。將此半導體裝置表面實裝於布線基板10時，藉由膏狀焊錫12可使引線3之本體部6之下表面6a接合對應於接島11。
因在引線3之本體部6側面形成焊錫鍍敷層，故一旦本體部6之下表面6a接合於接島11上之膏狀焊錫12，膏狀焊錫12即以延伸至本體部6之側面之方式密著。此外，由於在引線3之本體部6下表面6a形成凹溝8，故一旦本體部6下表面6a乃接合於接島11上之膏狀焊錫12時，膏狀焊錫12乃鉗入其凹溝8內。藉由此，膏狀焊錫12係呈現在引線3之本體部6外端面6b側突起之狀態，即於引線3之本體部6外端面6b側形成所謂的焊點。因此，可易於外觀檢查引線3與接島11之接合(焊接)狀態。
此外，由於在凹溝8之內面也形成焊錫鍍敷層，故鉗入凹溝8內之膏狀焊錫12係可對凹溝8之內面發揮良好之密著性。因此，可增加對接島11之引線3之接合強度。並且，也可確實達成引線3與接島11之電性連接。
再者，由於在凹溝8周圍形成從底面視略為U字狀之堰堤部9，故組裝半導體裝置時，可防止密封樹脂4進入凹溝8且也可防止凹溝8被密封樹脂4填埋。因此，實裝半導體裝置時，可確實使接島11之膏狀焊錫12鉗入凹溝8內，且也可確實形成焊點。
以上，說明本發明之一實施形態，本發明係也可以其他形態實施。例如，上述之實施形態中，舉例出含有無引線型SON之半導體裝置，但本發明係如圖5所示，也可適用於含有將引線3之本體部6之外端面6b與密封樹脂4之側面形成同一面，即所謂去框類型SON之半導體裝置。此外，並不限定於SON，例如也可適用於含有QFN(Quad Flat Non-leaded Package)之半導體裝置。
另外，上述之實施形態中，藉由蝕刻加工，於引線3之本體部6下表面6b形成凹溝8，但亦可利用蝕刻加工以外之方法，例如藉由雷射加工形成凹溝8。
其他，於記載於專利申請事項範圍內可實施各種變更設計。
1‧‧‧半導體晶片
2‧‧‧晶片墊
3‧‧‧引線
4‧‧‧密封樹脂
4a‧‧‧密封樹脂之下表面
5‧‧‧接合線
6‧‧‧本體部
6a‧‧‧本體部之下表面
6b‧‧‧本體部之外端面
7‧‧‧脫落部
8‧‧‧凹溝
9‧‧‧堰堤部
10‧‧‧布線基板
11‧‧‧接島
12‧‧‧膏狀焊錫
101‧‧‧晶片墊
102‧‧‧框部
103‧‧‧引線
104‧‧‧密封區域
105‧‧‧接合線
106‧‧‧密封樹脂
107‧‧‧切斷線
108‧‧‧下表面
109‧‧‧布線基板
110‧‧‧接島
111‧‧‧膏狀焊錫
圖1係表示此發明一實施形態之半導體裝置(引線切斷類型)構造之圖解剖面圖。
圖2係表示圖1所示之半導體裝置之底面圖。
圖3係表示圖1所示之半導體裝置一角之立體圖。
圖4係表示圖1所示之半導體裝置實裝狀態之圖解剖面圖。
圖5係表示此發明其他實施形態之半導體裝置(去框類型)構造之圖解剖面圖。
圖6係表示以往引線框架構造之平面圖。
圖7係使用圖6所示之引線框架之半導體裝置實裝狀態之圖解剖面圖。
3‧‧‧引線
4‧‧‧密封樹脂
4a‧‧‧密封樹脂之下表面
6‧‧‧本體部
6a‧‧‧本體部之下表面
6b‧‧‧本體部之外端面
7‧‧‧防止脫落部
8‧‧‧凹溝
9‧‧‧堰堤部
10‧‧‧布線基板
11‧‧‧接島
12‧‧‧膏狀焊錫

Claims (2)

  1. 一種半導體裝置，其特徵在於包含：半導體晶片；密封樹脂，其係密封此半導體晶片；及引線，其係於前述密封樹脂內與前述半導體晶片電性連接，以其下表面至少一部分從前述密封樹脂之下表面露出且端面從前述密封樹脂之側面露出之方式，與前述半導體晶片一同由前述密封樹脂所密封；於前述引線之下表面之從前述密封樹脂露出之部分，形成有到達前述引線之外端面之凹溝；前述引線係包含：本體部，其係形成有前述凹溝；及防止脫落部，其相對於前述本體部，在前述半導體晶片側及與前述引線之長度方向正交之兩側突出，而比前述本體部薄，且被前述密封樹脂覆蓋；且前述引線包括：堰堤部，其形成於前述凹溝之前述端面側除外之周圍，用以防止前述密封樹脂進入前述凹溝，且其仰視為大致U字狀。
  2. 如請求項1之半導體裝置，其中於前述凹溝之內面施以焊料鍍敷。
TW095112023A 2005-04-08 2006-04-04 半導體裝置 TWI382499B (zh)

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JP6238121B2 (ja) * 2013-10-01 2017-11-29 ローム株式会社 半導体装置
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