1380360 九、發明說明 【發明所屬之技術領域】 本發明係關於基板處理裝置用元件及其製造方法，特 別係關於被使用於消耗環境下之基板處理裝置用元件及其 製造方法。 【先前技術】 通常，對作爲基板之半導體晶圓（以下稱爲「晶圓」 )施行蝕刻處理之基板處理裝置，配備收容晶圓之收容室 (以下稱爲「處理室」）。此基板處理裝置’在處理室內 施加高頻電力，而由CF4系氣體等的處理氣體，生成電漿 ，再藉由該被生成的電漿，對晶圓的表面施行蝕刻處理。 在處理室內，配置爲了將電漿的狀態維持在所希望的 狀態之各種元件，作爲如此的元件之其中一種，已知有聚 磁環。聚磁環係圓環狀的元件，被配置在處理室內，使得 可以包圍晶圓的周邊。聚磁環，爲了將處理室內的電漿有 效率地導引至晶圓，需要具有與晶圓相同的電特性，例如 導電性。因此，習知的聚磁環，係藉由矽（Si)而被形成 〇 可是，由於矽會被電漿侵蝕，所以在處理室內，聚磁 環會在短時間內消耗而變形。若聚磁環變形，由於晶圓上 的電漿的狀態會變化，所以在使用由矽所構成的聚磁環的 情況，每隔一段短的時間，便需要交換聚磁環。 因此，近年來，開始使用藉由以作爲難以被電漿侵蝕 138〇36〇 的材料著稱的碳化矽（sic)而被形成 ’具有大約與晶圓相同的導電性，在電 會發生金屬污染，所以作爲處理室內元 作爲碳化矽，已知有藉由燒結法而 矽、及藉由CVD法而被形成的CVD碳 電漿所造成的消耗量，相對於矽之由於 量，前者大約減少1 5 °/〇，後者大約減少 但是，燒結碳化矽，由於已知容易 提出一種藉由難以發生微粒的CVD碳 )藉由燒結碳化矽而被形成的聚磁環的 參照專利文獻1 )。藉此，能夠抑制從I [專利文獻1]日本特開平1 0- 1 3 5093 【發明內容】 (發明所欲解決之課題） 然而，CVD碳化矽，係先將材料氣 在高溫氣氛中的石墨基材的周圍，而在 上，形成碳化矽的厚膜，再藉由切出該 被得到。又，由於被切出來的CVD碳 將提升外觀及藉由表面圓滑化來防止微 目的，而對聚磁環施行硏磨加工。因此 磁環，會有製造困難這樣的問題。 又，CVD碳化矽，雖然難以發生微 生一些微粒，特別是在聚磁環交換後的 之聚磁環。碳化矽 漿氣氛中，由於不 件是適合的。 被形成的燒結碳化 化矽。各自的由於 電漿所造成的消耗 5 0%。 發生微粒，所以被 化矽來保護（被膜 表面之技術（例如 δ磁環發生微粒。 號公報 體導入已經被配置 該石墨基材的表面 已經形成的厚膜而 化矽的表面粗糙， 粒飛散一事，作爲 ，CVD碳化矽的聚 粒，但是依然會發 初期的蝕刻處理， -6- 1380360 具體而言，在高頻電力的施加時間達到120小時爲止的期 間，會發生許多微粒。因此’使用CVD碳化矽的聚磁環 的情況，在聚磁環交換後’需要長時間實行爲了使處理室 內的氣氛安定之陳化（seasoning)處理，因而也會有基板 處理裝置的運轉率低下這樣的問題。 本發明的目的在於提供一種基板處理裝置用元件及其 製造方法，能夠抑制微粒的發生，並防止基板處理裝置的 運轉率的低下，而且能夠容易地製造。 (解決課題所用的手段） 爲了達成前述目的，申請專利範圍第1項所記載之基 板處理裝置用元件的製造方法，係被配置在用來收容基板 之基板處理裝置的收容室內之基板處理裝置用元件的製造 方法，其特徵爲： 具有使存在於前述基板處理裝置用元件的表面附近之 空孔狀缺陷的存在比率降低之缺陷存在比率降低步驟。 申請專利範圍第2項所記載之基板處理裝置用元件的 製造方法’係針對申請專利範圍第1項所記載之基板處理 裝置用元件的製造方法，其中前述缺陷存在比率降低步驟 ’係將不純物導入前述缺陷中。 申請專利範圍第3項所記載之基板處理裝置用元件的 製造方法，係針對申請專利範圍第2項所記載之基板處理 裝置用元件的製造方法，其中前述不純物，係由含氟氣體 、含碳氣體、及含氧氣體之中的至少一種的氣體所生成的 1380360 . 電漿’而被生成。 申請專利範圍第4項所記 製造方法’係針對申請專利範 裝置用元件的製造方法，其中 ♦ ，係將前述基板處理裝置用元 • 申請專利範圍第5項所記 製造方法’係針對申請專利範 •裝置用元件的製造方法，其中 ’係在非活性氣體的氣氛中， 的溫度，設成1200°C〜16〇〇。0 • 申請專利範圍第6項所記 製造方法’係針對申請專利範 所記載之基板處理裝置用元件 正電子消滅法’來檢查前述基 近之檢查步驟。 爲了達成目I』述目的，申請 板處理裝置用元件，係被配置 * 裝置的收容室內之基板處理裝 . 存在於表面附近之空孔狀 於藉由CVD法而被形成的碳 缺陷的存在比率低。 【實施方式】 (實施發明的最佳形態） 載之基板處理裝置用元件的 圍第1項所記載之基板處理 前述缺陷存在比率降低步驟 件，作熱處理。 載之基板處理裝置用元件的 圍第4項所記載之基板處理 前述缺陷存在比率降低步驟 將前述基板處理裝置用元件 〇 載之基板處理裝置用元件的 圍第1項至第5項之任一項 的製造方法，其中具有藉由 板處理裝置用元件的表面附 專利範圍第7項所記載之基 在用來收容基板之基板處理 置用元件，其特徵爲： 缺陷的存在比率，係比存在 化矽體的表面附近之空孔狀 -8- 1380360 以下’一邊參照圖面一邊說明有關本發明的實施形態 〇 首先’說明關於本發明的第1實施形態的基板處理裝 置用元件及其製造方法。 第1圖係表示使用了作爲有關本發明的第1實施形態 的基板處理裝置用元件的聚磁環之基板處理裝置的槪略構 成的剖面圖。 在第1圖中’作爲基板處理裝置而被構成之蝕刻處理 裝置1’配備：例如鋁製的圓筒型處理室2;被配設在該 處理室2內’經由絕緣材4來支持例如用來載置200mm 的半導體晶圓W之下部電極3，而可以升降自如的支持體 5;和面對下部電極3’作爲被配置在處理室2的上方之上 部電極之噴頭6。 處理室2，其上部係被形成作爲小直徑的上室7，其 下部係被形成作爲大直徑的下室8。偶極環磁石9被配置 在上室7的周圍’該偶極環磁石9，在上室7內，形成指 向一方向的同樣的水平磁場。在下室8的側面上部，安裝 使半導體晶圓W的搬出入口開閉之閘閥丨〇 ;蝕刻處理裝 置1，經由閘閥1 0，與相鄰的加載互鎖真空室（未圖示） 等接續。 高頻電源11’經由匹配器12，被接續至下部電極3; 高頻電源11 ’對下部電極3施加規定的高頻電力。藉此， 下部電極3，發揮作爲下部電極的機能。 爲了以靜電吸著力來吸住半導體晶圓W之靜電夾盤 -9 - 1380360 (ESC) 13,被配置在下部電極3的頂面。由導電膜所構 成的圓板狀電極板14，被配置在該靜電夾盤13的內部， 直流電源15則導電地被接續至該電極板14。半導體晶圓 W，藉由從直流電源15被施加在電極板14上的直流電壓 所產生的庫倫力等，被吸住保持在靜電夾盤13的頂面上 〇 圓環狀的聚磁環16，被配置在靜電夾盤13的周圍。 因此，聚磁環16，包圍被靜電夾盤13吸住之半導體晶圓 W的周圍。又，聚磁環16，由於是由碳化矽所構成，故 具有大約與半導體晶圓W相同的導電性。藉此，聚磁環 16，能夠將在處理室2內所產生的電漿，有效率地導引至 半導體晶圓W。此處，聚磁環16，係藉由後述有關本實 施形態的基板處理裝置用元件之製造方法而被製造出來， 其存在於表面附近的空孔狀缺陷的存在比率（以下稱爲「 缺陷存在比」），係被設成比存在於藉由CVD法而被形 成的碳化矽體的表面附近之缺陷存在比率低。 將下部電極3上方的氣體，往處理室2的外面排出之 排出路徑，被形成在上室7的側壁和下部電極3之間；環 狀的擋板1 7，則被配置在該排氣路徑的途中。從排氣路徑 的擋板17往下游的空間（下室8的內部空間），連通至 不僅進行處理室2內的壓力控制，且將處理室2內減壓至 真空狀態爲止之排氣系統1 8。 由從該支持體5的下部朝向下方延伸設置的螺栓19 所構成的下部電極升降機構，被配置在下部電極3的下部 -10- 1380360 。該下部電極升降機構，經由支持體5，支持下部電極3 ，並藉由利用未圖示的馬達等，使螺栓19旋轉，而使作 爲GAP之下部電極3升降。此下部電極升降機構，係藉 由被配置在其周圍之伸縮囊20、及被配置在該伸縮囊20 的周圍之伸縮囊蓋21，來遮斷處理室2內的氣氛。 又，從該靜電夾盤13的頂面突出自如的複數個推進 銷22，被配置在下部電極3。這些推進銷22係在圖中的 上下方向作移動。 此蝕刻處理裝置1，在半導體晶圓W的搬出入之際， 其下部電極3’係下降至半導體晶圓w的搬出入位置爲止 ，同時推進銷22從靜電夾盤13的頂面突出，使半導體晶 圓W從下部電極3離開，而往上方抬起。又，在半導體 晶圓W的蝕刻處理之際，下部電極3上升至半導體晶圓 W的處理位置爲止，同時推進銷22被收納在下部電極3 內，靜電夾盤1 3則吸住保持半導體晶圓w。 又，例如往圓周方向延伸之環狀的冷媒室23，被設在 下部電極3的內部。經由配管24從冷卻單元（未圖示） 來的規定溫度的冷媒’例如冷卻水，被循環供給至此冷媒 室23內’藉由該冷媒的溫度，被載置在下部電極3上之 半導體晶圓W的處理溫度會被控制。 複數的傳熱氣體供給孔與傳熱氣體供給溝（未圖示） ’被配設在靜電夾盤13的頂面。這些傳熱氣體供給孔等 ’係經由被配置在下部電極3的內部之傳熱氣體供給管線 25’而被接續至傳熱氣體供給部26;該傳熱氣體供給部 -11- 1380360 26，將傳熱氣體例如He氣體，供給至靜電夾盤13和半導 體晶圓W之間的間隙中。此傳熱氣體供給部26，也被構 成可以將靜電夾盤1 3和半導體晶圓W之間的間隙抽真空 〇 被配置在處理室2的天花板部之噴頭6，被接地（通 地），噴頭6發揮作爲接地電極的機能。又，緩衝室27 被設在噴頭6的頂面，此緩衝室27，接續從處理氣體供給 部（未圖示）來的處理氣體導入管28。MFC(Mass Flow Controller ’質量流量控制器）29被配置在此處理氣體導 入管28的途中。此MFC29，經由緩衝室27與噴頭6,將 規定的氣體例如處理氣體、N2氣體等，供給至處理室2內 ，並控制該氣體的流量，與前述排氣系統18共同作用， 將處理室2的壓力控制成所希望的値。 在此蝕刻處理裝置1的處理室2內，如前述般，高頻 電力被施加在下部電極3上，藉由該被施加的高頻電力， 在下部電極3與噴頭6之間，由處理氣體發生高密度的電 漿，而生成離子等。 蝕刻處理裝置1，在蝕刻處理之際，首先使閘閥10成 爲開狀態，將加工對象之半導體晶圓w搬入處理室2內 。然後，先藉由噴頭6，將處理氣體（例如規定流量比率 的四氟化碳（CF4 )氣體與氧氣（02 )之至少一種所組成 的混合氣體），以規定的流量與流量比，導入處理室2內 ，再藉由排氣系統18等，將處理室2內的壓力作成規定 値。進而，藉由高頻電源11對下部電極3施加高頻電力 -12- 1380360 ，並藉由直流電源15對電極板14施加直流電壓，而將半 導體晶圓W吸在下部電極3上。而且，使由噴頭6吐出 的處理氣體，如上述般地電漿化。此電漿，藉由聚磁環16 ，被收束在半導體晶圓W的表面上，而藉由此電漿所生 成的離子，‘例如氟離子、氧離子等，將半導體晶圓W的 表面，作物理蝕刻。 如前述般，在藉由碳化矽來形成聚磁環16的情況， 作爲碳化矽，有採用藉由燒結法而被形成的碳化矽（以下 稱爲「燒結碳化矽」）與藉由CVD法而被形成的碳化矽 (以下稱爲「CVD碳化矽」）之任一種，但是不論是採用 燒結碳化矽的情況、及採用CVD碳化矽的情況之任一種 ，已知在初期的蝕刻處理中，聚磁環16會發生微粒。 關於在初期的蝕刻處理中會發生微粒之機構，由於明 瞭地說明有所困難，故本發明的發明人，類推該機構的假 設，先製作出由碳化矽所構成的聚磁環，再將該聚磁環配 置在蝕刻處理裝置的處理室內，觀察相對於蝕刻處理時間 之從聚磁環來的微粒（碳化矽微粒）的發生數量、以及相 對於蝕刻處理時間之聚磁環的消耗量。 其結果，本發明的發明人，確認了：在高頻電力的施 加時間爲15分鐘的時點，在處理室2內發生許多的微粒 、微粒之中的大約1/3是由聚磁環來的微粒、以及聚磁環 的消耗幾乎沒有進行。又，本發明的發明人，確認了：在 高頻電力的施加時間爲80小時的時點，在處理室內的微 粒持續減少 '微粒之中的大約1/10是由聚磁環來的微粒 -13- 1380360 、以及聚磁環的消耗持續進行。 亦即，本發明的發明人，確認了 ：伴隨著聚磁環的消 耗，從聚磁環來的微粒的發生量持續減少。藉此，本發明 的發明人，在初期的蝕刻處理中，關於發生微粒之機構， 類推出第2圖所示之以下的假設。 在由碳化矽所構成的聚磁環的表面附近，存在多數個 缺少碳 '矽等所形成之空孔狀.的缺陷（在圖中以“〇”來 表示），該缺陷的存在比率，越靠近表面越高。因此，聚 磁環，被認爲在其表面形成了脆性層（第2圖（A))。 在初期的蝕刻處理中，如圖中的箭頭所示，若離子等 的物質衝撞此脆性層，則離子的動能會傳遞至此脆性層， 於是脆性層中的碳化矽分子飛散，該飛散的碳化矽分子， 成爲微粒（第2圖（B))。 若對半導體晶圓W連續長時間地施行蝕刻處理，則 以可以包圍該半導體晶圓W的周圍之方式而被配置之聚 磁環’由於長時間暴露於電漿中，而消耗其脆性層，於是 < 脆性層下方的比較緻密的層（以下稱爲「緻密層」）露出 。如圖中的箭頭所示，即使離子等的物質衝撞此緻密層， 由於緻密層中的碳化矽的分子間力大，所以緻密層中的碳 化矽分子不會飛散，其結果，幾乎不會發生微粒（第2圖 (C))。 亦即，缺陷存在比率和微粒的發生量，有密切的關係 :缺陷存在比率低的時候，微粒的發生量變少。 對應此假設，有關本發明的第1實施形態之基板處理 -14- 1380360 裝置用元件的製造方法，係使存在於由碳化矽所構成之作 爲基板處理裝置用元件的聚磁環的表面附近之缺陷存在比 率降低。 第3圖係作爲有關本發明的第丨實施形態之基板處理 裝置用元件的製造方法之零件製造處理的流程圖。 在第3圖中，首先，藉由燒結法或CVD法，形成所 希望的尺寸的碳化矽體，再藉由切削加工，將該被形成的 碳化矽體成形爲聚磁環（步驟S31)。 接著，將被成形後的聚磁環，暴露於會生成不純物之 由四氟化碳氣體與氧氣之中的至少一種的氣體所生成的電 漿中，將由電漿來的不純物例如氟離子、氧離子等，導入 存在於聚磁環的表面附近之空孔狀的缺陷中（缺陷存在比 率降低步驟）（步驟S32)。 在步驟S32中，首先，如圖中之繪有陰影線的箭頭所 示，朝向被成形後的聚磁環的表面，照射電漿，將電漿中 的氟離子、氧離子等作爲不純物，藉由摻雜或離子植入， 導入缺陷中（第4圖（A))。被導入該缺陷中的氟離子 、氧離子等，提高面向缺陷之碳化矽彼此之間的電的結合 力（分子間力）。又，藉由被導入缺陷中的氟離子、氧離 子等，留在缺陷中（在圖中，以繪有陰影線的圓來表示） ，結果存在於聚磁環的表面附近之缺陷存在比率降低，於 是聚磁環的表層成爲比較緻密的層（以下稱爲「不純物導 入層」）（第4圖（B))。 此時，氟離子、氧離子等，由於僅被導入聚磁環的表 -15-[Technical Field] The present invention relates to an element for a substrate processing apparatus and a method of manufacturing the same, and more particularly to an element for a substrate processing apparatus used in a consumption environment and a method of manufacturing the same. [Prior Art] Generally, a substrate processing apparatus that etches a semiconductor wafer (hereinafter referred to as a "wafer") as a substrate is provided with a storage chamber (hereinafter referred to as a "processing chamber") for accommodating the wafer. The substrate processing apparatus ' applies high-frequency electric power to the processing chamber, generates a plasma from a processing gas such as CF4 gas, and etches the surface of the wafer by the generated plasma. As the various elements for maintaining the state of the plasma in a desired state in the processing chamber, a magnetic ring is known as one of such elements. The magneto-ring ring-shaped element is disposed in the processing chamber so as to surround the periphery of the wafer. The collecting ring needs to have the same electrical characteristics as the wafer, such as electrical conductivity, in order to efficiently direct the plasma in the processing chamber to the wafer. Therefore, the conventional collecting magnetic ring is formed by yttrium (Si). However, since the yttrium is eroded by the plasma, the collecting magnetic ring is consumed and deformed in a short time in the processing chamber. If the magnetic ring is deformed, the state of the plasma on the wafer changes. Therefore, in the case of using a collecting ring made of tantalum, it is necessary to exchange the collecting ring every short period of time. Therefore, in recent years, the use of sic is known to be sic which is known as a material which is difficult to be etched by plasma, and has the same conductivity as the wafer, and metal contamination occurs in electricity. Therefore, as the processing chamber element, as the niobium carbide, the amount of consumption by the sintering method and the CVD carbon plasma formed by the CVD method is known, and the former is reduced by about 15 as compared with the amount of niobium. In the latter case, the latter is reduced. However, it is known that it is easy to propose a polymagnetic ring formed by sintering lanthanum carbide by CVD carbon which is hard to generate fine particles. In this way, it is possible to suppress the problem from the I [Patent Document 1] Japanese Patent Application Laid-Open No. Hei 10- 1 3 5093 [Explanation of the Invention] However, the CVD niobium carbide is a graphite in which a material gas is first used in a high-temperature atmosphere. A thick film of tantalum carbide is formed around the substrate and on top, and is obtained by cutting out the film. Further, since the cut CVD carbon will enhance the appearance and prevent the micro purpose by rounding the surface, the concentrating ring is honed. Therefore, the magnetic ring has such a problem that manufacturing is difficult. Further, CVD carbonized ruthenium, although it is difficult to generate some fine particles, in particular, the magnetic collecting ring after the exchange of the magnetic magnetic ring. In a carbonized mash atmosphere, it is not suitable. The sintered carbonized niobium is formed. The respective consumption due to the plasma is 50%. When particles are generated, they are protected by pupation (the technique of the surface of the film (for example, the δ magnetic ring generates particles.) The surface of the graphite substrate has been deposited with a thick film that has been formed on the surface of the graphite substrate, and the surface of the surface is rough, and the particles are scattered. As a granule of CVD tantalum carbide, it is still an initial etching treatment. -6- 1380360 Specifically, many particles are generated during the period when the application time of high-frequency power reaches 120 hours. In the case of the magnetization ring of the tantalum carbide, it is necessary to carry out the seasoning treatment for the atmosphere in the processing chamber after the exchange of the magnetism ring, and thus the operation rate of the substrate processing apparatus may be lowered. An object of the present invention is to provide an element for a substrate processing apparatus and a method of manufacturing the same, which can suppress the occurrence of fine particles and prevent the operation rate of the substrate processing apparatus from being lowered, and can be easily manufactured. (Means for Solving the Problem) The method for manufacturing a component for a substrate processing apparatus according to the first aspect of the invention is A method of manufacturing a substrate processing device element in a housing chamber of a substrate processing apparatus for accommodating a substrate, comprising: reducing a ratio of existence of a void-like defect existing in a vicinity of a surface of the substrate processing device element In the method of manufacturing a substrate processing device according to the first aspect of the invention, the method of manufacturing the substrate processing device according to the first aspect of the invention, wherein the defect presence ratio In the method of manufacturing a substrate processing device according to the second aspect of the invention, the method of manufacturing the substrate processing device according to the second aspect of the invention, wherein the method of manufacturing the substrate processing device according to claim 2, wherein The impurity is produced by 1380360. Plasma generated by a gas containing at least one of a fluorine-containing gas, a carbon-containing gas, and an oxygen-containing gas. The manufacturing method of the fourth application of the patent application is directed to the application. a manufacturing method of a component for a patent device, wherein ♦ The processing method of the processing device is as follows: The manufacturing method described in the fifth paragraph of the patent application is a method for manufacturing a component for a patent application device, wherein the temperature in the atmosphere of the inert gas is set to 1200 ° C to 16 〇〇 0 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造The component for the board processing apparatus is disposed in the substrate processing apparatus in the storage chamber of the apparatus. The existence ratio of the carbon defects formed by the CVD method in the vicinity of the surface is low. [Embodiment] BEST MODE FOR CARRYING OUT THE INVENTION The substrate according to the first item of the substrate processing apparatus is processed to treat the defect-reducing ratio lowering step and heat-treated. Substrate processing of the substrate processing apparatus according to the fourth aspect of the present invention, the defect processing ratio lowering step, any one of the first to fifth items of the substrate processing apparatus component carried by the substrate processing apparatus component The manufacturing method of the item, wherein the surface of the component for the board processing apparatus is attached to the substrate according to the seventh aspect of the patent scope, and the substrate processing component for accommodating the substrate is characterized in that: the existence ratio of the defect is present The embodiment of the present invention will be described with reference to the drawings. First, the substrate processing device element according to the first embodiment of the present invention and a method for manufacturing the same will be described. . Fig. 1 is a schematic cross-sectional view showing a schematic configuration of a substrate processing apparatus using a magnetism collecting ring as an element for a substrate processing apparatus according to a first embodiment of the present invention. In the first embodiment, 'the etching processing apparatus 1' configured as a substrate processing apparatus is equipped with, for example, a cylindrical processing chamber 2 made of aluminum; and disposed in the processing chamber 2, 'supported by the insulating material 4, for example. The lower electrode 3 of the semiconductor wafer W of 200 mm is placed, and the support 5 can be lifted and lowered, and the lower electrode 3' is placed as the head 6 disposed above the upper electrode of the processing chamber 2. The processing chamber 2 has an upper portion formed as a small-diameter upper chamber 7, and a lower portion formed as a large-diameter lower chamber 8. The dipole ring magnet 9 is disposed around the upper chamber 7. The dipole ring magnet 9 forms the same horizontal magnetic field in one direction in the upper chamber 7. A gate valve 开 for opening and closing the loading/unloading port of the semiconductor wafer W is attached to the upper portion of the side surface of the lower chamber 8. The etching processing device 1 is connected to an adjacent load-locking vacuum chamber (not shown) via the gate valve 10, and the like. The high-frequency power source 11' is connected to the lower electrode 3 via the matching unit 12, and the high-frequency power source 11' applies predetermined high-frequency power to the lower electrode 3. Thereby, the lower electrode 3 functions as a lower electrode. An electrostatic chuck -9 - 1380360 (ESC) 13 for holding the semiconductor wafer W by electrostatic attraction is disposed on the top surface of the lower electrode 3. The disk-shaped electrode plate 14 composed of a conductive film is disposed inside the electrostatic chuck 13, and the DC power source 15 is electrically connected to the electrode plate 14. The semiconductor wafer W is attracted to a ring-shaped magnetism collecting ring 16 held on the top surface of the electrostatic chuck 13 by a Coulomb force or the like generated by a DC voltage applied from the DC power source 15 to the electrode plate 14. It is disposed around the electrostatic chuck 13. Therefore, the collecting magnetic ring 16 surrounds the periphery of the semiconductor wafer W sucked by the electrostatic chuck 13. Further, since the collecting ring 16 is made of tantalum carbide, it has approximately the same conductivity as the semiconductor wafer W. Thereby, the magnetism collecting ring 16 can efficiently guide the plasma generated in the processing chamber 2 to the semiconductor wafer W. Here, the magnetic flux ring 16 is manufactured by the method for manufacturing a substrate processing apparatus according to the present embodiment, and the existence ratio of the void-like defects existing in the vicinity of the surface (hereinafter referred to as "defective existence" The ratio is set to be lower than the ratio of defects existing in the vicinity of the surface of the carbonized carbide body formed by the CVD method. A discharge path for discharging the gas above the lower electrode 3 to the outside of the processing chamber 2 is formed between the side wall of the upper chamber 7 and the lower electrode 3; and an annular baffle plate 7 is disposed in the exhaust path. On the way. The space downstream of the baffle 17 of the exhaust path (the internal space of the lower chamber 8) is connected to the exhaust system 1 that not only performs pressure control in the processing chamber 2 but also decompresses the inside of the processing chamber 2 to a vacuum state. 8. A lower electrode elevating mechanism composed of a bolt 19 extending downward from a lower portion of the support 5 is disposed at a lower portion of the lower electrode 3 - 10380380. The lower electrode elevating mechanism supports the lower electrode 3 via the support 5, and rotates the bolt 19 by a motor (not shown) to raise and lower the lower electrode 3 as the GAP. The lower electrode elevating mechanism blocks the atmosphere in the processing chamber 2 by the bellows 20 disposed around the bellows 20 and the bellows cap 21 disposed around the bellows 20. Further, a plurality of push pins 22 projecting from the top surface of the electrostatic chuck 13 are disposed on the lower electrode 3. These push pins 22 are moved in the up and down direction in the drawing. In the etching processing apparatus 1, when the semiconductor wafer W is carried in and out, the lower electrode 3' is lowered to the loading/unloading position of the semiconductor wafer w, and the push pin 22 protrudes from the top surface of the electrostatic chuck 13, so that the push pin 22 protrudes from the top surface of the electrostatic chuck 13. The semiconductor wafer W is separated from the lower electrode 3 and lifted upward. Further, when the semiconductor wafer W is etched, the lower electrode 3 rises to the processing position of the semiconductor wafer W, and the push pin 22 is housed in the lower electrode 3, and the electrostatic chuck 13 holds and holds the semiconductor crystal. Round w. Further, for example, an annular refrigerant chamber 23 extending in the circumferential direction is provided inside the lower electrode 3. A refrigerant of a predetermined temperature (for example, cooling water) from a cooling unit (not shown) via a pipe 24 is circulated and supplied to the refrigerant chamber 23, and a semiconductor wafer placed on the lower electrode 3 by the temperature of the refrigerant The processing temperature of W will be controlled. A plurality of heat transfer gas supply holes and a heat transfer gas supply groove (not shown) are disposed on the top surface of the electrostatic chuck 13. These heat transfer gas supply holes and the like are connected to the heat transfer gas supply portion 26 via the heat transfer gas supply line 25' disposed inside the lower electrode 3; the heat transfer gas supply portion -11 - 1380360 26 A heat transfer gas such as He gas is supplied to the gap between the electrostatic chuck 13 and the semiconductor wafer W. The heat transfer gas supply unit 26 is also configured to be capable of evacuating a gap between the electrostatic chuck 13 and the semiconductor wafer W, and is disposed in the head portion 6 of the ceiling portion of the processing chamber 2, and is grounded (grounded). The head 6 functions as a ground electrode. Further, the buffer chamber 27 is provided on the top surface of the head 6, and the buffer chamber 27 is connected to the processing gas introduction pipe 28 from the processing gas supply unit (not shown). An MFC (Mass Flow Controller 'mass flow controller) 29 is disposed on the way of the process gas introduction pipe 28. The MFC 29 supplies a predetermined gas such as a processing gas, an N 2 gas, or the like to the processing chamber 2 via the buffer chamber 27 and the head 6, and controls the flow rate of the gas to interact with the exhaust system 18 to process the chamber 2 The pressure is controlled to the desired enthalpy. In the processing chamber 2 of the etching processing apparatus 1, as described above, high-frequency power is applied to the lower electrode 3, and the applied high-frequency power is applied between the lower electrode 3 and the shower head 6 by the processing gas. A high-density plasma is generated to generate ions and the like. In the etching processing apparatus 1, first, the gate valve 10 is opened, and the semiconductor wafer w to be processed is carried into the processing chamber 2. Then, the processing gas (for example, a mixed gas of at least one of a carbon tetrafluoride (CF4) gas and a specific oxygen gas (02) having a predetermined flow rate ratio) is first introduced into the treatment by a predetermined flow rate to flow ratio by the shower head 6. In the chamber 2, the pressure in the processing chamber 2 is further defined by the exhaust system 18 or the like. Further, high frequency power -12-1380360 is applied to the lower electrode 3 by the high frequency power source 11, and a direct current voltage is applied to the electrode plate 14 by the direct current power source 15, whereby the semiconductor wafer W is sucked onto the lower electrode 3. Further, the processing gas discharged from the head 6 is plasmatized as described above. The plasma is converged on the surface of the semiconductor wafer W by the magnetic flux ring 16, and the surface of the semiconductor wafer W is irradiated by ions generated by the plasma, such as fluoride ions, oxygen ions, and the like. For physical etching. As described above, in the case where the magnetism ring 16 is formed by tantalum carbide, as the tantalum carbide, tantalum carbide (hereinafter referred to as "sintered niobium carbide") formed by a sintering method and by a CVD method are used. Any of the formed niobium carbide (hereinafter referred to as "CVD niobium carbide"), but it is known that in the initial etching treatment, it is known that either the case of sintering tantalum carbide or the case of using CVD niobium carbide is used. Particles can occur in the magnetic ring 16. The mechanism for generating fine particles in the initial etching process is difficult to explain clearly. Therefore, the inventors of the present invention have similarly assumed that the magnetism ring made of tantalum carbide is produced. The collecting ring is disposed in the processing chamber of the etching processing apparatus, and the amount of generation of particles (carbonized carbide particles) from the collecting ring with respect to the etching treatment time and the amount of consumption of the collecting ring with respect to the etching processing time are observed. As a result, the inventors of the present invention confirmed that when the application time of the high-frequency power is 15 minutes, about 1/3 of the plurality of fine particles and fine particles are generated in the processing chamber 2 by the collecting magnetic ring. The consumption of the particles and the collecting ring is hardly carried out. Moreover, the inventors of the present invention confirmed that when the application time of the high-frequency power is 80 hours, the particles in the processing chamber continue to decrease. About 1/10 of the particles are particles 13 of the collecting ring. - 1380360, and the consumption of the magnetic ring continues. That is, the inventors of the present invention confirmed that the amount of generation of fine particles from the collecting magnetic ring continues to decrease with the consumption of the collecting magnetic ring. As a result, the inventors of the present invention have made the following assumptions as shown in Fig. 2 regarding the mechanism in which the particles are generated in the initial etching process. In the vicinity of the surface of the magnetism ring composed of tantalum carbide, there are many defects (indicated by "〇" in the figure) which are lack of voids formed by carbon '矽, etc., and the ratio of the existence of the defect is The higher the surface. Therefore, the magnetic ring is considered to have a brittle layer formed on its surface (Fig. 2(A)). In the initial etching process, if a substance such as ions collides with the brittle layer as indicated by an arrow in the figure, the kinetic energy of the ions is transmitted to the brittle layer, and the ceria molecules in the brittle layer are scattered, and the scattered tantalum carbide The molecule becomes a particle (Fig. 2(B)). When the semiconductor wafer W is subjected to an etching treatment for a long period of time, the magnetism collecting ring disposed so as to surround the periphery of the semiconductor wafer W consumes a brittle layer due to prolonged exposure to the plasma. Thus, a relatively dense layer (hereinafter referred to as "dense layer") under the brittle layer is exposed. As indicated by the arrow in the figure, even if a substance such as ions collides with the dense layer, since the intermolecular force of the niobium carbide in the dense layer is large, the niobium carbide molecules in the dense layer do not fly, and as a result, almost no occurrence occurs. Particles (Fig. 2 (C)). That is, the ratio of the presence of defects and the amount of occurrence of particles are closely related: when the ratio of defects is low, the amount of generation of particles is small. In response to this assumption, the method of manufacturing the device for the substrate processing of the first embodiment of the present invention is in the vicinity of the surface of the collecting ring which is an element for the substrate processing apparatus which is made of tantalum carbide. The defect presence ratio is reduced. Fig. 3 is a flowchart showing a part manufacturing process of a method for manufacturing a substrate processing apparatus according to a third embodiment of the present invention. In Fig. 3, first, a niobium carbide body having a desired size is formed by a sintering method or a CVD method, and the formed niobium carbide body is formed into a magneto-magnetic ring by cutting (step S31). Next, the formed magnetic ring is exposed to a plasma generated by a gas of at least one of carbon tetrafluoride gas and oxygen which generates impurities, and impurities such as fluoride ions and oxygen are generated by the plasma. The ions or the like are introduced into the pore-shaped defects existing in the vicinity of the surface of the magnetism collecting ring (defect existence ratio lowering step) (step S32). In step S32, first, as indicated by the hatched arrows in the figure, the plasma is irradiated toward the surface of the formed magnetism collecting ring, and fluorine ions, oxygen ions, and the like in the plasma are taken as impurities. Introduced into the defect by doping or ion implantation (Fig. 4(A)). Fluoride ions, oxygen ions, and the like introduced into the defect increase the electrical bonding force (intermolecular force) between the defect-oriented carbides. Further, fluorine ions, oxygen ions, and the like introduced into the defect remain in the defect (indicated by a hatched circle in the drawing), and as a result, the defect existence ratio near the surface of the collecting ring is lowered. Then, the surface layer of the magnetism ring becomes a relatively dense layer (hereinafter referred to as "impurity introduction layer") (Fig. 4(B)). At this time, fluoride ions, oxygen ions, etc., are only introduced into the polymagnetic ring.
1380360 面附近的缺陷中，所以不純物導入層的厚度薄 該不純物導入層之聚磁環配置在處理室內來進 的情況，由於蝕刻，不純物導入層會有在早期 然而，即使是在蝕刻處理中，聚磁環，由 由四氟化碳氣體與氧氣之至少一種氣體所組成 而被生成的電漿中（在圖中以空白箭頭來表示 純物導入層已經消耗，電漿中的不純物例如氟 子等，繼續地被導入不純物導入層消耗而被曝 的新的表面的附近之缺陷中。亦即，在新的表 陷的存在比率繼續地降低.，而形成新的不純物 4 圖（C ))。 因此，在步驟S 32的不純物導入中所使用 想爲與在蝕刻處理中所使用的電漿相同。 第5圖係表示在第3圖中的步驟S32的不 結果之圖表。 在第5圖中，縱軸爲各原子的密度，橫軸 表面算起的深度。在此圖表中，係表示先對由 所構成的聚磁環，施行不純物導入，再藉 Secondary Ion Mass Spectrometry )法，分析 不純物導入後的聚磁環之結果。 如圖所示，在被曝露於電漿中的聚磁環中 起至深度大約爲2vm程度爲止，存在氟原子 。因此，藉由不純物導入，電漿中的氟離子、 ，在將具有 行蝕刻處理 便消耗之虞 於被曝露在 的處理氣體 )，即使不 離子、氧離 露在電漿中 面附近，缺 導入層（第 的電漿，理 純物導入的 爲從聚磁環 燒結碳化矽 由 SIMS ( 已經被施行 ，由表面算 、氧原子等 氧離子等， -16- 1380360 被導入存在於深度2vm爲止之缺陷中。藉此，在被施行 不純物導入後的聚磁環中，被形成其厚度大約爲2#m的 不純物導入層。 燒結碳化矽的聚磁環與CVD碳化矽的聚磁環，在其 表面附近，皆有多數個空孔狀的缺陷，但是前述不純物導 入，由於可以對任一聚磁環施行，所以不論碳化矽的製造 方法爲何，能夠降低聚磁環的表面附近之缺陷存在比率。 第6圖係表示碳化矽的製造方法和缺陷存在比率之關 係的圖表。 在第6圖中，縱軸係對應缺陷存在比率之S參數，橫 軸係對應從聚磁環表面算起的深度之正電子能量。在此圖 表中，係表示藉由正電子消滅法，測量在由各種碳化矽所 構成的聚磁環的表面附近之缺陷存在比率的結果》 正電子消滅法，係先將從鈉放射性同位體被放出的正 電子，打入碳化矽中，再藉由監視由於該被打入的正電子 和碳化矽內的電子，例如內核電子、自由電子等的成對消 滅所發生的能量，來測量缺陷存在比率。 於正電子消滅法，在其缺陷存在比率低的情況，正電 子會侵入用來形成碳化矽的各原子的格子之間，與各原子 的內核電子之成對消滅的比例（以下稱爲「消滅比例」） 變高。另一方面，缺陷存在比率高的情況，正電子侵入各 缺陷，與缺陷中的自由電子之消滅比例變高。 —般而言，內核電子的動能，由於比自由電子的動能 大，所以正電子和內核電子成對消滅時所發生的能量，比 -17- 1380360 正電子和自由電子成對消滅時所發生的能量大。因此，藉 由監視成對消滅能量，能夠測量缺陷存在比率。例如，在 被測量出來的成對消滅能量大的情況，被認定缺陷存在比 率低。 又，s參數爲具有自由電子等之動能小的電子之消滅 比例；S參數越小，動能大的電子亦即與內核電子之消滅 比例變多。因此，在第6圖的圖表中，S參數越小，表示 缺陷存在比率越低。 又，被打入碳化矽中的正電子的能量越大，正電子便 越會侵入碳化砂的深部。因此，在第6圖的圖表中，係顯 示出橫軸的正電子能量越大，從碳化矽的表面算起的深度 越深。 針對第6圖的圖表，「·」係表示燒結碳化矽、「▲ 」係表示低電阻的CVD碳化矽、「▼」係表示高電阻的 CVD碳化矽、「〇」係表示被施行不純物導入後的燒結碳 化矽、「△」係表示被施行不純物導入後的低電阻的CVD 碳化矽、「▽」係表示被施行不純物導入後的高電阻的 CVD碳化矽。此處，高電阻的CVD碳化矽的電阻値，例 如爲1 0000 Ω cm，低電阻的CVD碳化矽的電阻値，例如 爲 0.01 〜O.lQcm。 如第6圖的圖所示，沒有被施行不純物導入之燒結碳 化矽、低電阻的CVD碳化矽、及高電阻的CVD碳化矽之 正電子的能量爲〇，亦即碳化矽的表面的S參數互相相異 :燒結碳化矽，其S參數最大；低電阻的CVD碳化矽， -18- 1380360 其s參數最小。因此，沒有被施行不純物導入的 結碳化矽的缺陷存在比率最高，低電阻的CVD 缺陷存在比率最低。 若對各碳化矽施行不純物導入，則不論碳化 方法爲何，S參數變小。例如，被施行不純物導 結碳化矽的S參數，會比沒有被施行不純物導入 的CVD碳化矽的S參數小。亦即，作爲聚磁環 即使是使用燒結碳化矽的情況，藉由施行不純物 較於沒有被施行不純物導入之低電阻的CVD碳 夠降低缺陷存在比率。 因此，作爲聚磁環的材料，即使是在使用燒 的情況，藉由施行不純物導入，能夠使初期的蝕 的微粒的發生率，比沒有施行不純物導入之低電 碳化矽的發生率低。 ' 又’被施行不純物導入後的燒結碳化矽、 CVD碳化矽、及高電阻的CVD碳化矽，在碳化 面’由於顯示出相同的S參數，所以藉由施行不 ’不論碳化矽的製造方法爲何，能夠將缺陷存在 至同一的低水平爲止。 因此，作爲聚磁環的材料，即使是在使用燒 的情況’藉由施行不純物導入，能夠使初期的蝕 的微粒的發生率，降低至與施行不純物導入後的 化矽的發生率同一的低水平爲止。 回到第3圖’接著，將正電子打入已經被導 情況，燒 碳化矽的 矽的製造 入後的燒 之低電阻 的材料， 導入，相 化矽，能 結碳化矽 刻處理中 阻的C V D 低電阻的 矽體的表 純物導入 比率降低 結碳化砂 刻處理中 CVD碳 入不純物 -19- 1380360 之聚磁環的表面附近，藉由正電子消滅法，檢查在聚磁環 的表面附近之缺陷存在比率（檢查步驟）（步驟S33)。 被檢測出來的缺陷存在比率，在比規定的値低的情況，該 聚磁環被配置在處理室內；被檢測出來的缺陷存在比率， 在沒有比規定的値低的情況，該聚磁環沒有被配置在處理 室內。 若根據有關本發明的第1實施形態之基板處理裝置用 元件及其製造方法，由於不純物被導入存在於作爲基板處 理裝置用元件之由碳化矽所構成的聚磁環的表面附近之空 孔狀的缺陷中，所以聚磁環的表面附近的缺陷存在比率降 低。具體而言，聚磁環的表面附近的缺陷存在比率，會比 沒有被施行不純物導入之CVD碳化矽體的表面附近的缺 陷存在比率低。若表面附近的缺陷存在比率降低，則初期 的蝕刻處理中的微粒的發生率降低。因此，能夠抑制從聚 磁環來的微粒的發生，且由於不需要長時間的陳化處理， 所以能夠防止蝕刻處理裝置的運轉率的降低。又，以微粒 飛散防止爲目的之硏磨加工，變成不需要；進而，即使是 在使用製造比較容易的燒結碳化矽的情況，由於也能夠使 在初期的蝕刻處理中的微粒的發生率降低，所以能夠容易 地製造聚磁環。 又，在前述本實施形態，即使是在蝕刻處理中，聚磁 環，由於被曝露在由四氟化碳氣體與氧氣之至少一種氣體 所組成的處理氣體而被生成的電漿中’所以作爲不純物， 從該電漿來的氟離子、氧離子等，·被導入缺陷中。因此， -20- 1380360 能夠容易地對存在於表面附近的缺陷進行不純物的導入， 進而，即使聚磁環的不純物導入層已經消耗，電漿中的氟 離子、氧離子等，也會繼續地被導入該不純物導入層消耗 而被曝露在電漿中的新的表面的附近之缺陷中。亦即，在 新的表面附近，缺陷的存在比率繼續地降低，而能夠繼續 地形成新的不純物導入層。 又，在前述本實施形態，係對不純物已經被導入存在 於其表面附近之空孔狀的缺陷中之聚磁環的表面附近，打 入正電子，並藉由正電子消滅法，檢查在聚磁環的表面附 近之缺陷存在比率。正電子消滅法，能夠容易地檢測出由 碳化矽所構成的聚磁環的表面附近的缺陷存在比率。因此 ，不用進行長時間的實物評價，便能夠容易地判定有無從 聚磁環發生微粒，因而能夠容易地製造出聚磁環。 接著，說明關於本發明的第2實施形態的基板處理裝 置用元件及其製造方法。 本實施形態，其構成、作用，基板上與前述第1實施 形態相同，針對基板處理裝置用元件之製造方法，其相異 點僅在於不是前述的不純物導入，而是使用熱處理。因此 ’省略有關重複的構成、作用之說明，以下僅進行有關相 異的構成、作用的說明。 針對作爲有關本實施形態的基板處理裝置用元件之聚 磁環’也與前述聚磁環16同樣，其存在於表面附近之缺 陷存在比率，係被設定成比CVD碳化矽體的表面附近之 缺陷存在比率低。本實施形態的聚磁環，與聚磁環1 6相 -21 - 1380360 異之點，在於係藉由有關後述的本實施形態之基板 置用元件之製造方法，而被製造出來。 以下，就有關本實施形態的基板處理裝置用元 造方法，加以說明。該製造方法，係對應在前述初 刻處理中會發生微粒的機構的假設，與有關第1實 之基板處理裝置用元件的製造方法同樣地使存在於 矽所構成之作爲基板處理裝置用元件的聚磁環的表 之缺陷存在比率降低。 第7圖係作爲有關本發明的第2實施形態之基 裝置用元件的製造方法之零件製造處理的流程圖。 第7圖的處理中的步驟S31與S33，與第3圖的步 與S33相同。 在第7圖中，於步驟S3 1之後，在非活性氣體 中，使被成形後的聚磁環的溫度上升至1 200°C，來 磁環的熱處理（退火）（缺陷存在比率降低步驟 驟 S72 )。 具體而言，於步驟S 72，係將聚磁環配置在氬 中，將該聚磁環的溫度維持在120(TC，持續20分 。此時，熱熔融後的碳化矽的分子等，發生流動， 磁環的表面附近的空孔狀缺陷，而使其消滅。藉此 存在於聚磁環的表面附近之缺陷存在比率。 第8圖係表示在第7圖中的步驟S 72的熱處理 之圖表。 在第8圖中，縱軸係對應缺陷存在比率之S參 處理裝 件之製 期的蝕 施形態 由碳化 面附近 板處理 再者， 驟S3 1 的氣氛 進行聚 )(步 的氣氛 鐘以上 充塡聚 ，降低 的結果 數，橫 -22- 1380360 軸係對應從聚磁環表面算起的深度之正電子能量。 在此圖表中’係表示利用正電子消滅法，測量在已經 利用1400 °C將聚磁環作熱處理後的情況中之缺陷存在比率 的結果。如圖表所示，S參數，在從表面至200nm (0.2 V m )的深度之間，急速地變小。亦即，聚磁環的表面附 近之缺陷存在比率降低。此傾向，不論是燒結碳化矽與 CVD碳化矽的任一種，皆是如此。 再者’聚磁環的溫度，若成爲1 400°C以上，則碳化矽 開始蒸發，若成爲1 600°C以上，則由於該蒸發變激烈，所 以在步驟S72的熱處理中，係將聚磁環的溫度設成1200 。(：〜1 600°C，理想爲設成 120CTC 〜1 400。(：。 若根據有關本發明的第2實施形態之基板處理裝置用 元件及其製造方法，由於作爲基板處理裝置用元件之由碳 化矽所構成的聚磁環，被進行熱處理，所以存在於表面附 近的空孔狀缺陷消滅，於是聚磁環的表面附近之缺陷存在 比率降低。若表面附近之缺陷存在比率降低，則在初期的 蝕刻處理中，微粒的發生率降低。因此，能夠抑制從聚磁 環來的微粒的發生，且由於不需要長時間的陳化處理，所 以能夠防止蝕刻處理裝置的運轉率的降低。又，由於以微 粒飛散防止爲目的之硏磨加工變成不需要，所以能夠容易 地製造聚磁環。 又，在步驟S72的熱處理中，聚磁環的溫度係被設成 1 2 00 °C〜1 600°C，所以除了熱處理被促進，並能夠抑制聚 磁環的碳化矽的蒸發。 -23- 1380360 在前述實施形態中，係說明了關於將本發明適用 爲基板處理裝置用元件之聚磁環上的情況，但是本發 以適用之基板處理裝置用元件，並未被限定於聚磁環 如，只要是上部電極、排氣整流環、遮蔽環等之被使 消耗環境下之基板處理裝置用元件，便可以適用本發 又，本發明的製造方法，不僅可以適用於基板處 置用元件，也可以適用於與基板處理裝置用元件同樣 使用在消耗環境下，例如加載互鎖真空室等的搬送裝 構成元件上》 在前述實施形態中，被處理的基板爲半導體晶圓 是被處理的基板並未被限定爲半導體晶圓，例如也可 LCD ( Liquid Crystal Display，液晶顯示器）' FPD ( Panel Display，平面顯示器）等的玻璃基板。 [發明之效果] 若根據申請專利範圍第1項所記載之基板處理裝 元件的製造方法，存在於基板處理裝置用元件的表面 之空孔狀缺陷的存在比率降低。若空孔狀缺陷的存在 降低，則初期的蝕刻處理中的微粒的發生率降低。因 能夠抑制從基板處理裝置用元件來的微粒的發生，且 要長時間的陳化處理，所以能夠防止基板處理裝置的 率的降低。又，以微粒飛散防止爲目的之硏磨加工， 不需要：進而，即使是在使用藉由其製造比較容易的 法所形成的碳化矽的情況，由於也能夠使在初期的蝕 在作 明可 。例 用於 明。 理裝 地被 置的 ，但 以是 ：Flat 置用 附近 比率 此， 不需 運轉 變成 燒結 刻處 -24- 1380360 理中的微粒的發生率降低’所以能夠容易地製造出基板處 理裝置用元件。 若根據申請專利範圍第2項所記載之基板處理裝置用 兀件的製造方法，由於不純物被導入存在於基板處理裝置 用元件的表面附近之空孔狀的缺陷中，所以能夠確實地使 該缺陷的存在比率降低。 若根據申請專利範圍第3項所記載之基板處理裝置用 元件的製造方法，由於不純物係由含氟氣體、含碳氣體、 及含氧氣體之中的至少一種的氣體所生成的電漿，而被生 成’所以能夠容易地進行往存在於表面附近的缺陷之導入 。又’這些電獎，由於在蝕刻處理中也會被生成，所以在 蝕刻處理中，從這些電漿所生成的不純物，繼續地進行往 缺陷之導入。因此，能夠繼續地降低缺陷的存在比率。 若根據申請專利範圍第4項所記載之基板處理裝置用 元件的製造方法，由於基板處理裝置用元件被作熱處理， 所以能夠使存在於表面附近的空孔狀缺陷消滅，而確實地 降低缺陷的存在比率。 若根據申請專利範圍第5項所記載之基板處理裝置用 元件的製造方法，由於在非活性氣體的氣氛中，基板處理 裝置用元件的溫度，係被設成1 2 0 0 °C〜1 6 0 0 °C，所以能夠 促進熱處理，並能夠抑制基板處理裝置用元件的構成材料 的蒸發。 若根據申請專利範圍第6項所記載之基板處理裝置用 元件的製造方法，基板處理裝置用元件的表面附近，係藉 -25- 1380360 由正電子消滅法而被檢查。正電子 測出存在於處理裝置用元件的表面 在比率。因此，能夠容易地判定有 件發生微粒，因而能夠容易地製造 〇 若根據申請專利範圍第7項所 元件，存在於表面附近之空孔狀缺 在於藉由CVD法而被形成的碳化 狀缺陷的存在比率低。空孔狀缺陷 CVD法所形成的碳化矽體的空孔狀 在初期的蝕刻處理中的微粒的發生 制從基板處理裝置用元件來的微粒 間的陳化處理，所以能夠防止基板 低。又，以微粒飛散防止爲目的之 :進而，即使是在使用藉由其製造 成的碳化矽的情況，由於也能夠使 微粒的發生率降低，所以能夠容易 用元件。 【圖式簡單說明】 第1圖係表示使用了作爲有關 的基板處理裝置用元件的聚磁環之 成的剖面圖。 第2圖係表示在初期的蝕刻處 消滅法，能夠容易地檢 附近之空孔狀的缺陷存 無從基板處理裝置用元 出基板處理裝置用元件 記載之基板處理裝置用 陷的存在比率，係比存 矽體的表面附近之空孔 的存在比率，若比藉由 缺陷的存在比率低，則 率降低。因此，能夠抑 的發生，且不需要長時 處理裝置的運轉率的降 硏磨加工，變成不需要 比較容易的燒結法所形 在初期的蝕刻處理中的 地製造出基板處理裝置 本發明的第1實施形態 基板處理裝置的槪略構 理中，發生微粒之機構 -26- 1380360 的圖。 第3圖係作爲有關本實施形態之基板處理裝置用元件 的製造方法之零件製造處理的流程圖。 第4圖係表示在第3圖中的步驟S32的不純物導入的 . 過程之圖。 . 第5圖係表示在第3圖中的步驟S32的不純物導入的 結果之圖表。 φ 第6圖係表示碳化矽的製造方法和缺陷存在比率之關 係的圖表。 第7圖係作爲有關本發明的第2實施形態之基板處理 • 裝置用元件的製造方法之零件製造處理的流程圖。 第8圖係表示在第7圖中的步驟S72的熱處理的結果 之圖表。 【主要元件符號說明】 • W :半導體晶圓 1 :蝕刻處理裝置 _ 2 :處理室 • 3 :下部電極 4 :絕緣材 5 :支持體 6 :噴頭 7 :上室 8 :下室 -27- 1380360 9 :偶極環磁石 1 〇 :閘閥 1 1 :局頻電源 12 :匹配器 1 3 :靜電夾盤 1 4 :電極板 1 5 :直流電源 1 6 :聚磁環 17 :擋板 1 8 :排氣系統 19 :螺栓 2 〇 :伸縮囊 2 1 :伸縮囊蓋 22 :推進銷 23 :冷媒室 24 :配管 2 5 :傳熱氣體供給管線 26 :傳熱氣體供給部 2 7 :緩衝室 28:處理氣體導入管 29 : MFC (質量流量控制器） -28-1380360 The defect near the surface, so the thickness of the impurity-impermeable layer is thin. The polymagnetic ring of the impurity-impermeable layer is disposed in the processing chamber. Due to the etching, the impurity-impermeable layer may be in the early stage, however, even in the etching process. a collecting magnetic ring, which is formed by a plasma composed of at least one gas of carbon tetrafluoride gas and oxygen (in the figure, a blank arrow indicates that the pure substance introduction layer has been consumed, and impurities in the plasma such as fluorine are used. Etc., continues to be introduced into the vicinity of the new surface exposed by the impurity introduction layer, that is, the existence ratio of the new surface depression continues to decrease, and a new impurity is formed (Fig. 4C). Therefore, the use in the impurity introduction in step S32 is the same as that used in the etching process. Fig. 5 is a graph showing the result of the step S32 in Fig. 3 . In Fig. 5, the vertical axis represents the density of each atom and the depth of the horizontal axis. In this graph, the results of the introduction of impurities into the collecting magnetic ring are first introduced, and the results of the polymagnetic ring after the introduction of the impurity are analyzed by the Secondary Ion Mass Spectrometry method. As shown in the figure, there is a fluorine atom in the polymagnetic ring exposed to the plasma to a depth of about 2 vm. Therefore, by the introduction of impurities, the fluorine ions in the plasma are consumed by the etching process, which is consumed by the etching process, even if no ions or oxygen are exposed to the vicinity of the plasma surface. The layer (the first plasma, the pure material is introduced from the polymagnetic ring, the tantalum carbide is sintered by SIMS (has been applied, and the surface is calculated, oxygen atoms, etc., etc., -16-1380360 is introduced at a depth of 2vm) In the defect, the impurity-introducing layer having a thickness of about 2 #m is formed in the collecting magnetic ring after the introduction of the impurity. The polymagnetic ring of the sintered niobium carbide and the polymagnetic ring of the CVD niobium carbide are In the vicinity of the surface, there are many void-like defects. However, since the introduction of the impurities can be performed on any of the magnetism rings, the ratio of the defects in the vicinity of the surface of the magnetism ring can be reduced regardless of the method of manufacturing the niobium carbide. Fig. 6 is a graph showing the relationship between the method for producing niobium carbide and the ratio of defects present. In Fig. 6, the vertical axis corresponds to the S parameter of the defect existence ratio, and the horizontal axis corresponds to the polymagnetic ring table. The positron energy of the depth calculated. In this graph, the positron extinction method is used to measure the ratio of the presence of defects in the vicinity of the surface of the magnetism ring composed of various kinds of niobium carbide by the positron extinction method. The positron emitted from the sodium radioactive isol is first injected into the niobium carbide, and the pair is eliminated by monitoring the electrons in the positron and the niobium carbide, such as the core electrons and the free electrons. The energy generated to measure the defect existence ratio. In the case of the positron emission elimination method, in the case where the defect ratio is low, the positron will invade between the lattices of the atoms used to form the tantalum carbide, and the core electrons of each atom The ratio of the pair elimination (hereinafter referred to as the "elimination ratio") becomes higher. On the other hand, when the defect ratio is high, the positron intrudes into each defect, and the ratio of the free electrons in the defect becomes high. The kinetic energy of the core electrons, because of the greater kinetic energy than the free electrons, the energy that occurs when the positron and the core electrons are destroyed in pairs, than the -17-1380360 positron and The energy generated when the electrons are destroyed in pairs is large. Therefore, by monitoring the paired extinguishing energy, it is possible to measure the defect existence ratio. For example, in the case where the measured paired extinguishing energy is large, it is determined that the defect existence ratio is low. Further, the s parameter is an erasing ratio of electrons having a small kinetic energy such as free electrons; the smaller the S parameter is, the more the electrons having a large kinetic energy are eliminated from the core electrons. Therefore, in the graph of Fig. 6, the S parameter The smaller the value, the lower the defect existence ratio. The larger the energy of the positron that is driven into the tantalum carbide, the more the positron will intrude into the deep part of the carbonized sand. Therefore, in the graph of Fig. 6, it is shown. The larger the positron energy on the horizontal axis, the deeper the depth from the surface of the tantalum carbide. For the graph in Fig. 6, "·" indicates that the tantalum carbide is sintered, and "▲" indicates that the low-resistance CVD carbon carbide is " ▼" indicates high-resistance CVD carbonized tantalum, "〇" indicates sintered tantalum carbide after introduction of impurities, and "△" indicates low-resistance CVD tantalum carbide after introduction of impurities, "▽" It is a high-resistance CVD niobium carbide which is subjected to introduction of impurities. Here, the resistance 値 of the high-resistance CVD niobium carbide is, for example, 1 0000 Ω cm, and the resistance 値 of the low-resistance CVD niobium carbide is, for example, 0.01 to 0.1 cm. As shown in the graph of Fig. 6, the energy of the positron of the sintered tantalum carbide, the low-resistance CVD tantalum carbide, and the high-resistance CVD tantalum carbide which are not subjected to impurity introduction is 〇, that is, the S parameter of the surface of the tantalum carbide Different from each other: sintered tantalum carbide with the largest S-parameter; low-resistance CVD tantalum carbide, -18-1380360 with the smallest s-parameter. Therefore, the defect-forming ratio of the carbonized niobium which is not introduced by the impurity is the highest, and the ratio of the low-resistance CVD defect is the lowest. When impurity is introduced into each of the tantalum carbides, the S parameter becomes small regardless of the carbonization method. For example, the S parameter of the impurity-conducting niobium carbide is less than the S-parameter of the CVD niobium carbide which is not introduced with the impurity. That is, as the polymagnetic ring, even in the case where sintered niobium carbide is used, the defect existence ratio is lowered by performing the impurity to be lower than that of the low-resistance CVD carbon to which the impurity is not introduced. Therefore, as the material of the magnetism collecting ring, even when the burning is performed, the incidence of the primary etched particles can be made lower than that of the low-carbonized ruthenium introduced without the introduction of the impurities by the introduction of the impurity. 'By' is a sintered carbonized tantalum, a CVD tantalum carbide, and a high-resistance CVD tantalum carbide after the introduction of impurities, and since the carbonized surface 'shows the same S-parameters, the manufacturing method is not performed regardless of the tantalum carbide. It is possible to have defects at the same low level. Therefore, as the material of the magnetism collecting ring, even when the burning is used, the introduction of the impurity can reduce the incidence of the initial etched particles to the same level as the incidence of the ruthenium after the introduction of the impurity. Up to the level. Go back to Figure 3, and then, the positron is injected into the material that has been guided, and the sintered low-resistance material after the carbonization of the crucible is introduced, and the phase is transformed into a carbonization engraving process. The surface pure matter introduction ratio of the CVD low-resistance ruthenium is reduced in the vicinity of the surface of the polymagnetic ring of the CVD carbon into the impurity -19-38080 in the carbonization sanding treatment, and is examined by the positron extinction method near the surface of the magnetic resonance ring. The defect existence ratio (inspection step) (step S33). The ratio of the detected defects is lower than the predetermined enthalpy, and the concentrating ring is disposed in the processing chamber; the detected defect has a ratio, and in the case where there is no lower than the specified enthalpy, the collecting ring does not have It is configured in the processing room. According to the element for a substrate processing apparatus and the method of manufacturing the same according to the first embodiment of the present invention, the impurity is introduced into the pores existing in the vicinity of the surface of the magnetism ring made of tantalum carbide as the element for the substrate processing apparatus. Among the defects, the ratio of defects near the surface of the collecting ring is lowered. Specifically, the ratio of the defects in the vicinity of the surface of the collecting ring is lower than the ratio of the defects in the vicinity of the surface of the CVD carbide body to which the impurity is not introduced. When the ratio of the defects in the vicinity of the surface is lowered, the incidence of fine particles in the initial etching treatment is lowered. Therefore, it is possible to suppress the occurrence of fine particles from the magnetizing ring, and since it is not necessary to perform the aging treatment for a long period of time, it is possible to prevent a decrease in the operating rate of the etching processing apparatus. In addition, it is not necessary to perform honing processing for the purpose of preventing the scattering of the fine particles. Further, even in the case of using sintered tantalum carbide which is relatively easy to manufacture, the incidence of fine particles in the initial etching treatment can be lowered. Therefore, the magnetism collecting ring can be easily manufactured. Further, in the above-described embodiment, even in the etching process, the magnetism collecting ring is exposed to the plasma generated by the processing gas composed of at least one of the carbon tetrafluoride gas and the oxygen gas. Impurities, fluoride ions, oxygen ions, etc. from the plasma are introduced into defects. Therefore, -20- 1380360 can easily introduce impurities into the defects existing near the surface, and further, even if the impurity introduction layer of the magnetism ring has been consumed, fluorine ions, oxygen ions, etc. in the plasma will continue to be The introduction of the impurity introduction layer is consumed and exposed to defects in the vicinity of a new surface in the plasma. That is, in the vicinity of the new surface, the existence ratio of the defects continues to decrease, and a new impurity introduction layer can be continuously formed. Further, in the present embodiment, the positron is injected into the vicinity of the surface of the collecting ring in which the impurity has been introduced into the void-like defect existing near the surface thereof, and the positron is destroyed by the positron erasing method. There is a ratio of defects near the surface of the magnetic ring. With the positron erasing method, the ratio of the defects in the vicinity of the surface of the collecting ring composed of tantalum carbide can be easily detected. Therefore, it is possible to easily determine whether or not particles are generated from the collecting ring without performing long-term physical evaluation, and thus the collecting ring can be easily manufactured. Next, an element for a substrate processing apparatus according to a second embodiment of the present invention and a method of manufacturing the same will be described. In the present embodiment, the configuration and operation of the substrate are the same as in the first embodiment, and the method of manufacturing the substrate processing device element differs only in that the impurity is not introduced as described above, but heat treatment is used. Therefore, the description of the configuration and action of the repetition will be omitted, and only the description of the different configurations and operations will be given below. In the same manner as the above-described magneto-gear 16 of the magnetism ring of the substrate processing apparatus according to the present embodiment, the ratio of the defects existing in the vicinity of the surface is set to be smaller than the surface of the CVD carbide body. The ratio of existence is low. The magnetism ring of the present embodiment differs from the magnetism ring 16 phase -21 - 1380360 in that it is manufactured by a method for manufacturing a substrate-usaging element according to the present embodiment to be described later. Hereinafter, a method of manufacturing a substrate processing apparatus according to the present embodiment will be described. In the same manner as the manufacturing method of the element for the substrate processing apparatus according to the first embodiment, the manufacturing method is based on the element for the substrate processing apparatus. The defect ratio of the surface of the polymagnetic ring is lowered. Fig. 7 is a flowchart showing a part manufacturing process as a method of manufacturing a device for a base device according to a second embodiment of the present invention. Steps S31 and S33 in the processing of Fig. 7 are the same as steps S33 in Fig. 3 . In Fig. 7, after the step S31, the temperature of the formed magnetism ring is raised to 1,200 ° C in the inert gas to heat-treat (anneal) the magnetic ring (defect presence ratio reduction step) S72). Specifically, in step S72, the collecting magnetic ring is placed in argon, and the temperature of the collecting magnetic ring is maintained at 120 (TC for 20 minutes. At this time, the molecules of the carbonized germanium after the heat melting occur, etc. Flow, a hole-shaped defect near the surface of the magnetic ring, which is destroyed, whereby the defect exists in the vicinity of the surface of the magnetism ring. Fig. 8 shows the heat treatment of step S72 in Fig. 7. In Fig. 8, the vertical axis is the treatment pattern of the S-parameter processing component corresponding to the defect existence ratio, and the etching process is performed by the vicinity of the carbonized surface, and the atmosphere of the step S3 1 is concentrated. The above is full of polycondensation, the number of results is reduced, and the horizontal -22-38080 axis corresponds to the positron energy of the depth from the surface of the collecting ring. In this chart, the quotation indicates that the positron elimination method is used, and the measurement has already utilized 1400. °C The result of the ratio of the defects in the case where the polymagnetic ring is subjected to heat treatment. As shown in the graph, the S parameter rapidly decreases between the depth from the surface to 200 nm (0.2 V m ). There is a ratio drop in the defect near the surface of the collecting ring This tendency is the same regardless of either sintered tantalum carbide or CVD tantalum carbide. In addition, if the temperature of the polymagnetic ring is 1 400 ° C or higher, the niobium carbide begins to evaporate, and if it becomes 1 600 ° In the case of C or more, since the evaporation is severe, in the heat treatment of the step S72, the temperature of the collecting ring is set to 1200. (: 〜1 600 ° C, preferably 120 CTC 〜1 400. (: If According to the element for a substrate processing apparatus and the method of manufacturing the same according to the second embodiment of the present invention, the magnetism ring made of tantalum carbide as the element for the substrate processing apparatus is heat-treated, so that it exists in the vicinity of the surface. When the shape defect is eliminated, the ratio of the defect in the vicinity of the surface of the collecting ring is lowered. When the ratio of the defect in the vicinity of the surface is lowered, the incidence of the particles is lowered in the initial etching process. Therefore, it is possible to suppress the occurrence of the particle from the collecting ring. Since the generation of fine particles does not require a long-time aging treatment, it is possible to prevent a decrease in the operation rate of the etching treatment apparatus, and further, the honing addition for the purpose of preventing the scattering of the particles Since the work becomes unnecessary, the magnetism ring can be easily manufactured. Further, in the heat treatment of step S72, the temperature of the magnetism ring is set to 1 200 ° C to 1 600 ° C, so that heat treatment is promoted, and It is possible to suppress the evaporation of the ruthenium carbide of the magnetism ring. -23- 1380360 In the above embodiment, the case where the present invention is applied to a magnetism ring of an element for a substrate processing apparatus has been described, but the substrate to which the present invention is applied is described. The component for the processing device is not limited to the magnetism ring, and the present invention can be applied to the substrate processing device element in an environment where the upper electrode, the exhaust rectifier ring, and the shielding ring are consumed. In the above-described embodiment, the manufacturing method can be applied not only to the substrate-disposing element but also to the substrate processing device element in a consumable environment, for example, a load-carrying vacuum chamber or the like. The substrate to be processed is a semiconductor wafer, and the substrate to be processed is not limited to a semiconductor wafer, for example, an LCD (Liquid Crystal Display) Glass substrate such as FPD (panel display). According to the method of manufacturing a substrate processing device according to the first aspect of the invention, the ratio of the existence of the void-like defects existing on the surface of the substrate processing device element is lowered. When the existence of the void-like defects is lowered, the incidence of fine particles in the initial etching treatment is lowered. Since the occurrence of fine particles from the substrate processing apparatus element can be suppressed and the aging process is performed for a long period of time, it is possible to prevent a decrease in the rate of the substrate processing apparatus. Further, in the honing process for the purpose of preventing the scattering of the particles, it is not necessary to further etch the ruthenium in the initial stage even when the ruthenium carbide formed by the method which is relatively easy to manufacture is used. . Example for use. However, it is possible to easily manufacture the components for the substrate processing apparatus by using the nearby ratio, which does not need to be operated, and becomes a sintered spot. -24- 1380360 The incidence of fine particles is lowered. According to the method for manufacturing a substrate for a substrate processing apparatus according to the second aspect of the invention, since the impurity is introduced into the hole-shaped defect existing in the vicinity of the surface of the substrate processing device element, the defect can be reliably obtained. The ratio of existence is reduced. According to the method for producing a substrate processing apparatus according to the third aspect of the invention, the impurity is a plasma generated by a gas containing at least one of a fluorine-containing gas, a carbon-containing gas, and an oxygen-containing gas. It is generated' so that the introduction of defects existing in the vicinity of the surface can be easily performed. Further, since these electric prizes are also generated during the etching process, the impurities generated from these plasmas are continuously introduced into the defects during the etching process. Therefore, it is possible to continuously reduce the existence ratio of defects. According to the method for manufacturing a substrate processing apparatus according to the fourth aspect of the invention, since the element for the substrate processing apparatus is subjected to heat treatment, the void-like defect existing in the vicinity of the surface can be eliminated, and the defect can be surely reduced. There is a ratio. According to the method of manufacturing a substrate processing apparatus according to the fifth aspect of the invention, in the atmosphere of the inert gas, the temperature of the element for the substrate processing apparatus is set to 1 2 0 0 ° C to 1 6 At 0 0 °C, heat treatment can be promoted, and evaporation of constituent materials of the substrate processing apparatus element can be suppressed. According to the method for producing a substrate processing apparatus according to the sixth aspect of the invention, the surface of the substrate processing device is inspected by the positron erasing method by -25 to 1380360. The positron is measured at the surface of the component for the processing device at the ratio. Therefore, it is possible to easily determine that the generated particles are generated, and thus it is possible to easily manufacture the material. According to the element of the seventh aspect of the patent application, the void-like defect existing in the vicinity of the surface is a carbonized defect formed by the CVD method. The ratio of existence is low. Porous hole-shaped voids of the carbonized carbide body formed by the CVD method The generation of fine particles in the initial etching process is performed by the aging of the particles from the substrate processing apparatus element, so that the substrate can be prevented from being low. Further, in order to prevent the occurrence of the scattering of the particles, in addition, even when the niobium carbide produced by the niobium carbide is used, the incidence of the fine particles can be lowered, so that the element can be easily used. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the use of a magnetism collecting ring as an element for a substrate processing apparatus. Fig. 2 is a view showing the existence ratio of the substrate processing apparatus in the substrate processing apparatus, and the ratio of the existence of the substrate processing apparatus in the substrate processing apparatus. When the ratio of the existence of the pores near the surface of the storage body is lower than the ratio of the presence of the defects, the rate is lowered. Therefore, it is possible to produce a substrate processing apparatus according to the present invention, which is capable of suppressing the occurrence of a long-time processing apparatus and reducing the operating rate of the apparatus, and forming a substrate processing apparatus in an initial etching process that does not require a relatively easy sintering method. In the schematic configuration of the substrate processing apparatus of the embodiment, a diagram of the mechanism 26 - 1380360 of the microparticles is generated. Fig. 3 is a flowchart showing a part manufacturing process as a method of manufacturing an element for a substrate processing apparatus according to the present embodiment. Fig. 4 is a view showing the process of introducing impurities in the step S32 in Fig. 3. Fig. 5 is a graph showing the result of the impurity introduction in the step S32 in Fig. 3. φ Fig. 6 is a graph showing the relationship between the method of manufacturing niobium carbide and the ratio of defect existence. Fig. 7 is a flowchart showing a part manufacturing process of a substrate processing method for manufacturing a device according to a second embodiment of the present invention. Fig. 8 is a graph showing the results of the heat treatment in step S72 in Fig. 7. [Description of main component symbols] • W: Semiconductor wafer 1: Etch processing device _ 2: Processing chamber • 3: Lower electrode 4: Insulator 5: Support 6: Nozzle 7: Upper chamber 8: Lower chamber -27- 1380360 9: Dipole ring magnet 1 〇: Gate valve 1 1 : Local frequency power supply 12 : Matcher 1 3 : Electrostatic chuck 1 4 : Electrode plate 1 5 : DC power supply 1 6 : Polymagnetic ring 17 : Baffle 1 8 : Row Gas system 19: bolt 2 〇: bellows 2 1 : bellows 22 : push pin 23 : refrigerant chamber 24 : pipe 2 5 : heat transfer gas supply line 26 : heat transfer gas supply unit 2 7 : buffer chamber 28 : treatment Gas introduction pipe 29 : MFC (mass flow controller) -28-