201001530 六、發明說明 【發明所屬之技術領域】 本發明係關於電極構造及基板處理裝置，尤其關於被 配置在基板處理裝置之處理室內連接直流電源之電極構造 【先前技術】 對當作基板之晶圓施予電漿處理之基板處理裝置具備 收容晶圓之處理室，和配置在該處理室內而載置晶圓之載 置台，和對處理室內之處理空間供給處理氣體之噴淋頭。 該基板處理裝置係在載置台連接高頻電源，載置台對處理 空間施加高頻電力，被供給至處理空間之處理氣體藉由高 頻電力被激發而成爲電漿（陽離子或電子）。 因處理空間中之電漿分佈對晶圓之電槳處理之結果造 成大影響，故以積極性控制電槳分佈爲佳，對應此爲了控 制電漿分佈尤其係電子密度分佈，執行對噴淋頭施加直流 電壓。 於對噴淋頭施加直流電壓之時，於噴淋頭之構成構件 即係露出於處理空間之圓板狀之天井電極板連接直流電源 。在此，當對噴淋頭施加負之直流電壓之時’該噴淋頭只 引入電漿中之陽離子。直流電壓因與高頻電壓不同，電位 不經時間變化，故陽離子持續地被引入噴淋頭。再者，被 引入噴淋頭之陽離子自該噴淋頭之構成原子釋放出二次電 子。其結果，在與處理空間之噴淋頭相向之部分’電子密 -5- 201001530 度提高（例如，參照專利文獻1 )。 〔專利文獻1〕日本特開2006-270019號公報 【發明內容】 (發明所欲解決之課題） 但是，電子密度分佈受到處理室之形狀等之影響’在 處理空間中有成爲不均勻之情形，但於以一片導電板構成 天井電極板之時，即使對天井電極板施加直流電壓，因僅 有與噴淋頭相向之處理空間中之所有部份之電子密度提高 ，故無法解除電子密度分佈不均勻之情形。其結果，在與 處理空間中之晶圓周緣部相向之部分，電子密度降低，於 蝕刻處理之時，則有晶圓之周緣部中之蝕刻率低於晶圓之 中心部的問題。 本發明之目的係提供可在與處理空間中之基板之周緣 部相向的部份使電子密度充分提高之電極構造及基板處理 裝置。 (用以解決課題之手段） 爲了達成上述目的，申請專利範圍第1項所記載之電 極構造，係屬於被配置在對基板施予電漿處理之基板處理 裝置所具備之處理室內，與在該處理室內被配置在載置台 之上述基板相向的電極構造，其特徵爲：具備與上述基板 之中心部相向之內側電極，和與上述基板之周緣部相向之 外側電極，上述內側電極連接第1直流電源，並且上述外 -6- 201001530 側電極連接第2直流電源，上述外側電極具有與上述基板 平行之第1面，和對該第1面傾斜之第2面。 申請專利範圍第2項所記載之電極構造係在申請專利 範圍第1項所記載之電極構造中，上述第1面及上述第2 面指向上述基板之周緣部。 爲了達成上述目的，申請專利範圍第3項所記載之基 板處理裝置，係屬於對基板施予電漿處理之基板處理裝置 ，其特徵爲··具備收容上述基板之處理室’和被配置在上 述處理室內載置上述基板之載置台，和被配置在上述處理 室內並且與被載置在上述載置台之上述基板相向之電極構 造，上述電極構造具備與上述基板之中心部相向之內側電 極，和與上述基板之周緣部相向之外側電極’上述內側電 極連接第1直流電源，並且上述外側電極連接第2直流電 源，上述外側電極具有與上述基板平行之第1面’和對該 第1面傾斜之第2面。 〔發明效果〕 若藉由申請專利範圍第1項所記載之電極構造及申請 專利範圍第3項所記載之基板處理裝置時’在與基板之周 緣部相向之外側電極連接第2直流電源而被施加直流電壓 。當在外側電極施加直流電壓之時，該外側電極引入電漿 中之陽離子而釋放出二次電子。其結果’可以在與處理空 間中之基板之周緣部相向之部分提高電子密度。再者’連 接第2直流電源之外側電極具有與基板平行之第1面’和 201001530 對該第1面傾斜之第2面’二次電子自第1面及第2面釋 放出。第2面因對第1面傾斜，故在與處理空間中之基板 之周緣部相向之部分，自第2面釋放出之二次電子與自第 1面釋放出之二次電子重疊。其結果，可以在與處理空間 中之基板之周緣部相向之部分充分提高電子密度。 若藉由申請專利範圍第2項所記載之電極構造，第1 面及第2面因指向基板之周緣部，故自第1面釋放出之二 次電子及自第2面釋放出之二次電子在基板之周緣部之正 上方重疊。其結果，可以在基板之周緣部之正上方確實且 充分提高電子密度。 【實施方式】 以下，針對本發明之實施型態，一面參照圖面一面予 以說明。 第1圖爲槪略性表示本實施型態所涉及之基板處理裝 置之構成的剖面圖，第2圖爲槪略性表示第1圖中之上部 電極之外側電極附近之構成之放大剖面圖。該基板處理裝 置係構成對當作基板之半導體晶圓使用電漿施予RIE ( Reactive Ion Etching)處理。 在第1圖及第2圖中，基板處理裝置10係具備有圓 筒形狀之處理室11、被配置在該處理室η內，當作載置 例如直徑爲3 00mm之半導體晶圓（以下’單稱爲「晶圓 」）W之載置台的圓柱狀之承受器12。 在基板處理裝置10中，藉由處理室11之內側壁和承 -8- 201001530 受器1 2之側面，形成將後述之處理空間S之氣體排出處 理室1 1外之流路而發揮功能之排氣流路1 3。在該排氣流 路13之途中，配置排氣板（排氣環）1 4。 排氣板1 4爲具有多數貫通孔之板狀構件，當作將處 理室1 1分隔成上部和下部之分隔板而發揮功能。在藉由 排氣板14而分隔之處理室11之上部（以下稱爲「反應室 」）15如後述般產生電漿。再者，在處理室11之下部（ 以下，稱爲「排氣室（歧管）」）16連接排出處理室11 內之氣體的排氣管1 7、1 8。排氣板1 4捕捉或反射產生於 反應室15之電漿而防止朝歧管16洩漏。 排氣管 17 連接 TMP ( Turbo Molecular Pump)(無圖 不），排氣管18連接DP(DryPump)(無圖示），該些 泵將處理室1 1內予以抽真空而減壓。具體而言，DP係將 處理室1 1內從大氣壓減壓至中真空狀態（例如，1 .3 X l〇Pa ( O.lTorr)以下），TMP與DP合作將處理室1 1內 減壓至低於中真空狀態之壓力的高真空狀態（例如，1 .3 X WdpaCl.OxlO^Torr)以下）。並且，處理室11內之壓 力藉由APC閥（無圖示）被控制。 在處理室11內之承受器12，經第1整合器21及第2 整合器22各連接第1高頻電源19及第2高頻電源20，第 1高頻電源19對承受器12施加比較高之頻率例如60MHz 之高頻亀力，第2高頻電源20對承受器12施加比較低之 頻率例如2MHz之高頻電力。依此，承受器12當作對該 承受器1 2及後述噴淋頭30之間之處理空間S施加高頻電 -9- 201001530 力之下部電極而發揮功能。 再者，在承受器12上設置有在內部具有靜電電極板 23之由圓板狀絕緣性構件所構成之靜電夾具24。當在承 受器1 2載置晶圓W之時，該晶圓W則被配置在靜電夾具 24上。再者，在該靜電夾具24中，於靜電電極板23電性 連接有直流電源25。當對靜電電極板23施加正的直流電 壓時，則在晶圓W中之靜電夾具24側之面（以下，稱爲 「背面」）產生負電位，在靜電電極板23及晶圓W之背 面之間產生電位差，因該電位差引起之庫倫力或強生拉別 克（Johnsen-Rahbek )力，晶圓W被吸附保持於靜電夾具 24 ° 再者，在承受器12上，以包圍被吸附保持之晶圓W 之方式，載置圓環狀之聚焦環26。聚焦環26係由導電性 構件，例如由矽所構成，使電漿朝向晶圓W之表面收束 ，提高RIE處理之效率。 再者，在承受器12之內部設置有例如延伸於圓周方 向之環狀冷媒室27。在該冷媒室27自冷卻單元（無圖示 )經冷媒用配管2 8循環供給低溫之冷媒例如冷卻水或油 脂液（Galden :註冊商標）。藉由該低溫之冷媒而被冷卻 之承受器12，經靜電夾具24冷卻晶圚W及聚焦環26。 在靜電夾具2 4之上面中吸附保持晶圓W之部分（以 下，稱爲「吸附面」），開口多數傳熱氣體供給孔29。該 些多數傳熱氣體供給孔29係經傳熱氣體供給孔29而將當 作傳熱氣體之氦（H e )氣體供給至吸附面及晶圓W之背 -10- 201001530 面之間隙。被供給至吸附面及晶圓w之背面之間隙的氦 氣體係有效果地將晶圓W之熱傳達至靜電夾具24。 在處理室11之天井部設置有噴淋頭30。該噴淋頭30 具有露出於處理空間S而與被載置在承受器12之晶圓W (以下’稱爲「載置晶圓W」）相向之上部電極31 (電 極構造），和由絕緣性構件所構成之絕緣板3 2，和經該絕 緣板32垂釣支撐上部電極31之電極垂釣支撐體33，依照 上部電極31、絕緣板32及電極垂釣支撐體33之順序被重 疊。 電極垂釣支撐體33在內部具有緩衝室39。緩衝室39 爲圓柱狀之空間，藉由圓環狀之密封材，例如Ο型環40 被區分成內側緩衝室3 9a和外側緩衝室3 9b。 在內側緩衝室3 9 a連接有處理氣體導入管4 1，在外側 緩衝室3 9b連接有處理氣體導入管42，處理氣體導入管 4 1、42各對內側緩衝室3 9a及外側緩衝室3 9b導入處理氣 體。 處理氣體導入管41、42因各具有流量控制器（MFC )(無圖示），故被導入至內側緩衝室3 9a及外側緩衝室 39b之處理氣體之流量各獨立性被控制。再者，緩衝室39 經電極垂釣支撐體33之氣體孔43、絕緣板32之氣體孔 44及上部電極31之氣體孔36而與處理空間S連通，被 導入至內側緩衝室39a或外側緩衝室39b之處理氣體被供 給至處理空間S。此時’藉由調整被導入至內側緩衝室 3 9 a及外側緩衝室3 9 b之處理氣體之流量，控制處理空間 -11 - 201001530 S中之處理氣體之分佈。 在該基板處理裝置】0中’於對載置晶圓w施予RIE 處理之時，噴淋頭30將處理氣體供給至處理空間S，第1 高頻電源19經承受器12對處理空間S施加60MHz之局 頻電力，並且第2高頻電源20對承受器12施加2MHz之 高頻電力。此時，處理氣體藉由60MHz之高頻電力而被 激發成爲電漿。再者’ 2MHz之高頻電力在承受器12中產 生偏壓電壓，故電漿中之陽離子或電子被引入至載置晶圓 W表面，該載置晶圓W被施予RIE處理。 再者，爲了在處理空間中部分性控制電子密度分佈， 開發有將上部電極分割成與晶圓之中心部相向之內側電極 ，和與晶圓之周緣部相向之外側電極，對內側電極及外側 電極之各個獨立施加負極性之直流電壓的方法已被開發。 在該方法中，對外側電極施加與內側電極値不同之直流電 壓而獨立控制在處理空間中與外側電極相向之部分之電子 密度，和與內側電極相向之部分之電子密度。 關於該方法，本發明人等發現當透過RIE處理之實驗 使外側電極中朝向處理空間之相向面的表面積（以下，稱 爲「外側電極表面積」）增加時，與處理空間中之外側電 極之相向面相向之部分（以下稱爲「外側電極相向部份」 )之電子密度提高，其結果提高晶圓之周緣部中之蝕刻率 (參照第3圖）。 再者’本發明人等發現當使施加於外側電極之直流電 壓之値增加時’依然提高外側電極相向部分之電子密度， -12- 201001530 其結果提高晶圓之周緣部中之蝕刻率。具體 當施加於內側電極之直流電壓之絕對値維持 態，直接將施加於外側電極之直流電壓之凝 上升至900V之時，晶圓之周緣部中之蝕刻J (參照第4圖）。 但是，在通常之基板處理裝置中，在外 因存在其他處理室構成構件，故難以將外側 加至給定値以上之情形爲多。再者，也難以 性能等之制約提高施加於外側電極之直流電 値以上之情形爲多。即是，通常難以使處理 之周緣部相向之部分充分提高電子密度。 在基板處理裝置10中，對應此上部電卷 置晶圓W之中心部相向之內側電極3 4，和 極34並且與載置晶圓W之周緣部相向之外 側電極3 5具有與載置晶圓W平行之第1二 3 5a (第1面），及對該第1二次電子釋放 置晶圓W傾斜之第2二次電子釋放面35b ( 1二次電子釋放面35a及外側電極35b各指 之周緣部。 在此，內側電極34具有例如由直徑爲 狀構件所構成，貫通於厚度方向之多數氣體 極35係由外徑爲380mm且內徑爲300mm之 構成。內側電極3 4及外側電極3 5係由導電 材料例如單晶矽所構成。 而言，確認出 在300V之狀 I對値從3 00V _提高大約7% 側電極之周邊 電極表面積增 從直流電源之 源之値至給定 空間中與晶圓 i 31具有與載 包圍該內側電 側電極3 5，外 次電子釋放面 面35a朝向載 第2面）。第 向載置晶圓W 3 00mm之圓板 ?L 3 6。外側電 圓環狀構件所 性或半導電性 -13- 201001530 再者，在上部電極31中，於內側電極34連接有第1 直流電源3 7，於外側電極3 5連接有第2直流電源3 8，內 側電極3 4及外側電極3 5各獨立被施加直流電壓。 在基板處理裝置10中，於RIE處理之期間，第1直 流電源3 7及第2直流電源3 8對上部電極3 1之內側電極 3 4及外側電極3 5施加負的直流電壓。此時，於內側電極 34或外側電極35被引入處理空間S之電漿中之陽離子。 被引入之陽離子對內側電極34或外側電極35中之構成原 子中之電子賦予能量，當所賦予之能量超過給定値之時， 構成原子中之電子則當作二次電子自內側電極34之表面 或外側電極35之第1二次電子釋放面35a及第2二次電 子釋放面35b被釋放出。 內側電極3 4如上述般，爲圓板狀構件，因僅與載置 晶圓W平行之表面露出於處理空間S，故自該表面所釋放 出之二次電子從載置晶圓W之中心部到周緣部幾乎均句 分佈。其結果，RIE處理在整個載置晶圓w全面被促進。 外側電極3 5之第1二次電子釋放面3 5 a及第2二次 電子釋放面35b如上述般’因任一者皆指向載置晶圓w 之周緣部，故自第1二次電子釋放面35a及自第2二次電 子釋放面35b所釋放出之二次電子在載置晶圓w之周緣 部之正上方重疊。其結果’可以在載置晶圓W之周緣部 之正上方充分提局電子密度’並在晶圓W之周緣部促進 RIE處理。 並且’上述基板處理裝置10之各構成零件之動作係 -14- 201001530 由基板處理裝置10所具備之控制部（無圖示）之CPU控 制。 若藉由本實施型態所涉及之當作電極構造的上部電極 3 1時，在與載置晶圓W之周緣部相向之外側電極3 5連接 第2直流電源3 8而被施加直流電壓。當在外側電極3 5施 加直流電壓之時，該外側電極35引入電漿中之陽離子而 釋放出二次電子。其結果，可以在與處理空間S中之載置 晶圓W之周緣部之正上方提高電子密度。再者，連接第2 直流電源3 8之外側電極3 5具有與載置晶圓W平行之第1 二次電子釋放面35a，和對該第1二次電子釋放面35a朝 向載置晶圓W傾斜之第2二次電子釋放面35b，二次電子 自第1二次電子釋放面35a及第2二次電子釋放面35b釋 放出。第1二次電子釋放面35a及第2二次電子釋放面 35b因指向載置晶圓 W之周緣部，故可以在載置晶圓W 之周緣部之正上方充分提高電子密度，可以在載置晶圓W 之‘周緣部促進RIE處理。 在上述上部電極31中，因不用增加外側電極3 5中之 朝晶圓W之相向面的面積，可以在載置晶圓W之周緣部 之正上方充分提高電子密度，故不需要增大外側電極35。 其結果，可以刪減高價之單晶矽之使用量，進而可以降低 上部電極31之製造成本。 再者，在上述上部電極31中，不僅第1二次電子釋 放面35a，第2二次電子釋放面35b雖然也指向載置晶圓 W之周緣部，但是第2二次電子釋放面3 5 b即使不指向載 -15- 201001530 置晶圓W之周緣部亦可，例如第2二次電子釋放面35b 即使對第1二次電子釋放面35a垂直亦可。即使於此時， 因在處理空間S中與載置晶圓W之周緣部相向之部分， 重疊所釋放出之二次電子，故可以在與載置晶圓W之周 緣部相向之部分充分提高電子密度。 又’第2二次電子釋放面35b不須要爲平面，即使爲 指向載置晶圓W之周緣部的拋物面亦可。此時，可以將 二次電子從第2二次電子釋放面35b朝向載置晶圓W之 周緣部集中性釋放出，進而可以更充分提高載置晶圓 W 之周緣部之正上方之電子密度。 並且，在上述本實施之型態中，施予鈾刻處理之基板 雖然爲半導體晶圓W，但是並不限定於施予蝕刻處理之基 板，即使爲例如 LCD ( Liquid Crystal Display)或 FPD ( Flat Panel Display)等之玻璃基板亦可。 〔實施例〕 接著，針對本發明之實施例予以說明。 實施例1 首先，本發明人在基板處理裝置10中對載置晶圓W 施予RIE處理，測量該RIE處理中之載置晶圓W之周緣 部之飽刻率’將其結果在第5圖之曲線圖中以「鲁」表不 -16- 201001530 比較例1、2 接著，本發明人準備僅具有與載置晶圓W平行之表 面，且互相該表面面積不同之兩個外側電極，以代替外側 電極3 5。然後，在基板處理裝置1 〇將外側電極3 5與所準 備之各外側電極替換，對載置晶圓W施予RIE處理，測 量該RIE處理中之載置晶圓W之周緣部之蝕刻率，將其 結果在第5圖之曲線圖中以「♦」表示。 第5圖之曲線圖之橫軸表示外側電極之表面積。在此 ，外側電極之表面積相當於實施例1中之第1二次電子釋 放面3 5a及第2二次電子釋放面3 5b之面積之合計値或比 較例1、2中與載置晶圓W平行之表面的面積。再者，在 第5圖之曲線圖中，橫軸表示將比較例1之外側電極之表 面積設爲1之時之實施例1或各比較例之外側電極之表面 積，縱軸爲將比較例1之蝕刻率設爲1之時之實施例1或 各比較例之蝕刻率。藉由第5圖之曲線圖，可知比起增加 外側面積之表面積，藉由設置對第1二次電子釋放面35a 傾斜之第2二次電子釋放面35b則可以有效率充分提高載 置晶圓W之周緣部正上方之電子密度，可以在載置晶圓 W之周緣部促進RIE處理。 【圖式簡單說明】 第1圖爲槪略性表示本發明之實施型態所涉及之基板 處理裝置之構成的剖面圖。 -17- 201001530 第2圖爲槪略表示第1圖中之上部電極之外側電極附 近之構成的放大剖面圖。 第3圖爲表示外側電極中之外側電極表面積和晶圓之 周緣部中之蝕刻率之關係曲線圖。 第4圖爲表示使施加至外側電極之直流電壓之値增加 之時之蝕刻率上升率之曲線圖。 第5圖爲表示本發明之實施例1、以及比較例1、2中 之外側電極表面積和晶圓之周緣部中之蝕刻率之關係曲線 圖。 【主要元件符號說明】 W :晶圓 1 〇 :基板處理裝置 1 1 :處理室 12 :承受器 3 1 :上部電極 3 4 :內側電極 3 5 :外側電極 35a :第1二次電子釋放面 3 5b :第2二次電子釋放面 3 7 :第1直流電源 3 8 :第2直流電源201001530 VI. TECHNOLOGICAL FIELD The present invention relates to an electrode structure and a substrate processing apparatus, and more particularly to an electrode structure in which a DC power source is connected in a processing chamber disposed in a substrate processing apparatus. [Prior Art] The substrate processing apparatus that is subjected to the plasma treatment includes a processing chamber for accommodating the wafer, a mounting table on which the wafer is placed in the processing chamber, and a shower head that supplies the processing gas to the processing space in the processing chamber. In the substrate processing apparatus, a high-frequency power source is connected to the mounting table, and the mounting table applies high-frequency power to the processing space, and the processing gas supplied to the processing space is excited by high-frequency power to become plasma (cation or electron). Since the plasma distribution in the processing space has a great influence on the result of the electric paddle processing of the wafer, it is preferable to actively control the distribution of the electric paddle, and correspondingly, in order to control the plasma distribution, especially the electron density distribution, the application to the shower head is performed. DC voltage. When a DC voltage is applied to the shower head, the constituent members of the shower head are connected to the DC electrode of the disk-shaped patio electrode plate exposed in the processing space. Here, when a negative DC voltage is applied to the showerhead, the showerhead introduces only the cations in the plasma. Since the DC voltage is different from the high-frequency voltage and the potential does not change with time, the cation is continuously introduced into the shower head. Further, the cation introduced into the shower head releases secondary electrons from the constituent atoms of the shower head. As a result, the portion which is opposed to the shower head of the processing space is increased from -5 to 201001530 (see, for example, Patent Document 1). [Problem to be Solved by the Invention] However, the electron density distribution is affected by the shape of the processing chamber, etc., and it is uneven in the processing space. However, when a patio electrode plate is formed by a conductive plate, even if a DC voltage is applied to the patio electrode plate, since only the electron density of all portions in the processing space facing the shower head is increased, the electron density distribution cannot be released. Evenly. As a result, the electron density decreases in a portion facing the peripheral edge portion of the wafer in the processing space, and the etching rate in the peripheral portion of the wafer is lower than the center portion of the wafer during the etching process. SUMMARY OF THE INVENTION An object of the present invention is to provide an electrode structure and a substrate processing apparatus which can sufficiently increase the electron density in a portion facing a peripheral portion of a substrate in a processing space. (Means for Solving the Problem) In order to achieve the above object, the electrode structure described in the first aspect of the patent application belongs to a processing chamber provided in a substrate processing apparatus that applies plasma treatment to a substrate, and An electrode structure in which the substrate is disposed on the mounting table in the processing chamber, and includes an inner electrode facing the central portion of the substrate, and an outer electrode facing the peripheral portion of the substrate, wherein the inner electrode is connected to the first direct current The power source is connected to the second DC power source of the outer-6-201001530 side electrode, and the outer electrode has a first surface parallel to the substrate and a second surface inclined to the first surface. In the electrode structure according to the first aspect of the invention, the first surface and the second surface are directed to a peripheral portion of the substrate. In order to achieve the above object, the substrate processing apparatus according to the third aspect of the invention is a substrate processing apparatus for applying a plasma treatment to a substrate, characterized in that: a processing chamber for accommodating the substrate is disposed and disposed on the substrate a mounting table on which the substrate is placed in the processing chamber, and an electrode structure disposed in the processing chamber and facing the substrate placed on the mounting table, wherein the electrode structure includes an inner electrode facing the central portion of the substrate, and The first electrode is connected to the inner electrode of the outer surface of the substrate, and the inner electrode is connected to the first direct current power source, and the outer electrode is connected to the second direct current power source. The outer electrode has a first surface parallel to the substrate and is inclined to the first surface. The second side. According to the electrode structure described in the first aspect of the invention, and the substrate processing apparatus according to the third aspect of the patent application, the second DC power source is connected to the side electrode opposite to the peripheral portion of the substrate. Apply a DC voltage. When a direct current voltage is applied to the outer electrode, the outer electrode introduces a cation in the plasma to release secondary electrons. As a result, the electron density can be increased in a portion facing the peripheral portion of the substrate in the processing space. Further, the second electrode of the second DC power source has a first surface which is parallel to the substrate, and the second surface of the 201001530 which is inclined to the first surface. Secondary electrons are released from the first surface and the second surface. Since the second surface is inclined with respect to the first surface, the secondary electrons emitted from the second surface overlap with the secondary electrons emitted from the first surface in a portion facing the peripheral edge portion of the substrate in the processing space. As a result, the electron density can be sufficiently increased in a portion facing the peripheral portion of the substrate in the processing space. According to the electrode structure described in the second paragraph of the patent application, the first surface and the second surface are directed to the peripheral portion of the substrate, so that the secondary electrons released from the first surface and the second surface released from the second surface The electrons overlap directly above the peripheral portion of the substrate. As a result, the electron density can be surely and sufficiently increased directly above the peripheral portion of the substrate. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view schematically showing the configuration of a substrate processing apparatus according to the present embodiment, and Fig. 2 is an enlarged cross-sectional view schematically showing the configuration of the vicinity of the outer electrode of the upper electrode in Fig. 1 . The substrate processing apparatus is configured to apply a RIE (Reactive Ion Etching) process to a semiconductor wafer as a substrate. In the first and second figures, the substrate processing apparatus 10 is provided with a cylindrical processing chamber 11 and disposed in the processing chamber η as a semiconductor wafer having a diameter of 300 mm (hereinafter referred to as ' The cylindrical susceptor 12 is simply referred to as a "wafer" W mounting table. In the substrate processing apparatus 10, the inner side wall of the processing chamber 11 and the side surface of the receiver -12-201001530 receiver 1 2 are formed to form a flow path outside the gas discharge processing chamber 1 1 of the processing space S to be described later. Exhaust flow path 13 3. On the way of the exhaust flow path 13, an exhaust plate (exhaust ring) 14 is disposed. The exhaust plate 14 is a plate-like member having a plurality of through holes, and functions as a partition plate that partitions the processing chamber 11 into upper and lower portions. The upper portion of the processing chamber 11 (hereinafter referred to as "reaction chamber") 15 partitioned by the exhaust plate 14 generates plasma as will be described later. Further, the lower portion of the processing chamber 11 (hereinafter referred to as "exhaust chamber (manifold)") 16 is connected to the exhaust pipes 17 and 18 of the gas discharged from the processing chamber 11. The venting plate 14 captures or reflects the plasma generated in the reaction chamber 15 to prevent leakage toward the manifold 16. The exhaust pipe 17 is connected to a TMP (Turbo Molecular Pump) (not shown), and the exhaust pipe 18 is connected to a DP (DryPump) (not shown), and the pumps are evacuated in the treatment chamber 1 1 to be depressurized. Specifically, the DP system decompresses the pressure in the processing chamber 1 1 from the atmospheric pressure to the medium vacuum state (for example, 1.3 × 10 〇 Pa (O.lTorr) or less), and the TMP cooperates with the DP to decompress the inside of the processing chamber 1 1 . A high vacuum state (for example, 1.3 M WdpaCl. OxlO^Torr) below the pressure in the medium vacuum state. Further, the pressure in the processing chamber 11 is controlled by an APC valve (not shown). The first high frequency power supply 19 and the second high frequency power supply 20 are connected to the susceptor 12 in the processing chamber 11 via the first integrator 21 and the second integrator 22, and the first high frequency power supply 19 applies a comparison to the susceptor 12. The high frequency is, for example, a high frequency power of 60 MHz, and the second high frequency power source 20 applies a relatively low frequency, for example, 2 MHz high frequency power to the susceptor 12. Accordingly, the susceptor 12 functions as a lower electrode for applying a high-frequency electric force to the processing space S between the susceptor 1 2 and the shower head 30 to be described later. Further, the susceptor 12 is provided with an electrostatic chuck 24 composed of a disk-shaped insulating member having an electrostatic electrode plate 23 therein. When the wafer W is placed on the receiver 12, the wafer W is placed on the electrostatic chuck 24. Further, in the electrostatic chuck 24, a DC power source 25 is electrically connected to the electrostatic electrode plate 23. When a positive DC voltage is applied to the electrostatic electrode plate 23, a negative potential is generated on the surface of the wafer W on the side of the electrostatic chuck 24 (hereinafter referred to as "back surface"), and is on the back side of the electrostatic electrode plate 23 and the wafer W. A potential difference is generated between the Coulomb force or the Johnsonsen-Rahbek force caused by the potential difference, and the wafer W is adsorbed and held in the electrostatic chuck 24 °. Further, on the susceptor 12, the crystal is surrounded by the adsorption and retention. In the form of a circle W, an annular focus ring 26 is placed. The focus ring 26 is made of a conductive member, for example, made of tantalum, which causes the plasma to converge toward the surface of the wafer W, thereby improving the efficiency of the RIE process. Further, an annular refrigerant chamber 27 extending in the circumferential direction is provided inside the susceptor 12, for example. In the refrigerant chamber 27, a low-temperature refrigerant such as cooling water or grease liquid (Galden: registered trademark) is circulated and supplied from a cooling unit (not shown) via a refrigerant pipe 28. The susceptor 12, which is cooled by the low-temperature refrigerant, cools the wafer W and the focus ring 26 via the electrostatic chuck 24. A portion of the upper surface of the electrostatic chuck 24 is held by the wafer W (hereinafter referred to as "adsorption surface"), and a plurality of heat transfer gas supply holes 29 are opened. The plurality of heat transfer gas supply holes 29 are supplied through the heat transfer gas supply holes 29 to supply the helium (H e ) gas as the heat transfer gas to the gap between the adsorption surface and the back surface of the wafer W - 201001530. The helium gas system supplied to the gap between the adsorption surface and the back surface of the wafer w effectively transfers the heat of the wafer W to the electrostatic chuck 24. A shower head 30 is provided on the patio portion of the processing chamber 11. The shower head 30 has an upper surface electrode 31 (electrode structure) that is exposed to the processing space S and is opposed to the wafer W (hereinafter referred to as "mounting wafer W") placed on the susceptor 12, and is insulated. The insulating plate 3 2 composed of the member and the electrode fishing support 33 for supporting the upper electrode 31 via the insulating plate 32 are superposed in the order of the upper electrode 31, the insulating plate 32, and the electrode fishing support 33. The electrode fishing support 33 has a buffer chamber 39 inside. The buffer chamber 39 has a cylindrical space, and is divided into an inner buffer chamber 39a and an outer buffer chamber 39b by an annular seal member such as a serpentine ring 40. A processing gas introduction pipe 4 is connected to the inner buffer chamber 39a, and a processing gas introduction pipe 42 is connected to the outer buffer chamber 39b. The processing gas introduction pipes 4, 42 are paired with the inner buffer chamber 39a and the outer buffer chamber 3, respectively. 9b introduces a process gas. Since the process gas introduction pipes 41 and 42 each have a flow rate controller (MFC) (not shown), the flow rates of the process gases introduced into the inner buffer chamber 39a and the outer buffer chamber 39b are controlled independently. Further, the buffer chamber 39 is communicated with the processing space S via the gas hole 43 of the electrode fishing support 33, the gas hole 44 of the insulating plate 32, and the gas hole 36 of the upper electrode 31, and is introduced into the inner buffer chamber 39a or the outer buffer chamber. The processing gas of 39b is supplied to the processing space S. At this time, the distribution of the processing gas in the processing space -11 - 201001530 S is controlled by adjusting the flow rate of the processing gas introduced into the inner buffer chamber 319a and the outer buffer chamber 319b. In the substrate processing apparatus ○0, when the RIE process is performed on the mounted wafer w, the shower head 30 supplies the processing gas to the processing space S, and the first high-frequency power source 19 passes through the susceptor 12 to the processing space S. A local frequency power of 60 MHz is applied, and the second high frequency power source 20 applies high frequency power of 2 MHz to the susceptor 12. At this time, the processing gas is excited into a plasma by high frequency power of 60 MHz. Further, since the high frequency power of 2 MHz generates a bias voltage in the susceptor 12, cations or electrons in the plasma are introduced to the surface of the wafer W, and the carrier wafer W is subjected to RIE processing. Further, in order to partially control the electron density distribution in the processing space, an inner electrode that divides the upper electrode into a central portion of the wafer and an outer electrode that faces the peripheral portion of the wafer, the inner electrode and the outer side are developed. A method of independently applying a DC voltage of a negative polarity to each of the electrodes has been developed. In this method, a direct current voltage different from that of the inner electrode 施加 is applied to the outer electrode to independently control the electron density of the portion facing the outer electrode in the processing space and the electron density of the portion facing the inner electrode. In the present inventors, the present inventors have found that when the surface of the outer electrode facing the opposing surface of the processing space (hereinafter referred to as "outer electrode surface area") is increased by an experiment by RIE treatment, it faces the outer electrode in the processing space. The electron density of the surface facing portion (hereinafter referred to as the "outer electrode facing portion") is increased, and as a result, the etching rate in the peripheral portion of the wafer is increased (see Fig. 3). Further, the inventors of the present invention found that when the 直流 of the DC voltage applied to the outer electrode is increased, the electron density of the opposing portion of the outer electrode is still increased, and -12-201001530 results in an increase in the etching rate in the peripheral portion of the wafer. Specifically, when the absolute voltage of the DC voltage applied to the inner electrode is maintained, the condensing of the DC voltage applied to the outer electrode is raised to 900 V, and the etching is performed in the peripheral portion of the wafer (see Fig. 4). However, in a conventional substrate processing apparatus, since other processing chamber constituent members exist in an external direction, it is difficult to add the outer side to a predetermined thickness or more. Further, it is difficult to increase the DC voltage applied to the outer electrode by the performance and the like. That is, it is generally difficult to sufficiently increase the electron density in the portion where the peripheral portion of the treatment is opposed. In the substrate processing apparatus 10, the inner electrode 34 and the electrode 34 facing the center portion of the wafer W are placed opposite to the peripheral portion of the wafer W, and the side electrode 35 has a crystal. The first and second electron emission surfaces 35b (the secondary electron emission surface 35a and the outer electrode 35b) which are inclined to the first secondary electron release wafer W are parallel to the first and third sides of the circle W (the first surface) Here, the inner electrode 34 has a diameter-like member, and the plurality of gas electrodes 35 penetrating the thickness direction have an outer diameter of 380 mm and an inner diameter of 300 mm. The inner electrode 34 and The outer electrode 35 is made of a conductive material such as a single crystal germanium. In this case, it is confirmed that the I of the 300V is increased from 300 V _ by about 7%, and the peripheral electrode surface area of the side electrode is increased from the source of the DC power source to In the given space, the wafer i 31 has a carrier and the inner side electrode 35, and the outer electron emission surface 35a faces the second surface. The wafer W 3 00 mm round plate ?L 3 6 is placed in the first direction. The outer electric ring-shaped member is semi-conductive or semi-conductive. 13-201001530 Further, in the upper electrode 31, the first DC power source 3 is connected to the inner electrode 34, and the second DC power source 3 is connected to the outer electrode 35. 8. The inner electrode 34 and the outer electrode 35 are each independently applied with a direct current voltage. In the substrate processing apparatus 10, during the RIE process, the first DC power source 37 and the second DC power source 38 apply a negative DC voltage to the inside electrode 34 and the outside electrode 35 of the upper electrode 31. At this time, the inner electrode 34 or the outer electrode 35 is introduced into the cation in the plasma of the processing space S. The introduced cation imparts energy to the electrons in the constituent atoms in the inner electrode 34 or the outer electrode 35. When the energy imparted exceeds a given enthalpy, the electrons in the constituent atoms act as secondary electrons from the surface of the inner electrode 34. The first secondary electron emission surface 35a and the second secondary electron emission surface 35b of the outer electrode 35 are released. As described above, the inner electrode 34 is a disk-shaped member, and since only the surface parallel to the wafer W is exposed to the processing space S, the secondary electrons released from the surface are placed from the center of the wafer W. The department is almost evenly distributed to the periphery. As a result, the RIE process is fully promoted throughout the placement of the wafer w. As described above, the first secondary electron emission surface 35 a and the second secondary electron emission surface 35 b of the outer electrode 35 are directed to the peripheral portion of the wafer w, so that the first secondary electron The release surface 35a and the secondary electrons released from the second secondary electron emission surface 35b overlap directly above the peripheral portion of the wafer w. As a result, the electron density can be sufficiently extracted right above the peripheral portion on which the wafer W is placed, and the RIE process can be promoted at the peripheral portion of the wafer W. Further, the operation of each of the components of the substrate processing apparatus 10-14-201001530 is controlled by a CPU of a control unit (not shown) provided in the substrate processing apparatus 10. When the upper electrode 31 is used as the electrode structure according to the present embodiment, the second DC power source 38 is connected to the side electrode 35 opposite to the peripheral portion of the wafer W, and a DC voltage is applied thereto. When a DC voltage is applied to the outer electrode 35, the outer electrode 35 introduces a cation in the plasma to release secondary electrons. As a result, the electron density can be increased directly above the peripheral portion of the wafer W placed in the processing space S. Further, the second DC power source 3 8 is connected to the first secondary electron emitting surface 35a that is parallel to the mounting wafer W, and the first secondary electron emission surface 35a is placed toward the wafer W. The second secondary electron emission surface 35b is inclined, and the secondary electrons are released from the first secondary electron emission surface 35a and the second secondary electron emission surface 35b. Since the first secondary electron emission surface 35a and the second secondary electron emission surface 35b are directed to the peripheral portion of the wafer W, the electron density can be sufficiently increased just above the peripheral edge portion on which the wafer W is placed. The peripheral portion of the wafer W is subjected to RIE processing. In the upper electrode 31, since the area of the opposing surface of the wafer W facing the wafer W is not increased, the electron density can be sufficiently increased directly above the peripheral portion of the wafer W, so that it is not necessary to increase the outer side. Electrode 35. As a result, the amount of use of the high-priced single crystal germanium can be eliminated, and the manufacturing cost of the upper electrode 31 can be reduced. Further, in the upper electrode 31, not only the first secondary electron emission surface 35a but also the second secondary electron emission surface 35b is directed to the peripheral portion of the wafer W, but the second secondary electron emission surface 35 b The second secondary electron emission surface 35b may be perpendicular to the first secondary electron emission surface 35a, for example, even if it is not directed to the peripheral portion of the wafer W of the -15-201001530. Even at this time, since the secondary electrons emitted are overlapped in the portion facing the peripheral portion of the wafer W in the processing space S, the portion facing the peripheral portion of the wafer W can be sufficiently improved. Electronic density. Further, the second secondary electron emission surface 35b does not need to be a flat surface, and may be a paraboloid that faces the peripheral portion of the wafer W. In this case, the secondary electrons can be collectively released from the second secondary electron emission surface 35b toward the peripheral portion of the mounting wafer W, and the electron density directly above the peripheral portion of the wafer W can be more sufficiently increased. . Further, in the above-described embodiment, the substrate to which the uranium engraving treatment is applied is the semiconductor wafer W, but is not limited to the substrate to which the etching treatment is applied, and is, for example, an LCD (Liquid Crystal Display) or an FPD (Flat). Glass substrates such as Panel Display can also be used. [Embodiment] Next, an embodiment of the present invention will be described. First, the inventors of the present invention applied RIE processing to the placed wafer W in the substrate processing apparatus 10, and measured the saturation ratio of the peripheral portion of the mounted wafer W in the RIE processing. In the graph of the graph, "Lu" is not shown as -16-201001530. Comparative Examples 1 and 2 Next, the inventors prepare two outer electrodes having only surfaces parallel to the wafer W and having different surface areas. Instead of the outer electrode 35. Then, the substrate processing apparatus 1 替换 replaces the outer electrode 35 with each of the prepared outer electrodes, and performs RIE processing on the mounted wafer W to measure the etching rate of the peripheral portion of the wafer W to be placed in the RIE process. The result is indicated by "♦" in the graph of Fig. 5. The horizontal axis of the graph of Fig. 5 indicates the surface area of the outer electrode. Here, the surface area of the outer electrode corresponds to the total area of the first secondary electron emission surface 35a and the second secondary electron emission surface 35b in the first embodiment, or the wafers in the comparative examples 1, 2 and The area of the W parallel surface. In the graph of Fig. 5, the horizontal axis represents the surface area of the external electrode of Example 1 or Comparative Example when the surface area of the external electrode of Comparative Example 1 is set to 1, and the vertical axis is Comparative Example 1. The etching rate of Example 1 or each comparative example when the etching rate was set to 1. According to the graph of Fig. 5, it can be seen that the second secondary electron emission surface 35b inclined to the first secondary electron emission surface 35a can be efficiently increased in comparison with the surface area for increasing the outer area. The electron density directly above the peripheral portion of W can facilitate the RIE process on the peripheral portion of the wafer W. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view schematically showing the configuration of a substrate processing apparatus according to an embodiment of the present invention. -17- 201001530 Fig. 2 is an enlarged cross-sectional view showing the configuration of the electrode on the outer side of the upper electrode in Fig. 1 . Fig. 3 is a graph showing the relationship between the surface area of the outer side electrode and the etching rate in the peripheral portion of the wafer in the outer electrode. Fig. 4 is a graph showing the rate of increase in the etching rate when the enthalpy of the DC voltage applied to the outer electrode is increased. Fig. 5 is a graph showing the relationship between the outer electrode surface area and the etching rate in the peripheral portion of the wafer in Example 1 and Comparative Examples 1 and 2 of the present invention. [Description of main component symbols] W: Wafer 1 〇: substrate processing apparatus 1 1 : processing chamber 12 : susceptor 3 1 : upper electrode 3 4 : inner electrode 3 5 : outer electrode 35a : first secondary electron emission surface 3 5b: 2nd secondary electron release surface 3 7 : 1st DC power supply 3 8 : 2nd DC power supply