TWI355019B - Hydrogen ashing enhanced with water vapor and dilu - Google Patents

Hydrogen ashing enhanced with water vapor and dilu Download PDF

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TWI355019B
TWI355019B TW097114268A TW97114268A TWI355019B TW I355019 B TWI355019 B TW I355019B TW 097114268 A TW097114268 A TW 097114268A TW 97114268 A TW97114268 A TW 97114268A TW I355019 B TWI355019 B TW I355019B
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gas
ashing
plasma
hydrogen
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TW200908074A (en
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Chan-Syun Yang
Changhun Lee
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Applied Materials Inc
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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Description

九、發明說明—:---------------—--------… 【發明所屬之技術領域】 具 本發明一般涉及積體電路製造中材料的電聚餘刻 趙地,本發明涉及光阻的灰化。 【先前技術】 在矽積體電路製造中廣泛使用電漿蝕刻技術。其中__ 個製程步驟通常被稱爲介電質餘刻’該步驟被用於形成穿過 介電層的孔,從而在積體電路的不同層之間提供垂直電連 接°在第1圖的橫截面圖中示意性地示出了一種原型穿孔 (V1a)結構。形成在晶片表面上的下介電層1〇在下介電層 10的表面内具有導電構件(feature) 12。上介電層Μ沈積 在下介電層10和下介電層10的導電構件12的上方。平面 光阻層16被旋塗在未圖案化的上介電層14上利用步進式 光刻機按照輻射圖案對平面光阻層丨6進行曝光以形成^ 過光阻層16的遮罩孔18,因而在導電構件】2上方形成具有 遮罩孔18的光刻遮罩,以透過穿孔產生電連接。在上介電 層Μ和光阻層16之間可形成額外的層,例如钱刻硬遮罩或 者抗反射塗層。將被光遮罩的晶片放進電漿蝕刻反庫器中, ==上,電層14被…刻到導電構件;而形成 '、㈣了以使用相同的蝕刻反應器,利用對不同 的層使用不同的蝕刻化學試 來钱亥J抗反射塗層和硬遮罩 C如果有的話)。介雷曾為 1電質餘刻通常利用碳氟化合物’例如使 用八氟丁二烯(C4F6 )。 介電質钱-刻之後,利用諸如铭.戋錮6*1 A S rt! ^ 2〇 , ίΜ _ 及鋼的金屬來-填充穿 從而提供與導電構件12的垂直 用鋼金屬化Μ被^連接。對於通常使 “,:的雙鎮我結構來說,在上介電層Η (該上介電層 位在頂部的水平延伸溝 來代替穿孔20 “ 利用更短的穿孔 下介電居 時用銅填充。對於接觸層的金屬化, 戍,但?:被活性發層代替,並且導電構件12也切構 物,在,丄Μ Μ的介面處可能有複合矽化物和柵極氧化 ^ ^種情況下穿孔2〇被稱爲接觸孔。 在元成介電質蝕刻後’一些光阻可能殘留在介電層Η 20: 钮刻殘餘物(通常是碳質材料)可能殘留在穿孔 。殘餘物可能在穿孔20的側面上形成聚合物塗層”, 助於產生垂直㈣刻輪廓’或者殘餘物形成被隔離的钱 殘餘物24(包括在穿孔2〇底部的—些)。類似的聚合物 層可覆蓋光阻的剩餘部分,産生硬化外表面。金屬填充製 求穿孔20包覆上一層保形的襯裏(包括阻擋層),並 ^在利用電化學鍍覆(ECP)製程進行鋼金屬化時,銅層可 以作爲晶種層和電鍍電極。目前,阻擋層通常是TaN/Ta雙 層’並且阻擋層和銅晶種層可以利用先進濺射法來進行沈 積。重要的是在沈積穿孔的襯襄層之前將光阻和其他殘餘物 從結構中除去,因爲光阻和其他殘餘物會分解附著在穿孔側 壁上並且增加穿孔底部的接觸電阻,這兩種情況都會影響裝 置的良率和可靠性。 電漿灰化(plasma ashing )早已被用於在蝕刻之後除去 光阻和其他殘餘物。氧電漿對於蝕刻除去碳基材料層非常有 1355019 效。雖然以前是在—設計用於 士力〇 — 批—人處理大-量-晶-片的筒狀-灰-化器- 中進行灰化,但更新的技術 ^ ^ ^ 疋私用單晶片電漿灰化器,上述 兩個灰化器可以是單獨的 刻反應器或者是在用於介電質 姓刻的同樣的電漿蝕刻反應 應盗中進行的單獨處理步驟。 當介電層是由二氧化石+ 匕夕(具有Si〇2的近似化學組成和 約3.9的介電常數)所形成時,傳統的灰化製程是有效的。然 J積體電路所需的更低介電常數介電質時灰 化製程會遇到很多困難。單以,
早期的低介電常數介電質是利用以 氣換雜-礼化梦使介電當叙At :>·» 吊數降低到約3 · 5來形成的。更低的 介電常數(低& 3)可以利用氫化的氧碳化矽(silicon ο—)材料來得到,例如位於加州聖大克勞拉市的 APPHed MaUrials 公司所販售 & Black Diamond 介電質。更 低的’I電*數(低於3)可以利用沈積這些材料並使其多孔化 來知到。這些材料的氧灰化弓丨起了很多問題。氧電漿不僅攻 擊碳質光阻的殘餘物和其他殘餘物,氧電漿也會消耗氧碳化 矽中的碳,因此增加氧碳化矽的介電常數。多孔介電材料相
對易碎’並且更容易被氧電漿破壞’原因是部分氧穿透進入 孔中以及孔的崩塌。 因此’先進灰化製程已經從氧電漿的氧化化學試劑轉 移到電漿的還原化學試劑,該電漿的還原化學試劑是由氫和 可能的氮的一些組合(例如,H2、H2/N2或NH3 )所形成。 與氧灰化相比’基於氫自由基H•的灰化具有更好的性能和更 少的介電質破壞。但是,由於還原反應速率低並且在僅有還 原氣體的環境中産生的氫自由基密度低,因此氫灰化是非常 7 1.355019 慢的製程。當氧灰化製程需要2〇 心采進仃處理時,氫灰化 可能需要10倍的時間,從經濟角 角度考慮這明顯是個缺點。 因此,通常將^'買的氧加到還K备撕丄 J逛原钆體中以提高灰化速率和灰 化效率。然而,多孔低介電常數耔 ^ ^ 致材枓對即使少4㈤氧也是敏 感的,這些氧會從氧碳化矽材料昤 竹除去大量的碳並使孔結構崩 塌,因而增大介電常數。 【發明内容】 進行無氧電漿灰化製程,其中 — 、中主要的灰化步驟包括從 氫氣、可選的氮氣、水蒸氣、和非 非'舌性氣體或稀釋氣體(例 如氬或氦)形成的電漿。可以用氨氣 乱礼代替風和氮。形成電漿 的水蒸氣多於氫氡,並且非活性氣體多於水蒸氣。 該灰化製程特別適用於含碳和氧化石夕的低介電常 料,例如氫化的氧碳化石夕。 可選地,可以在主要灰彳卜半聰 安厌化步驟的電漿中加入碳氫化人 物氣體’例如曱烷。碳氫化合物的引入特別適用於多孔低介 電常數材料,例如介電常數小於3的材料。 初始的無氧電漿灰化步驟或表面處理步驟包括從含氣 還原氣體(例如氫氣或氨氣)和可選的氮氣(但沒有水蒸氣 形成的電漿。表面處理步驟可以比主要灰化步驟用時短'。、^ 【實施方式】 在基於氬的灰化電漿中加入水蒸氣和大量氬氣或氦 氣,可大幅增加氫自由基的濃度,並增加灰化速率而 低對 8 Γ355019 低介電常數介電質的損壞。 本發明可以在電漿灰化反應器30中進行,如第2圖的 橫截面圖所示。用真空泵浦***36將真空處理室32抽至低 壓力範圍。室32内的基座38支撐著待灰化的晶片4〇,與氣 體喷頭42相對,氣體喷頭42通過大量小孔44供應處理氣 體。 處理氣體通過遠端電漿源48被供應到喷頭42後面的 歧管46’遠端電漿源48激發處理氣體而形成電漿。遠端電 聚源48可以位於遠離真空室32的一定距離處,但該遠端電 漿源48仍被認爲附屬於真空室32,因爲含有在遠端電漿源 48産生的電漿的氣體會在其活性電漿狀態下流入真空室32 中。較佳地,大多數的自由基和相對很少的電漿離子被送到 處理室32中。遠端電漿源和歧管的—些細節公開在Fu等於 2〇〇6年2月10曰遞交的美國專利申請號第u/35i 676號 中 現在該申清已公開爲美國專利申請公開案第 2007/0190266號。遠端電聚源48可以使用在低gHz範圍(例 如2.54GHz)操作的微波激發源或者在亞GHz範圍(例如27〇 至650 kHz)操作的RF激發源。遠端電漿源48有利地具有 帶電粒子過遽器’使得送到處理室的電衆僅包含中性自由 基’而沒有帶電離子。如果氫氣(h2)被用作主要的灰化氣 體’則從氮氣源50通過質量流量控制器52向遠端電漿源48 供應氫氣。氮氣(N2)可以從氮氣源54通過另一個質量流 量控制器56來供應。氮往往用作氫自由基蝕刻的鈍化劑。 從含有液體水池62的真空密封的水安瓿⑽向遠端電 9 Γ355019 漿源48供應水蒸汽(H2〇 )。質量流量控制器64從安瓿6〇 計量所供應水蒸汽》室溫下,水的蒸汽壓約爲20 Torr,這遠 高於通常操作遠端電漿源48的真空水平。因此,一旦安瓶 60被反向抽吸,具有約20 T0rr壓力的水蒸汽就會出現在頂 部空間66中,該頂部空間66位於安瓿6〇的液體水池62上 方中。安瓶60可以直接安裝在室32上以最小化管道長度, 水會在管道壁上凝結。
根據存储在控制器70的可讀媒介72 (例如CDR〇M) 上的指令集來操作控制器70,從而控制泵浦系統%、遠端 電漿源48和各個質量流量控制器,包括已經提到的質量流 量控制器52、56、64以及其他質量流量控制器。 根據本發明,另外的非活性氣體(如Ar)從氬氣源8〇 經質量流量控制器82計量供應。可以用氦代替氬。氬可促 進仏〇解離成η*和〇H*,這被認爲是潘寧碰撞
Process),在潘寧碰撞中激發態氬自由基的能量被轉移給水 分子。因^與單獨@ Η“目tb ’可由水蒸汽産生更高密度
的氫自由基H*。因此’儘管氬氣和氦氣通常被認爲是非活性 的稀釋氣體,但柄以氮氣和氛氣在實際灰化過程中保持 非活性,但可促進高密度的活性灰化自由基的生成。然而, 在配方中有利地包括Ha可以抑制氧自由基〇·的産生。此外, ^有利地加入N2’不僅增強ha的解離,還在灰化過程中 提供了 一定的鈍化效果。 氫化的氧碳化矽的灰化製程的一個實施例在表丨中示 出。表1中示出的是一個兩步驟製程,其中處理氣體流量的 10 1355019 單位是標準立方釐米(seem)。 Γ355019 表1 步驟 步驟2 Η2 (seem) 600 6〇〇 100 1000 ----- 3〇〇〇 1 N2 (seem) H2O (seem)
Ar (seem) 壓 力 (Torr) RPS 功率(W)_ 時間(s) 5000 5000 20 60 第一個步驟是中度的軟蝕刻或者表面處理,該第一個 步驟並不會使光阻或聚合物側壁塗層表面變硬。第一個步驟 主要基於氫還原化學物質’因此較慢。然而,該第_個步驟 只是用於蝕刻掉表面。可以用其他還原氣體(如單獨的% 或氨氣NH3)來代替心爪2。第二個步驟用於迅速除去光阻 的主體部分和殘餘⑯。第二個步驟是主#的灰化步驟並且 比初始的表面處理步驟用時長。 應該理解本發明概括的配方僅是本發明製程的代表性 例子。壓力範圍可以容易地擴展到〇·5至5 T〇rr,Rps源功 12 1355019 率範圍對於300 mm的室來說,可介於2让冒至8 kw之間, 氣流量爲200至2000 Sccm,氬氣流量爲3〇〇〇至ι〇 〇〇〇 seem,水蒸汽流量爲5〇0至3000 sccm。如前所述可以用 氦代替氬。通常,在第一步驟中,主要供給氫,但也可以供 給少量的氮。在第二步驟中供給的氬比水多,供給的氫比水 蒸汽少。在這兩個步驟中都不供給氡氣或自由基形式的臭 氧。 '
也可以在不進行第一步驟的初步表面處理或進行其他 初步處理的情況下,實施第二步驟的主要灰化製程。
表1的配方對於氫化的氧碳化矽的非多孔低介電常數 介電質是有效的。然而,對於目前較傾向使用的同樣組成的 多孔低介電常數介電質來說,額外的鈍化是需要的。因此, 可以從碳氫化合物氣體源84通過另一個質量流量控制器% 供應碳氫化合物,例如甲烷(CH4 ),但也可以替換成其他 由碳和氫組成的碳氫化合物,例如乙烷(C2H6 )、乙烯(c2H4 ) 和乙炔((:2出),以及其他高級烷烴、烯烴、炔烴等。表2 中示出了一種用於多孔低介電常數介電質的優選配方。 13 Γ355019 表2 步驟1 步驟2 Η2 (seem) 600 600 N2 (seem) 100 H2O (seem) 1000 Ar (seem) 3000 CH4 (seem) 20 壓 力 (Torr) 1 1 RPS 功率 (W) 5000 5000 時間(s) 20 60
步驟 化合 暴露 分) 本發 電漿 生電 表2的配方與表1的配方基本一致,只是在第二 中引入了用量遠少於其他組分的曱烷。這些少量的碳氫 物被認爲可以透過密封介電質材料的孔來鈍化和保護 的低介電常數介電質,從而防止蝕刻電漿(尤其是氧成 穿透進入孔内的深處並降解介電質材料。 本發明並不限於使用遠端電漿源的電漿灰化器, 明也可以在二極體電漿蝕刻反應器中實現,在該二極體 蝕刻反應器中,在靠近晶片或其他基板的真空室内産 14 1355019 漿’但是電槳的離子濃度需要被最小化。此夕卜,本發明也不 限於上面描述的氫化的氧碳化矽低介電常數介電質也可以 用於其他類型料電質材肖’並可以在金屬㈣或耗刻= 程之後將該介電質材料進行灰化。 因此,本發明提供了特別適用於低介電常數介電質材 料的快速且具有保護性的灰化製程。 【圜式簡單說明】 第1圖是介電質钮刻後的穿孔的橫截面圖包括殘餘 光陴、側壁聚合物塗層、和其他需要被灰化製程除去的蝕刻 殘餘物。 第2圖是可用於本發明的電漿灰化器的橫截面示意圖。 【主要元件符號說明】 10 下介電層 12 導電構件
14 上介電層 16 光阻層 18 遮罩孔 20 穿扎 22 多聚物塗層 24 被隔離的蝕刻殘餘物 30電漿灰化反應器 15 Γ355019 真空處理室 真空泵浦系統 底座 晶片 氣體噴頭 小礼 歧管 遠端電漿源 氫氣源 質量流量控制器 氮氣源 質量流量控制器 水安瓿 池 質量流量控制器 頂部空間 控制器 可讀媒介 氬氣源 質量流量控制器 氫氣源 質量流量控制器 16

Claims (1)

1355019 十、申請專利範園: ι· 一種灰化製程’包括—主要灰化步驟,該主要灰化 步驟係將一主要灰化氣韹的一電漿施加至一基板上,該主要 灰化氣逋包括:一第一量的一還原氣體,選自由氫氣和氨氣 所組成的群組;大於該第〆量之一第二量的水蒸氣;以及大 於該第二量之一第三量的稀釋氣體,選自由氩氣和氦氣所 組成的群組;且不含一有妹量的氧氣。
2. 如請求項1所述的製程,其中該還原氣體包括氫氣。 3. 如請求項1所述的製程’其中該還原氣體包括氨氣。 4. 如請求項2所述的製程’其辛該主要灰化氣體額外 含有一第四量的碳氫化合物氣體》 5·如請求項4所述的製程,其中該第四量小於該第一
量。 6·如請求項4所述的製程,其中該碳氫化合物氣體包 括曱烷。 7·如請求項丨所述的製程,其中該基板包括一介電 層’該介電層中具有一經灰化製程處理過的孔。 17 8·如請求項7所述的製程,更包栝按照 d該介電層中的該孔的一先前步騍。 9·如睛求項8中任一項所述的製程 要灰化步騎之前進行的一初始灰化步驟,該 將初始灰化氣體的一電漿施加至該基板,該 第四量的含氫還原氣體且不含有效量 碳氳化合物》 10.如請求項9所述的製程,其中該含 括乳氣。 u·如請求項9所述的製程,其中該初 包括小於該第四量的一第五量的氮氣。 12·如請求項9所述的製程,其中該基 層,該介電層中具有一經灰化製程處理過的孔 13. 如請求項I〗所述的製程,更包括按 蝕刻該介電層中的該孔的一先前步驟。 14. 一種對一基板進行灰化的製程,該 層,該介電層中具有事先蝕刻的__孔,該製程 姓刻室中進行的步驟,該電漿蝕刻室中放置有 一光阻遮罩钱 ’更包括在該 初始灰化步驟 初始灰化氣體 的水蒸氣或一 氫還原氣體包 始灰化氣體更 板包括一介電 〇 照一光阻遮罩 基板具有介電 包括在一電漿 該基板和附屬 18 Γ355019 裝置,該步驟包含: 一第一步驟,將一第一氣體混合物激發成一第一電 漿,該第一氣體混合物包括一第一量的氫氣,且不含有有效 量的氧氣和水蒸氣;
後續進行的一第二步驟,將一第二氣體混合物激發成 一第二電漿,該第二氣體混合物包括:一第二量的氫氣;一 第三量的水蒸氣;以及一第四量的非活性氣體,該非活性氣 體選自由氬氣和氦氣所組成的群組;且不含有有效量的氧 氣。 15.如請求項14所述的製程,其中該第二步驟進行的 時間比該第一步驟長。 16.如請求項14所述的製程,其中該附屬裝置包括一 遠端電漿源,在該遠端電漿源中,該第一和第二電漿被激發 並流入該室中。
17.如請求項14所述的製程,其中該第一氣體混合物 還含有氮氣。 18.如請求項14至17中任一項所述的製程,其中該 第二氣體混合物還含有一第五量的碳氫化合物氣體。 19.如請求項18所述的製程,其中該碳氫化合物氣體 19 Γ355019
包括曱烷。 20.如請求項14至17中任一項所述的製程,其中該 第三量大於該第二量且小於該第四量。 20 1355019 七、指定代表圖: (一)、本案指定代表圖為:第(2)圖。 (二)、本代表圖之元件代表符號簡單說明: 30 電漿灰化反應器 32 真空處理室 36 真空泵浦系統 38 底座 40 晶片 42 氣體喷頭 44 小孔 46 歧管 48 遠端電漿源 50 氫氣源 52 質量流量控制器 54 氮氣源 56 質量流量控制器 60 水安瓿 62 池 64 質量流量控制器 66 頂部空間 70 控制器 72 可讀介質 80 氬氣源 82 質量流量控制器 84 氫氣源 86 質量流量控制器
八、本案若有化學式時,請揭示最能顯示 發明特徵的化學式:
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US7807579B2 (en) 2010-10-05
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