TWI336938B - Multi-layer electrode structure - Google Patents
Multi-layer electrode structure Download PDFInfo
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- TWI336938B TWI336938B TW096101660A TW96101660A TWI336938B TW I336938 B TWI336938 B TW I336938B TW 096101660 A TW096101660 A TW 096101660A TW 96101660 A TW96101660 A TW 96101660A TW I336938 B TWI336938 B TW I336938B
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- electrode
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- memory
- sidewall
- conductor
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Description
11336938 九、發明說明: 【聯合研究合約之當事人】 紐約國際商業機器公司(International Business Machines Corporation)、台灣旺宏國際股份有限公司及德國 英飛凌技術公司(Infineon Technologies A.G_)係為聯合研究 合約之當事人。 【發明所屬之技術領域】 _ 本發明一般係有關於積體電路設計,並尤其有關於記 憶裝置的設計與製造。 【先前技術】 隨者非揮發性έ己憶體的體積越來越小、可靠的儲存容 量越來越大’其應用也越來越廣泛。大體積的外部資料儲 存裝置逐漸被特殊應用的儲存裝置所取代,進而產生 「memory sticks」等微小的記憶卡,可儲存數十億位元的 籲資料。 在此儲存容量之下’功率消耗變得很重要。當具有數 十億個元件時’每一記憶儲存單元的功率消耗必須非常 低。對於此等裝置的功能與容量而言,將功率消耗降到最 低是非常重要的目標。 在本領域中的重要技術之一,係為各種形式的電阻隨 機存取記憶體(RRAM ) ’如下所詳述。美國專利申請案號 第 11Π55,067 號,標題為 “Thin Film Fuse Phase Changl
Ram And Manufacturing Method”,申請人與本案相同,此 5 1336938 案係詳述了上述的技術,並列為本案的參考。 如該案所詳述,利用了此種技術的記憶元件的操作, 係在元件内部快速而有效地加㉟。多種方法被提出來改善 此現象’其中包括了在記憶元件之中防止熱量流失的方法。 獲得最佳化的功率消耗」在此研究領域中,並未成 為關鍵的議題。目前的記憶元件係著重於習知手段中,將 電流柄合至記憶元件本身。此領域對於在記憶元件中如何 協助產生熱量並無著墨。
【發明内容】 ㈣之一面向,係為—種電極結構,其包括有兩個 ^的電w路徑。複數個大致為平㈣的電極係以堆疊方 式=,最外層提供了電氣接點,並定義穿越此堆疊 路徑。二側壁導體層係形成而鄰接至電極層堆疊的 一鈿點,二側壁導體層定義了第二電流路徑。側 的端點係與電極層導雷接鞔办认门_ ^ θ 導電接_:白:' 同一平面,使得電極結構 =電接絲各自1_壁層端點與—電極導電接點所形
【實施方式】 詳述—種電極結構,其提供較佳的熱性能,以 ,低悉_技藝者可實施本發明。在圖式 藝者將可以理解;= 示電極結構的基本實施例10。如圖所 '、大致為平板型,並且接點區域係適合與電路 Ϊ336938 元件形成電接觸。此電極包括二層,— 二可=解的是,在此所用的「底」與「頂: 钴不,而非用以指稱任何功能上的重 图i糸僅便於 裝置可以側面方式形成(亦即從圖示方向旋圖令戶^=的 下翻轉(旋轉180度),而不改變其功能。轉90度)或上 研究發現,以多層形成一電極可減少右驻 =量。無論各層係由不同材料或相同材所: 構成的單層相較之下:有口 ===但為單一材料所 也給予設計者Π心: 導熱此外,此現象 特定特徵條件“構。在此下可提供 熱性3面’而顯示了高電阻與低導 鈦等,而非# ^ A、、^有良好障礙特性的材料如氮化 料,例如欽^為活性因而較容易與鄰近材料鍵結的材 積,可以利用化學氣相沈積(㈤)而沈 該領理r沈積(pvd)而沈積,如 米之間,更佳係為=太1的厚度係介於g.3至2〇奈 薄膜可製造财效的^研究發現,在本實施例中, 與電ί 果λ一種電極結構,其可提供特定的電流 徵的重要性係技術裝置-般快速地導熱。此特 數目可ιϊ需’Λ括了二層不同材料。事實上,層的 熱性、多芦、,少㈣。设計者可根據如所需要的總電阻與導 …積版程的成本或時間、以及其他該領域中所 7 1336938 考量者等因素,而選擇所需要的層數。在此以下,係以二 層來表示多層裝置,但讀者可以瞭解的是,此結構係表示 任何數目的層數均可使用。 對於電極結構20之電性與熱性質的額外控制,係藉由 外加側壁導體26所達成,如第lb圖所示。在此,頂與底 層22,24係對應至第la圖所標示者,且側壁導體係位於此 二層的兩側。在本實施例中,側壁導體的材料係為鈦。側 壁導體的位置係使得其端點與導電元件位於同平面,使得 每一側壁導體提供了從一電極延伸至另一電極的電流路 φ徑,其間沒有材料或元件變化。較佳地,側壁的厚度係介 於0.3至20奈米之間,最佳為5奈米。 需要注意的是,此設計可包括側壁導體,也可不包括, 視應用需求而定。在以下的討論中,大致均包括側壁導體’ 但熟悉該項技藝者可以理解,此元件並非本發明的必要元 件。 另一實施例是在此結構加上導體材料層。如第lc圖所 示,一電極30不只包括頂與底電極元件32,34以及側壁導 體36,更包括導體層37,38。這些層係由與金屬化層相關 籲的材料所構成。舉例而言,可使用銅金屬化。其他類型的 金屬化如鋁、氮化鈦、含鎢材料等,亦可用於此。同時, 非金屬導電材料如摻雜多晶矽等,亦可用於此。在此實施 例中的電極材料較佳係為氮化鈦或氮化鈕。或者,電極可 為氮化鋁鈦或氮化鋁鈕,或可包括一種以上選自下列群組 的元素:鈦、嫣、钥、I呂、钮、銅、始、銀、鑭、錄、釕、 及其合金。如上所述,材料穩定性是重要的設計條件。因 此,大部分實施例係使用了组/氮化组/氮化銥/石夕氣化鈕。 在一實施例中,此特徵係藉由對材料進行高度摻雜而更加 1336938 明顯。 側壁導體的穩定效果,可參照至第lc與ld圖。第ic 圖中央的堆疊層元件(第lc圖中的層32,34,37與Μ)係 、串聯方式排列’使得母一元件直接加總到總電阻,因此 RL = R32 + R34 + R37 + R38 (方程式 〇 其中RL係為電極中央部分的電阻,而各分量則是每 -層的電阻、然而,側壁導體係與各層元件並聯,產生第 Id圖所示的等效電路,其中各層元件產生電阻虹,而側 鲁壁導體產生電阻RS。在此所排列的係為一並 阻計算係為 ~ (rl)(rS)/(rl+rs)(s.s2) 一第lc圖實施例的應用之一,係如第2a圖的記憶胞2〇〇 所不,其大致包括-頂電極210、一底電極22〇、以及位於 此二電極之間並與此二電極接觸的記憶元件23〇。此電極 係以相同方式形成,因此僅標示頂電極21〇。如前所述, 電極的70件包括頂與底電極元件202,204、二導體層 φ 207,208、以及側壁導體2〇6。 曰 在電極之間係為一記憶元件,由一電阻隨機存取記憶 (RRAM)材料所構成。多種材料已被證明在製造rram 時相當有用,如下所述。 一種重要的RRAM材料係為硫屬化物。硫屬化物包括 下列四7L素之任一者:氧(〇)、硫(s)、硒以及 碲(Te) ’形成几素週期表上第VI族的部分。硫屬化物包 ,將-硫屬元素與一更為正電性之元素或自由基結合而 得。硫屬化合物合金包括將硫屬化合物與其他物質如過渡 9 1336938 欄:屬:合物合金通常包括-個以上選自元 當,访厘/攔的70素’例如鍺(Ge)以及錫(Sn)。通 録(s^、β合,物合金包括下列元素中一個以上的複合物: : 錄(Ga )、銦(In )、以及銀(Ag )。由於石*屬化 =由態相而達成其雙記憶丄每= -特徵電阻值,這些材料係稱為「相變化」材料或 株Φ許:以相變化為基礎之記憶材料已經被描述於技術文 ▲成处〇括下列合金:錄/録、銦/錄、銦/石西、錄/蹄、錄/ 鲁I!心f /蹄、銦/錄/碎、鎵/砸/碲、錫/録/碲、銦/録/錯、 ,/銦/録/碲、錯/錫/録/碲、鍺/錄/石西/蹄、以及蹄/錯/録/硫。 ^錯/録/碲合金家族中’可以嘗試大範_合金成分。此成 刀可以下列特徵式表示:TeaGebSb__㈣),纟中&與b代表 了所組成元素的原子總數為1〇〇%時,各原子的百分比。一 位研究員描述了最有用的合金係為,在沈積材料中所包含 之平均碲濃度係遠低於70%,典型地係低於6〇%,並在一 般型態合金中的碲含量範圍從最低23%至最高58%,且最 佳係介於48%至58%之碲含量。鍺的濃度係高於約5%,且 籲其在材料中的平均範圍係從最低8〇/〇至最高3〇%,一般係低 於50%。最佳地,鍺的濃度範圍係介於8%至4〇%。在此成 分中所剩下的主要成分則為銻。(〇vshinky ‘丨12專利,攔 10〜Π)由另一研究者所評估的特殊合金包括Ge2Sb2Te5、 GeSb2Te4、以及 GeSb4Te7。( Noboru Yamada,’’Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording”,•S/VEvJ/OApp. 28-37(1997))更一般地,過渡 金屬如鉻(Cr)、鐵(Fe)、鎳(Ni)、鈮(Nb)、鈀(Pd)、鉑(Pt)、 以及上述之混合物或合金,可與鍺/銻/碲結合以形成一相變 1336938 化合金其包括有可程式化的電阻性質。可使用的記憶材料 的特殊範例,係如Ovshinsky ‘112專利中攔η·!3所述, 其範例在此係列入參考。 相變化合金能在此細胞主動通道區域内依其位置順序 於材料為一般非晶狀態之第一結構狀態與為一般結晶固體 狀之第· 一結構狀態之間切換。這此材料至少為靜籍定 態。此詞囊「非晶」係用以指稱一相對 =序= 其較之一單晶更無次序性,而帶有可偵測之特徵如較之结 晶態更高之電阻值。此詞彙「結晶態」係用以指稱一相對 較有次序之結構,其較之非晶態更有次序,因此包括有可 偵測的特徵例如比非晶態更低的電阻值。典型地,相變化 材料可電切換至完全結晶態與完全非晶態之間所有可偵測 的不同狀態。其他受到非晶態與結晶態之改變而影響之材 料特中包括,原子次序、自由電子密度、以及活化能。此 材料可切換成為不同的固態、或可切換成為由兩種以上固 態所形成之混合物,提供從非晶態至結晶態之間的灰階部 分。此材料中的電性質亦可能隨之改變。 疒砝曰i較大幅度脈衝中的能量夠大,因此足以破 ::曰曰曰構的鍵結’同時夠短因此可以防止原子再次排列 °在沒有不適當實驗的情形下,可以利用實驗方 特定相變化合金的適當脈衝量變曲 瞭解的V,中甘相變化材料係以gst指稱,而可以 '、、疋亦可使用其他類型的相變化材料…種可用於 態 相變化合金可藉由施加一電脈衝而從一種相態切換至 另-相態。先前觀察指出,一較短、較大幅度的脈衝傾向 於將相變化材料的相態改變成大體為非晶態。一較長 m脈衝傾向於將相變化材料的相態改變成 宵£ ο T7 Λ-n 4· a. % · ^ . 1336938 PCRAM的材料係為Ge2Sb2Te5 〇 其他可程式化電阻記憶材料亦可用於本發明的其他實 施例中。此種材料之一係為一超巨磁阻(CMR)材料,其 在一磁場中會大幅改變電阻未加。此種材料一般係為含猛 之鈣鈦礦氧化物,且電阻值的改變一般係在數量級的幅度 内。較佳的RRAM化學式係為PrxCayMn03,其中x:y = 0.5:0.5,或其他成分為X: 0〜1; y: 0~1。包括有锰氧化物之 超巨磁阻材料亦可被使用。 另一 RRAM材料係為一雙元素化合物,例如NixOy、 • TixOy、AlxOy、Wx0y、ZnxOy、ZrxOy、CuxOy 等,其中 x:y= 0.5:0.5,或其他成分為x: 0〜1; y: 0〜1。同時,亦可使用摻 雜有銅、碳六十、銀等的聚合物,包括 TCNQ(7,7,8,8-tetracyanoquinodimethane) 、 PCBM (methanofullerene 6,6-phenyl C61-butyric acid methyl ester)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、 以其他物質摻雜之TCNQ、或任何其他聚合物材料其包括 有以一電脈衝而控制之雙穩定或多穩定電阻態。 如前所述,第2a圖的電極元件提供了理想的電壓與電 鲁流位階,但並不會如同先前技術一般將熱量快速導離 RRAM元件230。此RRAM元件因此保留了電流產生的大 部分熱量,進而減少用以在RRAM之中產生理想熱量位階 所需要的電流輸入,因而較容易改變這些元件相關的狀態。 第2b圖繪示了另一實施例250,其中多層元件220的 高電阻率、以及所伴隨的熱量增加,係受到控制以提供熱 量至RRAM裝置230,240。除此改變之外,其他的次元件 以及元件成分係與上述的部分相同。 用以製造上述電極元件的製程實施例,係如第3a-3e 12 1336938 圖所示。在第3a圖中,此製程從沈積頂電極材料2、底電 極材料4、以及導電材料層7,8於一基板上開始。需要注意 的是’設計者可以自由地選擇特定的材料以及層數,從僅 具有頂與底電極的簡單結構到多層導電層,無論是否具有 側壁導體均可。舉例而言,在此所示的結構具有兩層導電 材料層、頂與底電極、以及一組側壁導體。 此沈積作用可利用此領域的習知技術所進行,較佳係 由CVD與PVD製程進行。特定製程係由所選定的材料本 質而決定’如該領域中所週知。 _ 在初始沈積之後,此製程係繼續進行以建立層堆疊的 尺寸,如第3b圖所示,其係從遮罩9的沈積開始,其位置 與尺寸係生成具有理想橫向尺寸的堆疊。此製程使用了習 知的光微影製程,以生成如第3c圖所示的堆疊j。 側壁導體係以數個步驟而形成。首先,如第圖所 示,一層側壁導體材料6係被沈積,產生一層結構而覆蓋 整個堆疊及其周圍區域。如同前一沈積,此製程較佳 用習知技術進行。 ' 、藉由使用非等向性蝕刻移除從堆疊橫向延伸的材料、 癱以及至少部分堆疊頂端的#料,而移除多餘的材料 使用化學機械研磨製程(CMP)而將已經完成的電極元件 之上表面平面化,生成電極30,如同先前第le圖中所示。 此平面化必須受到控制,以外露頂電極32的上表 因、拄 確保二側壁導體36以及頂電極係位於同一平面。 。, ^另一變體實施例係如第如與4b圖所示。在此, 係將介電層49加到側壁導體46之上。如第4a 父佳 製程將接著從側壁導體材料的沈積步驟開始 71^此 進行介電層49的沈積。介電材料較佳包括二氧化矽、聚亞 13 1336938 醯胺、氮化矽、或其他習知的介電材料。 之後則進行習知的非等向性蝕刻步驟,以定義此結構 的橫向尺寸,接著以CMP進行平坦化步驟,產生如第4b 圖所示的結構。 上述的各種實施例,均係以稱為「疊置」的製程所進 行。以相同原理所進行的一替代方法,係如第5a與5b圖 所示。在此,電極元件50係在一基板中生成並填滿凹口而 形成一電極元件50。如圖所示,係提供一基板51,如同製 造晶圓一般,並在基板中形成一凹口 53。接著,進行連續 馨沈積步驟,其係與上述相同,而沈積頂與底電極層52,54、 以及導電材料層57,58。這些層結構填滿了凹口 53,生成 了「層疊」效果。所生成的結構係被平坦化,以移除延伸 至凹口 53之上的材料層,如第5b圖所示。 用以形成此一電極結構的製程,可參照第6a-6d圖而 獲得詳述。在此,電極結構60包括一基板61,並在基板 中形成有一栓塞65,如第6a圖所示。此栓塞係作用為一 導電接點,較佳係由如鎢等耐熱金屬所構成,且係使用習 知方法而形成於基板中。其他财熱金屬包括欽、翻、I呂、 籲組、銅、舶、銀、鑭、鎳、釕、及其氧化物。 凹口 67係形成於基板中,如第6b圖所示,較佳係由 一優先蝕刻製程所進行,並選擇對於栓塞有高蝕刻速率而 對基板材料有較低餘刻速率的製程。如圖所示的較佳結構 中,適合的實施例包括鎢蝕刻製程。 藉著使用連續沈積步驟、接著進行CMP而完成電極 60,如第6c與6d圖所示。與其他電路元件的接觸係由栓 塞元件65以及頂電極62而完成。 如此領域所週知,在具有相當高深寬比的開口中進行 14 丄州938 被沈積件65 ’可能在所沈積材料巾產生深裂縫。 留空洞或史沿著所沈積結構的邊緣順形地沈積’ 步驟可將=門非:一句/心的材料。後她 為其順形性很高,鎢特在沈積結構中。因 示,即使餘刻至仏if 讀現象,如第6e圖所 可見。在此θ 衣度之後,裂縫69在栓塞元件中仍然 成的材料產生=接的材料可能無法與先前形 太旅的接觸,產生較差的層間接觸。 構在填,、L 上述的問題’因為電極材料以及相關結 極材料與^ 11之溝槽時相#有用。此材料確保了在電 雜的鶴金屬之間,良好而連續的接觸。 人所^:月係已參照較佳實施例來加以描述,將為吾 Ζ發明創作並未受限於其詳細描述内容。 替換方樣式係已於先前描述中所建議,並且其他 別是二;^ 11樣式將為熟習此項技藝之人士所思及。特 本發明^媒杜么明之結構與方法’所有具有實質上相同於 脫件結合而達成與本發明實質上相同結果者皆不 範嘴。因此’所有此等替換方式及修改 界i的ίί洛ί本發明於隨附申請專利範圍及其均等物所 刷文木Μ 壬何在*文中提及之專利申請案以及印 刷文本,均係列為本案之參考。 【圖式簡單說明】 ,h-lc圖係繪示本發明一實施例及其變體。
Id圖係繪示第lb與lc圖之實施例的操作。 的實施與%圖係繪示包括有本發明實施例之記憶元件 1336938 第3a-3e圖係繪示本發明製程的實施例。 ^ 會示另一本發明製程的實施例。 第5a與5b圖係繪示本發明另一督 第6a-6e圖係繪示用以製造本發 j製程。 73另一實施例的製程 【主要元件符號說明】 1 堆疊 2 頂電極材料 4 底電極材料 6 側壁導體材料 7,8 導電材料層 9 遮罩 10 電極結構 12 頂層 14 底層 20 電極結構 22,24 電極元件 26 側壁導體 30 電極結構 32,34 電極元件 36 側壁導體 37,38 導體層 46 側壁導體 49 介電層 50 電極元件 51 基板 52 頂電極 16 1336938 53 凹口 54 底電極 57,58 導電材料層 60 電極元件 61 基板 62 頂電極 65 栓塞元件 67 凹口 69 裂縫 200 記憶胞 202,204 電極元件 206 側壁導體 207,208 導體層 210 頂電極 220 底電極 230 記憶元件 230,240 RRAM裝置
Claims (1)
133 卿 8 、申請專利範圍 號 中華民國發明專射請轉獅丨〇166〇 無割線之申請專利範圍替換本 中華民國99年9月2日送呈 h 一種記憶結構,包括: ,,,、 ^個電極層,其雜大致為平板狀並以ϋ 取外層提供導電接點,並定義一第一電流路徑·;ϋ 所:Πί自由一組側壁層端點以及-電極層導“點 记憶元件,與該複數個電極層之最外者連接。 ^如中請專利範圍第丨項所述之記憶 與第二電流路徑係形成並聯電阻。 _ - 奢專利範圍第2項所述之記憶結構,呈中令補數 個電極層係沈積於-半導體結構中。 /、中》亥複數 層传1°=專利軌圍第2項所述之記憶結構,其中今電柽 :由選自下列群組之-材料所構成:氮化鈦、、=極 項所述之記憶結構, 項所述之記憶結構, 其中該電極 更包括複數 5.如申請專利範圍第4 結構係為高度摻雜。 6_如申請專利範圍第2 個電極層對。 18 如申清專利範圍第2 ^ 導體係由鈦所構成。 Ά5己憶結構’其中該側壁 8·如申請專利範圍第2項所诚夕^ a 極層係為薄膜,、’L °己丨思結構,其中該4b電 ,、厚度係介於約〇 3至2〇奈米之間:電 9·如申請專利範圍第2 Jg%、+, 極層係為薄膜,且其厚度係結構,其中該些電 10·如申請專利範圍第2 Jg%、+, 壁導體層係為薄膜,且其厚度係:?至構2。=側 12·如申請專利範圍第2 結構提供電氣接觸於相鄰之咖構,其中該電極 結構係項所述之記憶結構,其中該電極 氣接】:::材料元件’以提供請am材料電 !4,如申請專利範圍第2 層材料係選擇以顯以展示高電科二及:熱性其。中靡 ====所述之記憶結構,其中_ 1336938
16· 一種電極結構,包括·· 一基板層,其中具有一凹口並且 該凹口之内部而可存取,· /、 第一導體接點於 複,個電極層連續地内襯於該凹口之内部. 電氣接 點。一第二導體,其係與該些電極層之最㈣形成 17.如申請專利範圍第16項所述之 層係沈積於-半導縣構之中。 構’其中該電極 上8俜:專利範圍第16項所述之電極結構,其中兮電極 =由選自下列群組之一材料所構成:氮化欽、=極
19.如申請專利範圍第18項所述之 極材料係經高度摻雜。 電極結構,其中該 些電
一種用以製造一電極結構之方法 沈積複數層電極材料; 包括下列步驟: 修剪該沈積結構至一預定寬度; 上; 順形地沈積一層側壁導體材料於該電極材料結構之 20 1336938 说,y層μ電填充材料於該側壁導電材料之上;以及 導於沈積結構以從該電極結構之上表面移除該側壁 層介電填充電極結構至-預定寬度,以及留下-电具兄材科其黏附至該側壁導體材料之外表面。 m申明專利知圍帛21項所述之方法’其中該電極層係 ^自下列群組之—材料所構成··氮化鈦、氮化組、與紐。 範圍第21項所述之方法’其中該些電極材 24_如申請專利範圍第21項所述之方法,其中該側壁導 層係由鈦所構成。
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-
2006
- 2006-12-15 US US11/611,428 patent/US8344347B2/en active Active
-
2007
- 2007-01-16 TW TW096101660A patent/TWI336938B/zh active
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US8344347B2 (en) | 2013-01-01 |
TW200832678A (en) | 2008-08-01 |
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