1305044 九、發明說明： 【發明所屬之技術領域】 本發明係有關於由以相轉換為基礎之記憶材料所構成 之高密度記憶元件，此記憶材料包括以硫屬化物為基礎之 材料與其他材料。本發明亦有關於用以製造此等元件之方 法。 【先前技術】 • 以相轉換為基礎之記憶材料係被廣泛地運用於讀寫光 碟片中。這些材料包括有至少兩種固態相，包括如一大部 分為非晶態之固態相，以及一大體上為結晶態之固態相。 雷射脈衝係用於讀寫光碟片中，以在二種相中切換，並讀 取此種材料於相轉換之後的光學性質。 如硫屬化物及類似材料之此等相轉換記憶材料，可藉 由施加其幅度適用於積體電路中之電流，而致使晶相轉 換。一般而言非晶態之特徵係其電阻高‘結晶態，此電阻 值可輕易測量得到而用以作為指示。這種特性則引發使用 Φ 可程式化電阻材料以形成非揮發性記憶體電路等關注，此 電路可用於隨機存取讀寫。 從非晶態轉變至結晶態一般係為一低電流步驟。從結 晶態轉變至非晶態（以下指稱為重置（reset)) —般係為一高 電流步驟，其包括一短暫的高電流密度脈衝以融化或破壞 結晶結構，其後此相轉換材料會快速冷卻，抑制相轉換的 過程，使得至少部份相轉換結構得以維持在非晶態。理想 狀態下，致使相轉換材料從結晶態轉變至非晶態之重置電 流幅度應越低越好。欲降低重置所需的重置電流幅度，可 藉由減低在記憶體中的相轉換材料元件的尺寸、以及減少 電極與此相轉換材料之接觸面積而達成，因此可針對此相 1305044 轉換材料元件施加較小的絕對電流值而達成較高的電流密 度。 此領域發展的一種方法係致力於在一積體電路結構上 形成微小孔洞，並使用微量可程式化之電阻材料填充這些 微小孔洞。致力於此等微小孔洞的專利包括：於1997年 11月11曰公告之美國專利第5,687，112號”Multibit Single Cell Memory Element Having Tapered Contact”、發明人為 Ovshinky;於1998年8月4日公告之美國專利第5,789,277 號”Method of Making Chalogenide [sic] Memory Device”、 發明人為Zahorik等；於2000年11月21日公告之美國專 利第 6,150,253 號” Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same”、發明人為Doan等。 此外’在以非常小的尺度製造這些裝置、以及欲滿足 生產大尺寸記憶裝置時所需求的嚴格製程變數時，則會遭 遇到問題。在一電阻記憶元件中的接點會佔據相當可觀的 空間。因此，較佳係提供一記憶細胞結構其可減少接點的 尺寸，進而縮小一記憶細胞之整體尺寸。1305044 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a high-density memory element composed of a phase-converted memory material including a chalcogenide-based material and other materials. . The invention also relates to methods for making such components. [Prior Art] • Memory materials based on phase conversion are widely used in reading and writing optical discs. These materials include at least two solid phases, including, for example, a solid phase that is largely amorphous, and a solid phase that is substantially crystalline. Laser pulses are used to read and write optical discs to switch between the two phases and to read the optical properties of the material after phase inversion. Such phase-converting memory materials, such as chalcogenides and the like, can be converted by crystal phase by applying a current whose magnitude is applied to the integrated circuit. In general, the amorphous state is characterized by its high resistance 'crystalline state, which can be easily measured and used as an indication. This feature raises concerns about the use of Φ programmable resistive materials to form non-volatile memory circuits that can be used for random access. The transition from amorphous to crystalline is generally a low current step. Transitioning from a crystalline state to an amorphous state (hereinafter referred to as a reset) is generally a high current step that includes a brief high current density pulse to melt or destroy the crystalline structure, after which the phase transition material will Rapid cooling suppresses the phase transition process so that at least a portion of the phase inversion structure is maintained in an amorphous state. Ideally, the reset current amplitude that causes the phase change material to transition from crystalline to amorphous should be as low as possible. To reduce the magnitude of the reset current required for resetting, this can be achieved by reducing the size of the phase change material component in the memory and reducing the contact area of the electrode with the phase change material, so that the material can be converted for this phase 1305044 The component applies a small absolute current value to achieve a higher current density. One method developed in this field is to create tiny holes in an integrated circuit structure and fill these tiny holes with a trace of programmable resistance material. The patents dedicated to such microscopic holes include: "Multibit Single Cell Memory Element Having Tapered Contact", published on November 11, 1997, "Multibit Single Cell Memory Element Having Tapered Contact", inventor Ovshinky; announced on August 4, 1998 US Patent No. 5,789,277, "Method of Making Chalogenide [sic] Memory Device", inventor Zahorik et al., U.S. Patent No. 6,150,253, issued November 21, 2000, "Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same", the inventor is Doan et al. In addition, problems arise when manufacturing these devices on very small scales and the rigorous process variables required to produce large-size memory devices. The contacts in a resistive memory element occupy a considerable amount of space. Therefore, it is preferred to provide a memory cell structure which reduces the size of the contacts and thereby reduces the overall size of a memory cell.
【發明内容】 本發明描述了在一導橋結構中之一電阻隨機存取 位於包括一接觸結構’而第一與第二電極則； 、嘉/ 繞此接觸結構之一内壁。第二電極係位於周 -電阻並藉由一絕緣材料而與第—電極隔開： 接觸結;-與第邊緣表面。 内的第二電=俜ίί係連接至…曰體，而在接觸結構 使用以將位元線連接至第二電^。 才錢私係被 6 1305044 *電中’—金屬層間介電層側壁子係沈積 二上在 巧面r第二實施例中二介 -側壁子或4窗電極係在_刻，在此則不需要形成 則具包Ϊ有-接觸結構，此接觸結構 L且係沿著;觸結=表 電:形成於鶴材料之上表面之上;ί 緣材料可用以分隔第一與;!=支持_之内’使得絕 以=體尺寸，因此搏除在傳統4中以 明構;:法。本發明内容說 可透過下列說等將 【實施方式】 可以構ΐ”與方法之說明係參照至第1-15圖。 明可利用其:特彳;些::例^ 问貫_中的相似元件，係以相似的數字指定=在不 1305044 明參照第1圖’其顯示一記一 可依照本發明而實施。在第i “ 意圖，其 一字元線123、以及一字亓蝻共问源極線128、 列。位元線⑷與142係大致於Y軸而排 在方塊U5中的一 Y輛解碼器二字m巧。因此， 至字元線取⑶。在方塊146、m^ ’係輕接 感測放大器係_至位元線141 X =碼器與-組 係耦接至存取電晶體15〇151 γ Z。/、同源極線128 晶體150之閘極軸接至元’ 53 7極終端。存取電 至字70線123。存取電晶體153之閘極俜耦接 150 135之底電極構件132，M 土叫仅。己隐細胞 iV；〇 I，卜，ΐ ί接至侧壁腳位記憶細胞之底電極“ =、，土腳位。己憶細胞的位元線142。從圖中鬥 =m係被二列記憶細胞所共用，其中一列:如圖;; 搞^方、向排列。在其他實施例中，這些存取電晶體可被二 或其他結構所取代，這些結構可控制電流以在記情 陣列中選定用以讀取與寫入資料。 隐 如圖^所示，其根據本發明一實施例，顯示一積體電 0的簡化方塊圖。此積體電路275係在一半導體基板 ^括一 §己憶陣列，其係利用侧壁活性腳位雙穩態隨機存 己憶細胞而實施。一列解碼器261係耦接至複數個字元 ^ 2 ’子元線係沿著記憶陣列260中的各列而設置。一 馬器263係耦接至複數個位元線264，位元線係沿著 5己思障列260中的行而設置，以從側壁腳位記憶細胞中讀 8 1305044 取並程式化資料。陳列？6η Λ v 而提供至-行解碼i=6G與：3 t的感測放大器與資料輸入結』:=土6;料在方= 而耦接至行解石馬器263。資料貞枓匯流排267 ^入ί 外部之其他資料來源，而經由資 電路上，例如一 I】目的；路274係包括於此積體 可提供單曰片系絲^的處益或特定目的應用電路、或 ί 經由資料輸出線272、而傳輸至積體雷 之資料ΐ^/輸出蟑或其他位於積體電路275内部或外部 在本實施例中’使用偏壓安 a 所施加的偏壓供應電壓 用在此領域中所週知的特3 。此控制器可使 代實施例中，此控制器包括施。在-替 -電腦程式以控制此元件的摔1體電路係執行 用特定目的邏輯電路與泛=處中’可使 控制器。 处里杰的結合’以實施此 :第3圖所緣示’其係根據本發明 ，，，、頁不衣造雙穩態電阻隨機存取記 實轭例，而 面圖，其包括形成一電晶體結構驟的剖 =3。。係形成於一半導體基板31=::以J取 ^ 基板31G内作用為共同源極區域 元（Η:作Λ為沒極區域之n型終端314與、16。多曰二Ϊ (_)線32G’322係形成了存取電晶體的閘^曰^ 1305044 間介電層330係包括了介電填充330a，330b，330c，其中介 電填充330b係形成於多晶矽字元線320,322之上。適合用 於此層間介電層330的材料包括硼磷矽玻璃氧化物(bpsG oxide)與電漿增強正矽酸乙酯（pETE〇s) $化物。此層係 經圖案化，並形成導電結構’包括一共同源‘線與接觸結 構326,328。此導電材料可為鎢或其他適合做為接觸結構之 材料與複合材料。接觸結構326,328係包括多種形狀，包 括圓形、方形、或其他隨著所選定設計而適合用於一接觸 栓塞之形狀。SUMMARY OF THE INVENTION The present invention describes a resistive random access in a via structure that includes a contact structure 'and a first and second electrode; and an inner wall of the contact structure. The second electrode is located at the periphery-resistance and is separated from the first electrode by an insulating material: a contact junction; and a surface of the edge. The second electrical = 俜 ίί is connected to the body, and is used in the contact structure to connect the bit line to the second cell.才钱私系 is 61305044 *Electrical--metal interlayer dielectric layer sidewall sub-system deposition two on the smart surface r in the second embodiment of the second-wall or four-window electrode system in the _ engraved, here is not It is necessary to form a package-with-contact structure, and the contact structure L is along the line; the junction is electric: formed on the upper surface of the crane material; ί edge material can be used to separate the first and; The inside 'make the absolute body size, so beat in the traditional 4 to make it clear;: method. The content of the present invention can be referred to by the following descriptions, and the description of the method can be referred to the drawings 1-15. It can be utilized: special features: some examples: The elements are designated by similar numbers = in 1350,044, see Fig. 1 ', which shows that one can be implemented in accordance with the present invention. In the i-th intent, one of the word lines 123, and one word Source line 128, column. The bit lines (4) and 142 are arranged on the Y-axis and are arranged in a U-block decoder in block U5. Therefore, the word line is taken (3). At block 146, m^', the sense amplifier system _ to the bit line 141 X = the coder and the combination are coupled to the access transistor 15 〇 151 γ Z . /, the gate line of the homopolar line 128 crystal 150 is connected to the element '53 7-pole terminal. Access to word line 70 123. The gate of the access transistor 153 is coupled to the bottom electrode member 132 of the 150 135, M is called only. The cryptic cell iV; 〇I, 卜, ΐ ί is connected to the bottom electrode of the memory cell of the sidewall. " =,, the soil position. The bit line of the cell is 142. From the figure, the bucket = m is the second column. Memory cells are shared, one of which: as shown in Fig.;; the square and the direction. In other embodiments, these access transistors can be replaced by two or other structures that control the current in the array. Selected for reading and writing data. As shown in FIG. 2, in accordance with an embodiment of the present invention, a simplified block diagram of an integrated body 0 is shown. The integrated circuit 275 is mounted on a semiconductor substrate. An array has been implemented, which is implemented by using a sidewall active foot bistable random memory cell. A column decoder 261 is coupled to a plurality of characters ^ 2 sub-line lines along each of the memory arrays 260 Arranged in a column, a horse 263 is coupled to a plurality of bit lines 264, and the bit lines are arranged along the lines in the 5th barrier column 260 to read 8 1305044 from the sidewall memory cells. Stylized data. Display? 6η Λ v provides to-line decoding i=6G and: 3 t sense amplifier and data input Knot: = soil 6; material in the side = and coupled to the calculus horse 263. Data 贞枓 bus 267 ^ into ί external sources of information, and through the circuit, for example, an I] purpose; The 274 series includes the benefit of the single-twisted wire or the specific purpose application circuit, or the data transmitted to the integrated body via the data output line 272, ΐ^/output 蟑 or other located in the integrated body. The bias supply voltage applied internally or externally by circuit 275 in the present embodiment using a bias voltage a is used in the art as is well known in the art. This controller may, in an embodiment, include In the case of a computer program to control this component, the circuit of the falling body is executed with a specific purpose logic circuit and the 'in the middle of the 'can make the controller. The combination of Lijie' to implement this: the third picture shows The invention is based on the present invention, and the bistable resistive random access recording yoke is exemplified, and the sectional view includes a section 3 of forming a transistor structure. The system is formed on a semiconductor substrate. 31=:: J is taken as the common source region element in the substrate 31G (Η: Λ is the immersion region The n-type terminals 314 and 16 of the domain. The multi-diode (_) line 32G'322 forms a gate for accessing the transistor. The dielectric layer 330 includes a dielectric fill 330a, 330b, 330c. The dielectric fill 330b is formed over the polysilicon character lines 320, 322. Materials suitable for the interlayer dielectric layer 330 include borophosphonium glass oxide (bpsG oxide) and plasma enhanced n-decanoate (pETE).化物s) $. This layer is patterned and forms a conductive structure 'including a common source' line and contact structures 326, 328. This conductive material can be tungsten or other suitable material and composite material for the contact structure. The contact structures 326, 328 comprise a variety of shapes, including circular, square, or other shapes suitable for a contact plug as the selected design.
第一電極345具有一周邊延伸形狀（例如環形）而圍 繞接觸結構326之一内壁。相似地，第一電極347具有一 ，邊延伸形狀（例如環形）而圍繞接觸結構328之一内壁。 母5亥第一電極345,347係由一如氮化鈦之導電材料所構 成。此導電材料可為鎮或其他適合用於栓塞盘導線έ士蠢 材料與組合物。共同源極線係接觸到源極區域 歹j中之一列而作用為一共同源極線。此接蝙結構326 係分別接觸至汲極終端314,316。 ’ 第4圖係根據本發明第一實施例，繪示用以製造雙 ^導橋電阻隨機存取記憶體之第二步驟的剖面圖4〇〇, ^ ^括鎢凹陷蝕刻、沈積一襯底介電層、以及沈積一第二： t紅在接觸結構326中，接觸結構326中的鎢的一頂部ί 刻，蝕刻深寬比係約1:1。在蝕刻步驟中，層間介 的選擇性係足夠高以避免介電填充33〇a，33〇b受到蝕^ :以产的化合物係為六_SF6)。· 冰度遠擇係相對於一接觸孔的尺寸。在一實施例中， =〇·2μιη的接觸孔而言，栓塞326的鎢蝕刻深度係 的一襯底介電層410係沈積於接觸結構中之轉金屬 餘部分、並沿著第一電極345之内壁以一化學氣= 積（CVD)製程進行。此滅介電層之選擇條件，係 1305044 具有低導熱性特徵的物質，例如二氧 極420係沈積於襯底介電層41G、襯 G電 以及介電填充物33〇a，33()b，33Ge之上表面 二導=徵=而;;他可提供充分導電 ，質、或一氧化物-亂化物-氧化物（〇N〇)或矽_ _The first electrode 345 has a peripherally extending shape (e.g., a ring shape) surrounding one of the inner walls of the contact structure 326. Similarly, the first electrode 347 has an edge extending shape (e.g., a ring shape) surrounding one of the inner walls of the contact structure 328. The first electrode 345, 347 of the mother 5 hai is composed of a conductive material such as titanium nitride. This electrically conductive material can be a town or other suitable material for embedding disc wires and compositions. The common source line contacts one of the source regions 歹j and acts as a common source line. The bat structure 326 is in contact with the drain terminals 314, 316, respectively. 4 is a cross-sectional view showing a second step of fabricating a dual-resistance resistor random access memory according to a first embodiment of the present invention, wherein a tungsten recess is etched and a substrate is deposited. The dielectric layer, and a second deposited: t red in the contact structure 326, a top portion of the tungsten in the contact structure 326, the etch aspect ratio is about 1:1. In the etching step, the interlayer dielectric selectivity is sufficiently high to avoid dielectric filling of 33〇a, 33〇b is etched: the compound produced is hexa-SF6). · The degree of ice is determined relative to the size of a contact hole. In one embodiment, for a contact hole of 〇·2μηη, a substrate dielectric layer 410 of the tungsten etch depth of the plug 326 is deposited on the metal portion of the contact structure and along the first electrode 345. The inner wall is made by a chemical gas = product (CVD) process. The selection condition of the de-energized layer is 1305044. The material having low thermal conductivity characteristics, for example, the oxycarbon diode 420 is deposited on the substrate dielectric layer 41G, the lining G, and the dielectric filler 33〇a, 33()b. , the surface of the 33Ge above the second derivative = sign = and;; he can provide sufficient conductivity, quality, or oxide - chaotic compound - oxide (〇N〇) or 矽 _ _
^化物-氧化物（SONO)多層結構。或者，此填充物可包 括一電絕緣體，其包括一個以上選自以下群組之元素：矽、 ，、銘、组、氮、氧、與碳。在較佳元件中，此填充物且 ，導熱性，低㈣0.G14 jWK*see。在—較U施例 ，此熱絕緣體之導熱性係低於相轉換材料之非晶態的導 …性’或者對於-包含有GST之相轉換材料而言、低於約 0/03 J/Cm*K* sec。代表性的絕熱材料包括由矽、碳、氧、 氟、與氫所組成之複合材料。可使用於熱絕緣填充層之熱 絕緣材料的範例，包括二氧化矽、SiC〇H、聚亞醯胺、聚 、以及氟碳聚合物。其他可用於熱絕緣填充層中的材 料^例、包括氟化之一氧化石夕、石夕氧烧(siiseSqUi〇xane)、聚 ，芳香醚（polyarylene ether)、聚對二曱苯(paryiene)、含 氟聚合物、含氟非晶碳、鑽石類碳、多孔性二氧化石夕、中 孔性^氧$矽、多孔性矽氧烷、多孔性聚亞醯胺、以及多 孔性聚亞芳香醚。單層或複合層均可提供熱絕緣與電絕緣 效果。 ，第5 ϋ繪示了 一剖面圖5〇〇，其係說明在第一實施例 中製造雙穩態導橋電阻隨機存取記憶體時之第三步驟’包 括研磨一第二電極、沈積一電阻記憶材料、以及圖案化此 電阻。己隐材料。第一電極420之一上表面係攀研磨，以移 除過量而可能從接觸材料326,328中露出的材料，進而在 1305044 ί 中形成-第二電極420a、並在第二接觸 ί機械研磨f i第：電極4 2 〇 b。研磨製程的實施例包括 、却和广l 接著則以毛刷清潔與液體及/或氣體清 ^5 —、中所週知。或者，進行化學機械研磨時， 1 夕二;义3磨程度，以同時移除可能突出於接觸結 電層410 *與第極黎偷係藉由伯襯底介 電層410、盥第二雷^ 隔開。弟一電極345、概底介 一電阻記憶材料彳位120&之上表面，係位於同一平面。 姐11·咅姑斜導柃si j係耜由微影製程圖案化，以形成一電 伤其中電阻記憶材料導橋510之長度， 由舛旦彡制浐m安儿 之厗度。相似地，電阻記憶材料係 雷ϋίΐί化以形成—電阻記憶材料導橋520，复中 己憶材料導橋520之長度係大於襯底介電 之 度。電阻記憶材料導橋Sin技, 曰 夂& 連接至第—雷搞47π = 係被蝕划，以允許第一電極345 ίίί電極& °電阻記憶材料導橋510之適合料 ίί:= 旦：可使用其他形狀。電阻記憶材料5 0 之較佳寬度係介於10至8〇nm之間。 <了叶等僑51〇 電阻記憶材料導橋51G，52Q之成分可 選擇’包括但不限於，—硫屬化物材料 t夕材枓中 二料、一雙元素化合物、以及一聚合物材丨。二(C:R) 實施例係包括以相轉換為基礎之記憶材田胞的 =硫J化物為基礎之材料與其他材料。硫屬^^括 凡素之任一者：氧（〇)、硫（S)、硒（Se) 下列 形^週期表上第力族的部分。硫屬 二 几素與-更為正電性之元素或自由基結合括屬 物2包括將硫屬化合物與其他物質如過：屬合 一硫屬化合物合金通常包括一個以上選1屬專結合。 襴的元素，例如錯（Ge)以及錫（Sn) j週期表第六 物合金包括下列元素中-個以上的複合物通：，(:屬)化合 12^Synthesis-oxide (SONO) multilayer structure. Alternatively, the filler may comprise an electrical insulator comprising one or more elements selected from the group consisting of: 矽, ,, 铭, groups, nitrogen, oxygen, and carbon. In the preferred component, this filler is, thermally conductive, low (iv) 0.G14 jWK*see. In the case of U, the thermal conductivity of the thermal insulator is lower than the amorphous state of the phase change material or less than about 0/03 J/cm for the phase conversion material containing GST. *K* sec. Representative insulating materials include composites composed of ruthenium, carbon, oxygen, fluorine, and hydrogen. Examples of thermal insulating materials that can be used for the thermally insulating filler layer include ceria, SiC〇H, polyamidamine, poly, and fluorocarbon polymers. Other materials which can be used in the thermal insulating filling layer include fluorinated one oxidized stone, siiseSqUi xxane, poly, polyarylene ether, paryiene, Fluoropolymer, fluorine-containing amorphous carbon, diamond-based carbon, porous silica dioxide, mesoporous oxygen, porous siloxane, porous polyamine, and porous polyarylene ether . Both single or composite layers provide thermal insulation and electrical insulation. FIG. 5 is a cross-sectional view showing the third step of manufacturing the bistable bridge resistor random access memory in the first embodiment, including grinding a second electrode and depositing a second electrode. Resistive memory material, and patterned this resistor. Hidden material. The upper surface of one of the first electrodes 420 is ground to remove excess material that may be exposed from the contact material 326, 328, thereby forming a second electrode 420a in the 1305044 ί, and mechanically grinding the second in the second contact: Electrode 4 2 〇b. Embodiments of the polishing process include, but are widely known, followed by brush cleaning and liquid and/or gas cleaning. Or, when performing chemical mechanical polishing, the degree of the third grinding; to remove at the same time may protrude from the contact junction layer 410 * and the first pole to steal the system by the dielectric layer 410, the second ray ^ Separated. The first electrode 345 is provided on the same plane as the upper surface of the resistive memory material 120& Sister 11·咅姑斜柃柃si j耜 is patterned by the lithography process to form a electrical injury in which the length of the resistive memory material guide 510 is determined by the 舛m 儿 安 安. Similarly, the resistive memory material is thundered to form a resistive memory material via 520, and the length of the intermediate material bridge 520 is greater than the dielectric of the substrate. Resistor memory material bridge Sin technology, 曰夂 & connected to the first - Lei 47π = system is etched to allow the first electrode 345 ίίί electrode & ° resistance memory material guide 510 suitable for material ίί:= Other shapes can be used. The preferred width of the resistive memory material 50 is between 10 and 8 〇 nm. <Ye et al. 51 〇 resistance memory material guide bridge 51G, 52Q components can be selected 'including but not limited to, - chalcogenide material t 枓 material 枓 in the second material, a two-element compound, and a polymer material 丨. The second (C:R) embodiment includes materials and other materials based on phase transition-based memory cell fields. Sulfur is a member of any of the following: oxygen (〇), sulfur (S), selenium (Se). The chalcogenant and the more electropositive element or the radical conjugation of the moieties 2 include the addition of a chalcogenide compound to other substances such as a genus. The monochalcogenide alloy usually comprises one or more exclusive genus combinations. The elements of ruthenium, such as the (Ge) and tin (Sn) j periodic table sixth alloys include more than one of the following elements: (: genus) compound 12
特殊合金包括 Ge2Sb2Te5、GeSb2Te4、以及 GeSb4Te7。 (Noboru Yamada，’’Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording，，，兑/五 v. 3 709, 1305044 ( 1 η )、以及銀（Ag )。許多以相轉換為基礎之 6己隐材料已經被描述於技術文件中，包括下列土楚^ /石西^Γ錦、銦A西、録，蹄、錯/碑、錯/録/碎、銦/錄/蹄、鎵 31、锡/録/蹄、銦/録/錯、銀/铜/錦/碲、錯/錫/綈崎、: 2弟/硒/碲、以及碲/鍺/銻/硫。在鍺/銻/碲合金家族中， 鲁试大範圍的合金成分。此成分可以下列特徵式表示. TeaGebSb100_(a+b)。一位研究員描述了最有用的合金係’，、 沈積材料中所包含之平均碲濃度係遠低於7〇%，典型地 低^^0%，並在一般型態合金中的碲含量範圍從最低 至最向58%，且最佳係介於48%至58%之碑含量。錯的濃 度，高於約5%，且其在材料中的平均範圍係從最低8%至 最咼30%，一般係低於50%。最佳地，鍺的濃度範圍係介 於8%至40%。在此成分中所剩下的主要成分則為銻。上述 百分比係為原子百分比’其為所有組成元素加總為1 〇〇%。 (Ovshinky ‘112專利，攔10〜11)由另一研究者所評估的 pp. 28-37(1997))更一般地，過渡金屬如鉻(Cr)、鐵(Fe)、 鎳（Ni)、鈮(Nb)、鈀（Pd)、鉑（Pt)、以及上述之混合物或合 金，可與錯/錄/碌結合以形成一相轉換合金其包括有可程式 化的電阻性質。可使用的記憶材料的特殊範例，係如 Ovshinsky ‘112專利中欄11-13所述，其範例在此係列入參 考0 在此記憶胞之活性通道區域中，相轉換合金係可在一 第一結構態與一第二結構態之間以其局部次序切換，其中 第一結構態一般係為非晶固態（amorphous solid phase)，而 第二結構態一般係為一結晶固態（crystalline solid phase)。 此合金至少為雙穩態的。此詞彙「非晶」係用以指稱一相 13 1305044 對較無次序之結構，其較之一單晶更無次序性，而帶有可 偵測之特徵如較之結晶態更高之電阻值。此詞囊「結晶，離、 係用以指稱一相對較有次序之結構，其較之非晶態更有次 序’因此包括有可偵測的特徵例如比非晶態更^的電阻 值。典型地，相轉換材料可電切換至完全結晶態與完全非 晶悲之間所有可偵測的不同狀態。其他受到非晶態與结晶 態之改變而影響之材料特中包括，原子次序、自電 度、以及活化能。此材料可切換成為不同的固態、或可切 換成為由兩種以上固態所形成之混合物，提供從非曰萍、至 結晶態之間的灰階部分。此材料中的電性質亦可能隨之改 相轉換合金可藉由施加一電脈衝而從一種相態切換至 另一相態。先前觀察指出，一較短、較大幅度的脈衝傾向 於將相轉換材料的相態改變成大體為非晶態。—較長、'較 低幅度的脈衝傾向於將相轉換材料的相態改變成大體為結 晶態。在較短、較大幅度脈衝中的能量，夠大因此足以& 壞結晶結構的鍵結，同時夠短因此可以防止原子再次排列 成結晶態。在沒有不適當實驗的情形下，可決定特別適用 於一特定相轉換合金的適當脈衝量變曲線。在本文的後續 • 部分，此相轉換材料係以GST代稱，同時吾人亦需瞭解^ 亦可使用其他類型之相轉換材料。在本文中所描述之一種 適用於PCRAM中之材料，係為GexSbyTez，其x:y:z = 2:2:5。其他 GexSbyTez 的成分包括 X: 〇〜5; y: 〇~5; z: 0〜10。 可用於本發明其他實施例中之其他可程式化之記憶材 料包括’摻雜A之GST、GexSby、或其他以不同結晶態轉 換來決定電阻之物質；PrxCayMn03、PrSrMn03、ZrOx、或 其他使用一電脈衝以改變電阻狀態之物質； TCNQ(7,7,8,8-tetracyanoquinodimethane) 、 PCBM (methanofullerene 6,6-phenyl C61-butyric acid methyl 14 1305044 ester)、TCNQ-PCBM、Cu-TCNQ、Ag_ _ 以其他^摻雜之TCNQ、或任何其他^物^料其包括 有以〆電脈衝而控制之雙穩態或多穩態阻能· ^ ( CMR) ^ , x：y = 〇-〇；5 ^ 成分ίΐ包括有錳氧化物之超巨磁阵材 料，以及一又兀素化s物如Νΐχ〇其、^ 其他成分為χ:0〜l;y:0〜1。 7 m 第6圖係繪示一剖面圖_，其說明在第一實施例中 製Ϊ雙Ϊ = Ϊ阻隨Γ取記憶體之第四1驟？包括沈 積弟底）丨電層、沈積-金屬層間介電層、以及圖案化 二見底ΐΪί _係沈積於電阻記憶材料 V橋，520之上、亚遍布整個剖面圖600的上表面。一 金屬層間介電層620係形成於第二襯底^ 面之上二金屬層間介電層_的_選擇性i實質上4 層620之材料係為以，層間介電 並停止在第二襯底介電層61〇而圖案二？ 30介^^ 介電層 61。““ = 擇性地停止於第二減介電層61G。仪、並選 第7圖係繪示一剖面圖700，其說明 態導橋電阻隨機存取記憶體之第五步驟， ，-金?層間介電側壁子、形成—第二介電突破、二 一位兀線。金屬層間介電側壁子71〇,712係藉由 ^ ^積^:積於介層t 63Q，632之中。金屬層間介 情姑粗目的係在一第二介電突破步驟之後保護電阻^ 巧二笛虽金屬層間介電側壁子71〇,712 <間側壁子蝕; “ΪΪ二襯底介電層610時，則利用以氟為基礎之Ϊί 向丨生乾式蝕刻製程而進行第二介電突破步驟，此蝕刻f 15 1305044 止在第二電極420a，420b之上夺 於金屬層間介電侧壁子7l〇 7：J面。—位元線720係沈積 層620之上形成—金屬化，之内，並在金屬層間介電 一閘極或字元線。層。位元線720的方向係垂直於 第8圖係繪示第二實施 體800之剖面圖，包括沈浐八之V橋電阻隨機存取記憶 案化介層窗820,822。金屬^ 間介電層810、以及圖 憶材料導橋510,520之上7電層810係沈積於電阻記 示之第二襯底介電層。二氧不包括在第一實施例中所 層810中之一適合材料。一 為可用於金屬層間介電 驟而圖案化，此蝕刻步驟係停:介f窗820係利用蝕刻步 面。介層窗82Θ的尺寸選擇，T 於第二電極420a之上表 座落於第二電極420a之上。使得介層窗820夠小而彳 為以氟為基礎之乾式蝕刻。^ ^介層窗蝕刻的化合物係 卜2。第9圖係為第二實施例曰二820之深寬比係2約 剖面圖900,包括沈積一位=導9=阻隨機存取記憶體^ 介層窗820,822之内，並在全屬岸線910係沈積』 方向係垂直於—閘極或字元線。 記情髀本啦明第三實施例之導橋電阻隨機存取 ίΪΪ 包括沈積一硬遮罩於-電阻記憶材 二山〜之上。第二電極420之一上表面係經研磨，以移除 =出於接觸結構326,328之過量材料，而生成在第一接觸 二構32=中之一第二電極42〇a、以及位於第二接觸結構328 心^一第二電極42〇b。研磨製程的實施例包括化學機械研 磨衣程、接著則以毛刷清潔與液體及/或氣體清潔程 此領域中所週知。或者，進行化學機械研磨時，可 一超研磨程度，以同時移除可能突出於接觸結構32^仃至 底”，層410。第二電極420a係藉由薄膜襯底介電 <有見 而與第一電極345分隔。第一電極345、襯底介電展肖Special alloys include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7. (Noboru Yamada, ''Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording,,,/V. 3 709, 1305044 (1 η ), and Silver (Ag). Many Phase-converted 6-hidden material has been described in the technical documents, including the following soil Chu ^ / Shixi ^ Γ Jin, Indium A West, recorded, hoof, wrong / monument, wrong / recorded / broken, indium / recorded /hoof, gallium 31, tin / recording / hoof, indium / recorded / wrong, silver / copper / brocade / 碲, wrong / tin / 绨崎,: 2 brother / selenium / 碲, and 碲 / 锗 / 锑 / sulfur. In the 锗/锑/碲 alloy family, Lu tests a wide range of alloy compositions. This composition can be expressed in the following formula: TeaGebSb100_(a+b). One researcher described the most useful alloy system', in deposited materials. The average enthalpy concentration included is well below 7〇%, typically low by 0%, and the bismuth content in the general type alloy ranges from the lowest to the most 58%, and the optimum is between 48% and 58%. % of the tablet content. The wrong concentration, above about 5%, and its average range in the material is from the lowest 8% to the last 30%, generally less than 50%. Optimally, the concentration range of strontium is Between 8% and 40%. Here The main component remaining in the sub-item is 锑. The above percentage is the atomic percentage 'which is a total of 1 〇〇% for all constituent elements. (Ovshinky '112 patent, block 10~11) is evaluated by another researcher Pp. 28-37 (1997)) More generally, transition metals such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and the like The mixture or alloy can be combined with the error/recording/rhd to form a phase change alloy which includes programmable resistance properties. A special example of a memory material that can be used is described in Sections 11-13 of the Ovshinsky '112 patent, an example of which is incorporated herein by reference. In the active channel region of the memory cell, the phase change alloy system can be in the first The structural state and a second structural state are switched in their local order, wherein the first structural state is generally an amorphous solid phase and the second structural state is generally a crystalline solid phase. This alloy is at least bistable. The term "amorphous" is used to refer to a relatively unordered structure of a phase 13 1305044, which is more unordered than a single crystal, with detectable features such as higher resistance values than crystalline states. . The term "crystallizes, is used to refer to a relatively ordered structure that is more ordered than amorphous" and thus includes detectable features such as resistance values that are more than amorphous. The phase-converting material can be electrically switched to all detectable different states between the fully crystalline state and the completely amorphous state. Other materials that are affected by changes in the amorphous state and the crystalline state include, atomic order, self-power Degree, and activation energy. This material can be switched to a different solid state, or can be switched into a mixture of two or more solids, providing a gray-scale portion from non-puppet to crystalline state. The nature may also be accompanied by a phase-shifting alloy that can be switched from one phase to another by applying an electrical pulse. Previous observations indicate that a shorter, larger amplitude pulse tends to phase the phase-converting material. Change to a substantially amorphous state. - Longer, 'lower amplitude pulses tend to change the phase of the phase change material to a substantially crystalline state. The energy in a shorter, larger amplitude pulse is large enough to be sufficient & The bonding of the bad crystalline structure, while being short enough, prevents the atoms from being re-arranged into a crystalline state. In the absence of undue experimentation, an appropriate pulse-quantity curve that is particularly suitable for a particular phase-converting alloy can be determined. • In part, this phase conversion material is GST, and we also need to know ^ can also use other types of phase conversion materials. One of the materials described in this article for PCRAM is GexSbyTez, its x:y : z = 2:2: 5. Other components of GexSbyTez include X: 〇~5; y: 〇~5; z: 0~10. Other programmable memory materials that may be used in other embodiments of the invention include ' GST doped with A, GexSby, or other substances that change resistance by different crystal states; PrxCayMn03, PrSrMn03, ZrOx, or other substances that use an electrical pulse to change the resistance state; TCNQ(7,7,8,8- Tetracyanoquinodimethane), PCBM (methanofullerene 6,6-phenyl C61-butyric acid methyl 14 1305044 ester), TCNQ-PCBM, Cu-TCNQ, Ag_ _ other T-doped TCNQ, or any other material 〆电脉The controlled bistable or multi-stable resistance · ^ ( CMR ) ^ , x: y = 〇 - 〇; 5 ^ composition ΐ includes the giant giant magnetic matrix material with manganese oxide, and a deuterated s The other components are χ: 0~l; y: 0~1. 7 m Fig. 6 shows a cross-sectional view _, which illustrates the double Ϊ in the first embodiment = Ϊ The fourth step of the memory is as follows: the deposition of the bottom layer, the tantalum layer, the deposition-metal interlayer dielectric layer, and the patterning of the second layer ΐΪ _ is deposited on the resistive memory material V bridge, 520, sub It is spread over the entire upper surface of the cross-sectional view 600. A metal interlayer dielectric layer 620 is formed on the second substrate surface _ selectivity i substantially 4 layers 620 of the material is, the interlayer dielectric and stop in the second lining The bottom dielectric layer 61 is the same as the pattern two? 30 dielectric layer 61. "" = selectively stops at the second reduced dielectric layer 61G. The instrument and the selected figure 7 show a cross-sectional view 700, which illustrates the fifth step of the state-controlled bridge resistor random access memory, - the gold-level interlayer dielectric sidewall, the formation - the second dielectric breakthrough, two A squall line. The inter-metal dielectric sidewalls 71, 712 are accumulated in the vias t 63Q, 632 by ^ ^ accumulation. The inter-metal interlamellar is used to protect the resistance after a second dielectric breakthrough step. Although the inter-metal dielectric sidewalls 71〇, 712 < between the sidewalls; the second dielectric layer 610 At the same time, a second dielectric breakthrough step is performed on the fluorine-based dry etching process, and the etching f 15 1305044 is performed on the second electrode 420a, 420b over the inter-metal dielectric sidewall 7l. 〇7: J-face.—The bit line 720 is formed over the deposited layer 620—metallized, and a gate or word line is dielectrically interposed between the metal layers. The direction of the bit line 720 is perpendicular to Figure 8 is a cross-sectional view of the second embodiment 800, including a V-bridge resistor random access memory via 820, 822, a metal dielectric layer 810, and a material bridge 510, 520. The upper 7 electrical layer 810 is deposited on the second substrate dielectric layer of the resistance indication. The dioxygen does not include one of the suitable materials in the layer 810 in the first embodiment. The etching step is stopped: the f window 820 is etched, and the size of the via 82 is selected. Alternatively, T is placed on the second electrode 420a over the second electrode 420a, so that the via 820 is small enough to be a fluorine-based dry etch. Figure 9 is a cross-sectional view 900 of the aspect ratio 2 of the second embodiment 222, including a deposition of one = 9 = resist random access memory ^ 280, 822, and The shoreline 910 system is deposited perpendicular to the gate or word line. The third embodiment of the guide bridge resistor random access 包括 包括 includes a hard mask deposited on the - resistance memory material II ~ The upper surface of one of the second electrodes 420 is ground to remove excess material from the contact structures 326, 328, and is formed in the first contact two structures 32 = one of the second electrodes 42a, and located The second contact structure 328 is a second electrode 42A. An embodiment of the polishing process includes a chemical mechanical polishing process followed by a brush cleaning and liquid and/or gas cleaning process as is well known in the art. When performing chemical mechanical polishing, it can be super-abrasive to remove at the same time and may protrude from the contact structure. 32^仃 to bottom", layer 410. The second electrode 420a is dielectrically separated from the first electrode 345 by a thin film substrate. First electrode 345, substrate dielectric exhibition
Ml〇、 16 1305044 : ，以及第二電極420a之上表面係位於同一平面。 -電阻記憶材料係藉由微影製程圖案化，以形成 ，記憶材料導橋510,其中電阻記憶材料導橋51〇之長度 f大於襯底介電層41G之厚度。相似地，電阻記憶材料係 由微影製程圖案化以形成一電阻記憶材料導橋52〇，其中 電阻記憶材料導橋520之長度係大於襯底介電層412之厚 度。電阻記憶材料導橋51〇係被蝕刻，以允許第一電極345 連接至第二電極420a。電阻記憶材料導橋51〇之適合形狀 係為方形，但亦可使用其他形狀。電阻記憶材料導橋51〇 • 之較佳寬度係介於10至 80 nm之間。 一硬遮罩1010係沈積於電阻記憶材料導橋510之上。 此硬遮罩101 〇係包括一介電材料如二氧化石夕。對於硬遮罩 1〇1〇以及第一與第二電極345,420a而言，此蝕刻步驟可為 一單步驟非等向性蝕刻，或為一雙步驟製程，先以一第一 蝕刻化合物蝕刻硬遮罩1010，接著以一第二蝕刻化合物蝕 刻第一與第二電極345,420a。在一實施例中，硬遮罩1010 之蝕刻速率，係遠小於第二電極420a與在接觸結構326中 之第一電極345之側壁的蝕刻速率。適合的蝕刻方式係為 使用以Cl2為基礎之化合物的乾式蝕刻。 • 第11圖係為一剖面圖1100,其說明第三實施例之導橋 電阻隨機存取記憶體，包括回蝕刻第一與第二電極，以及 沈積一襯底介電層。第一與第二電極345,420a的回蝕刻， 可視其材料種類而定。在一實施例中，第一與第二電極 345,420a係使用氮化鈦。針對第一與第二電極345,420a中 的氮化鈦所進行的回蝕刻，可使用以Cl2為基礎之化合物 而進行乾式I虫刻。在另一實施例中，第一電極345包括氮 化鈦材料、而第二電極420a則包括鎢材料。氮化鈦材料與 鎢材料的回蝕刻，係藉由二步驟乾蝕刻製程而完成，其中 以Cl2為基礎之化合物係用以在第一蝕刻步驟中蝕刻氮化 17 1305044 鈦，而以SF6為基礎之化合物則係在第二蝕刻步驟中蝕刻 鎢材料。在回蝕刻之後，一襯底介電層111〇係沈積於剖^ 圖1100的整個上表面。此襯底介電層1110係設計為足 順形，而使得襯底介電層mo的沈積可允許在第：：極 345的回蝕刻之後，填入一介電填充物於一孔洞中。此 底介電層1110之材料，可從氮化矽或二氧化矽中選 底介電層1110的適當厚度係為約2〇Iim。 第12圖係為一剖面圖12〇〇，說明第三實施 橋電阻隨機存取記憶體，包括飯刻一介電側壁子，並形^ 圖中的襯底介電層1110，係被蝕刻以在 i形成一"電側壁子。此介電側壁子係位於第二雷 ί 5 i0 i之-1，’㈣餘的襯底介電層41 °則將第-電極 345與苐—電極42Ga分隔。在第—電極州中 ^ =以=3:5以被移除，但是襯底介電填充物⑴2 ϊίί在苐7電 上。介電側壁子1210可以被-以氟 。之内，並 向係垂直於-閘極或字元線。 ％ K万 導橋電阻隨m;!:圖^3: ’〒說明第三實施例中的 -例示路徑中流路徑_。在 接觸結構326、再流經第命I 、"丨L經汲極314、再流經 導橋5H)、再流經第、t = = 345、再流經電阻記憶材料 第14Α圖^ 。而抵達位元線122〇。 為基礎之記憶面:管=了管狀構件1_ 式化電阻材料51〇，而第丨 牛400係耦接至可程 明-具有第一與第二電^之管二冓糸：：正交剖面圖，其說 側壁，側壁則具有—内# 牛。g狀構件1400包括 百内表面345a與-外表面345b，其均 18 1305044 係為圓筒狀。第―電 與外表面345b之間。 5之厚度T係定義於内表面345a 以被理解為基本上為此，内表面345a與外表面345b可 沿著一固定直線移動，狀的表面，典型地定義為/平行 對於一圓柱而言此固a表面執跡並指一固定曲線相交，而 心）’而此固定曲線係1直線係位於管狀構件的中央（或車由 柱狀的内表面345a邀為以此固定直線為中心之圓形。此圓 半徑的圓圈（差異係/灸外〃表面345b，可以分別由具有不同 定義管狀構件之/内部^管狀構件的厚度）所代表，旅因而 中，圓柱狀形狀具^n、外部周緣。在管狀構件的實施例 周緣，端視用以^成=形、橢圓形、方形或不規則形的外 因此，此處所描了二構件時所使用的製造技術而定。 而是管狀構件的梅# 1衣形」上表面，並非必要為®形’ 第圖係々形狀。 隨機存取記憶體之例圖丨5〇〇,其說明製造一導橋電阻 周邊延伸形狀的第一 ^ 4造參數。環繞著接觸結構而具有 以分隔第一電極345二，345，其厚度係約為100埃。用 其厚度係約為1〇〇埃^第二電極420a的襯底介電層410， 420a的電阻記憶材^用以接觸第一電極345與第二電極 度係約為100埃\ ’導橋510的寬度係為約400埃’而厚 「環形」不僅句把q 無論其係為規則或f圓形，也包括其他周邊延伸形狀， 而定。 見則的周邊延伸形狀，端視製造私序 ，、π I p /7汰，謂·爹兄夹國哥π 11/155,067 號”Thin Film Fuse Phase Change Manufacturing Method”、申請日為 2005 年 6 月 Π 日’申 請人與本案相同，且該案係列入本案之參考。 雖然本發明係已參照較佳實施例來加以描述’將為吾 轉換&機存取記憶元件的額外製造資訊、元件 材料、使用、與操作方法，請參見美國專利中請案第 ，，τν>;” έ?:ι…RAM and 19 1305044 杳換方式及6改樣式係已於先前描述 ^ # 替換方式及修改樣式將為熟習此項技：之所 T是，根據本發明之結構與方法，所有具有 I 於 刷文本，均係列為U7;;，及之專利申請案以及印 【圖式簡單說明】 列第！圖係根據本發明綠示一雙穩態電阻隨機記憶體陣 方塊第圖2圖係根據本發明—實施例，繪示―積體電路之簡化 態4=康記實步施 第4 _根據本發„ —實齡i = 態電阻隨機存取記憶體之第二步mj 域、沈積-襯底介電層與—第二電極。’、χ、凹^區 第5圖係根據本發明第—實施例嘴示 ;電；隨機存取記憶體之第三步，其係研磨第Ϊ極雙J 積:電阻記憶材料、並圖案化。 茗弟一電極沈 第6圖係根據本發明第一實施例， 存取記憶體之第四步，其係沈; 電層了積厂金屬層間介電層、以及圖案化一：二底，| m ^ 圖係根據本發明第—實施例，繪示用以贺、土 一餹籍 ^•、電阻隨機存取記憶體之第乂製f雙t 電側壁子、—第二介電突Ϊ、與成—金屬層間介 20 1305044 存取第記根第據二本實發;!第二實施例’緣示一導橋電阻隨機 電層^圖案化剖面圖’其係沈積金屬層間介 第9圖係根據本發明第二實 第體之下-步驟，包括沈積位^ 橋電阻隨機存取記憶體之下一J 7二，導 硬遮罩於-電阻隨機記憶;料==面圖，包括沈積— 圖係根據本發明，示第三實_中之⑽當阳 阻:機】橋電 壁子、以及形成一位元線。 g括蝕刻介電側 第13圖係根據本發明，給一 _ 記憶體之剖面圖，其具有—^示電流橋電阻隨機存取 第14A圖係根據本發明，繪示一以^ 記憶細胞之實施例的剖面圖，此管狀电極為基礎之 式化電，材料；第14B圖係根據本發明極：耦接至一可程 電極為管狀構件之實施例的正交剖面圖。、、、曰不第一與第二 第15圖係根據本發明，繪示用以 存取記憶體之例示參數佈局。 、乂一導橋電阻隨機 【主要元件符號說明】 100 123,124 128 132,133 134,137 記憶陣列 字元線 共同源極線 底電極構件 頂電極構件 21 1305044 135 141,142 145 146 側壁腳位記憶細胞 位元線 Y軸解碼器及字元線驅動器 X軸解碼器及感測放大器 150,151,152,153 存取電晶體 200 積體電路 260 261 262 263 264 265 266 267 268 269 271 272 274 275 300 310 312,314,316 320,322 326,328 330 記憶陣列 列解碼器 字元線 行解碼器 位元線 匯流排 感測放大器及貢料輸入結構 匯流排 偏壓排列供應電壓 狀態機器 貢料輸入線 貨料輸出線 其他電路 積體電路 雙穩態電阻隨機存取記憶體 半導體基板 η型終端 多晶碎閘極 接觸結構 層間介電層 330a,330b,330c 介電填充 345,347 第一電極 345a 内表面 22 1305044 345b 410,412 420,420a,420b 510,520 610 620 630 632 710,712 720 810 820,822 910 1010 1110 1112 1210 1220 1310 1400 外表面 襯底介電層 第二電極 電阻記憶材料導橋 第二襯底介電層 金屬層間介電層 第一介層窗 第二介層窗 金屬層間側壁子 位元線 金屬層間介電層 介層窗 位元線 硬遮罩 襯底介電層 襯底介電填入物 介電侧壁子 位元線 例示電流路徑 管狀構件 23Ml 〇, 16 1305044 : , and the upper surface of the second electrode 420a are in the same plane. The resistive memory material is patterned by a lithography process to form a memory material via 510, wherein the length f of the resistive memory material via 51 is greater than the thickness of the substrate dielectric layer 41G. Similarly, the resistive memory material is patterned by a lithography process to form a resistive memory material bridge 52, wherein the length of the resistive memory material bridge 520 is greater than the thickness of the substrate dielectric layer 412. The resistive memory material via 51 is etched to allow the first electrode 345 to be connected to the second electrode 420a. The suitable shape of the resistive memory material guide 51 is square, but other shapes can be used. Resistive Memory Material Guide 51〇 • The preferred width is between 10 and 80 nm. A hard mask 1010 is deposited over the resistive memory material bridge 510. The hard mask 101 includes a dielectric material such as a dioxide dioxide. For the hard mask 1〇1〇 and the first and second electrodes 345, 420a, the etching step may be a single-step asymmetrical etching, or a two-step process, first etching a first etching compound The mask 1010 is followed by etching the first and second electrodes 345, 420a with a second etch compound. In one embodiment, the etch rate of the hard mask 1010 is much less than the etch rate of the second electrode 420a and the sidewalls of the first electrode 345 in the contact structure 326. A suitable etching method is dry etching using a Cl2-based compound. • Figure 11 is a cross-sectional view 1100 illustrating a via-resistive random access memory of a third embodiment including etching back the first and second electrodes and depositing a substrate dielectric layer. The etch back of the first and second electrodes 345, 420a may depend on the type of material. In one embodiment, the first and second electrodes 345, 420a use titanium nitride. For the etch back of the titanium nitride in the first and second electrodes 345, 420a, a dry-type I-etch can be performed using a Cl2-based compound. In another embodiment, the first electrode 345 comprises a titanium nitride material and the second electrode 420a comprises a tungsten material. The etch back of the titanium nitride material and the tungsten material is completed by a two-step dry etching process, wherein the Cl2-based compound is used to etch nitride 17 1305044 titanium in the first etching step, and based on SF6. The compound etches the tungsten material in a second etching step. After etch back, a substrate dielectric layer 111 is deposited on the entire upper surface of the cross-sectional view 1100. The substrate dielectric layer 1110 is designed to be conformal, such that deposition of the dielectric layer mo of the substrate allows a dielectric fill to be filled into a hole after etch back of the :: electrode 345. The material of the bottom dielectric layer 1110 may be selected from tantalum nitride or ruthenium dioxide to have a suitable thickness of about 2 〇Iim. Figure 12 is a cross-sectional view showing the third embodiment of the bridge resistor random access memory, including a dielectric dielectric sidewall, and the substrate dielectric layer 1110 is etched to Form an "electric wall" in i. The dielectric sidewall sub-system is located at -1 of the second ray, and the substrate dielectric layer 41 of the remaining (4) separates the first electrode 345 from the 苐-electrode 42Ga. In the first electrode state ^ = with =3:5 to be removed, but the substrate dielectric filler (1)2 ϊίί is on 苐7. Dielectric sidewall 1210 can be -doped with fluorine. Within the direction, the system is perpendicular to the - gate or word line. % K 导 Bridge resistance with m;!: Figure ^3: ' 〒 〒 第三 第三 第三 第三 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例In contact structure 326, then flow through the first life I, "丨L through the drain 314, then through the guide bridge 5H), then through the first, t = = 345, and then through the resistance memory material. And arrived at the bit line 122〇. Based on the memory surface: tube = tubular member 1_type resistive material 51〇, and the first yak 400 series coupled to the programmable - first and second electric tube two:: orthogonal section Figure, which says the side wall, the side wall has - inner #牛. The g-shaped member 1400 includes a hundred inner surface 345a and an outer surface 345b, each of which is 18 1305044 in a cylindrical shape. Between the first and the outer surface 345b. The thickness T of 5 is defined on the inner surface 345a to be understood to be substantially for this purpose, the inner surface 345a and the outer surface 345b are movable along a fixed straight line, a surface that is typically defined as/parallel for a cylinder. The solid a surface is obscured and refers to a fixed curve intersecting, and the center of the fixed curve 1 is located in the center of the tubular member (or the car is invited by the cylindrical inner surface 345a to be a circle centered on the fixed straight line) The circle of the radius of the circle (the difference system / moxibustion outer surface 345b, which can be respectively represented by the thickness of the inner tubular member having differently defined tubular members), and the cylindrical shape have the outer circumference. In the periphery of the embodiment of the tubular member, the end view is used for the shape of the shape, the ellipse, the square or the irregular shape, and thus the manufacturing technique used for the two members is described herein. The upper surface of the #1 clothing shape is not necessarily the shape of the 'shaped shape'. The example of the random access memory is shown in Fig. 5, which shows the first parameter of the shape of the extension of the perimeter of the bridge resistor. Surrounding the contact structure The resistors are used to separate the first electrodes 345, 345, and have a thickness of about 100 angstroms. The dielectric memory layers 410, 420a of the second electrode 420a having a thickness of about 1 Å are used. Contacting the first electrode 345 with the second electrode is about 100 angstroms. The width of the via 510 is about 400 angstroms and the thickness "ring" is not only the sentence q, but it is also regular or f-circular, and includes other The shape of the perimeter extends, but the shape of the perimeter extension is seen, and the private order is made by the end, π I p /7, 谓 爹 夹 夹 π π π 11/155, 067 "Thin Film Fuse Phase Change Manufacturing Method", The application date is June 2, 2005, and the applicant is the same as the present case, and the case series is incorporated by reference. Although the present invention has been described with reference to the preferred embodiments, the present invention will be described as a <RTIgt; For additional manufacturing information, component materials, use, and method of operation, see US Patent Application, τν>; έ?:ι...RAM and 19 1305044 杳换方式和6改式系系 has been previously described ^ #换方式 and modify the style will be familiar with this technique T is the structure and method according to the present invention, all having I in the brush text, the series is U7;;, and the patent application and the printing [simplified description] column! The figure is green according to the present invention. FIG. 2 shows a simplified state of an integrated circuit according to the present invention—an embodiment of the present invention. The second step mj domain of the state resistance random access memory, the deposition-substrate dielectric layer and the second electrode. The fifth diagram of the ', χ, and concave regions is according to the first embodiment of the present invention; The third step of random access memory is to grind the first dipole double J product: resistive memory material and pattern. According to a first embodiment of the present invention, the fourth step of accessing the memory is sinking; the electrical layer is formed by a dielectric layer between the metal layers of the factory, and the patterned one: two bottoms, | According to the first embodiment of the present invention, the m ^ figure is a second double dielectric wall, a second dielectric protrusion, which is used for the He, the earth, and the resistance random access memory. Interacting with the metal-metal layer 20 1305044 accessing the second root data; the second embodiment 'the edge of a guide bridge resistance random electric layer ^ patterning sectional view' According to the second sub-body of the present invention, the steps include: deposition of a bridge resistance under random access memory, a J 7 II, hard masking-resistance random memory; material == surface pattern, including deposition - The figure is in accordance with the present invention, showing the third real (10) when the male resistance: machine] bridge electric wall, and forming a one-dimensional line. Figure 13 is a cross-sectional view of a memory having a current bridge resistance random access method according to the present invention. Figure 14A shows a memory cell according to the present invention. A cross-sectional view of an embodiment, the tubular electrode is a structured electric material, and a 14B is a cross-sectional view of an embodiment of the present invention coupled to a tubular member as a tubular member. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,乂 导 导 电阻 电阻 【 【 【 电阻 电阻 电阻 电阻 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 And word line driver X-axis decoder and sense amplifier 150, 151, 152, 153 access transistor 200 integrated circuit 260 261 262 263 264 265 266 267 268 269 271 272 274 275 300 310 312, 314, 316 320, 322 326, 328 330 Memory array column decoder character Line line decoder bit line bus bar sense amplifier and tribute input structure bus bar bias arrangement supply voltage state machine tribute input line cargo output line other circuit integrated circuit bistable resistance random access memory semiconductor substrate N-type terminal polycrystalline gate contact structure interlayer dielectric layer 330a, 330b, 330c dielectric fill 345, 347 first electrode 345a inner surface 22 1305044 345b 410, 412 420 420a, 420b 510, 520 610 620 630 632 710, 712 720 810 820, 822 910 1010 1110 1112 1210 1220 1310 1400 outer surface substrate dielectric layer second electrode resistance Material guide bridge second substrate dielectric layer metal interlayer dielectric layer first via window second via window metal interlayer sidewall sub-bit line metal interlayer dielectric layer via window bit line hard mask substrate dielectric Layer substrate dielectric fill dielectric sidewall sub-bit line exemplifies current path tubular member 23