TWI334212B - Lead frame with included passive devices - Google Patents
Lead frame with included passive devices Download PDFInfo
- Publication number
- TWI334212B TWI334212B TW093104345A TW93104345A TWI334212B TW I334212 B TWI334212 B TW I334212B TW 093104345 A TW093104345 A TW 093104345A TW 93104345 A TW93104345 A TW 93104345A TW I334212 B TWI334212 B TW I334212B
- Authority
- TW
- Taiwan
- Prior art keywords
- package
- semiconductor device
- pins
- lead frame
- interposers
- Prior art date
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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1334212 九、發明說明: 【發明所屬之技術領域】 本發明通常關於半導體裝置裝,尤i i衣兀具’關於裝置包括至 少一被動裝置之導線架之半導體裝置封裝。 【先前技術】 於-慣用之半導體裝置封裝中,一外殼包裝該半導體裝 置(晶片以防止該晶片暴露於環境之風險。可以使用塑膠 密封、包裝該外殼,或其他不受環境影響之方法。 於裝置導線架之半導體裝置封裝中,藉由—電傳導導線 架,傳輸至少一晶片與外部電路之間之電信號,例如一印 刷電路板。該導線架包括一些引腳,各自具有一内引腳末 端與-相對之外引腳末端。該内引腳末端電連接至該晶片 之一輪人/輪出⑽)墊,而該外⑽末端是該封裝主體之外 π接頭。該外⑽末端在該封裝主體之表面終止,該封裝 為已知的”無5丨腳,,封裝,而如果該等外引腳擴充超出該‘ 裝主體周圍,則該封裝稱為"引聊”封裝。已知之,,無引卿,, 封裝之範例包括四邊爲平無引腳(QFN)封裝,有四組引聊淨 繞一正方形封裝主體之底部周圍暴露,以及雙邊扁平^ =N)封裝,有二組引腳沿著一封裝主體之底部之兩相對 邊暴露。-種用於製造裝置導線架之封裝之方法,揭露於 共同所有之美國專利申請序號⑽34,882,於2〇〇2年4月29 日提出申請,於此全部以引用的方式併入本文中。 夕電子組裝中’被動組件,例如,電容器、感應 及電阻器料導體裝置封裝互連1提供料望之功能。 9i449.doc 丄州4212 ^ ^仍不以有成本效盈之方法,將大部分被動組件整 合於一已包裝之晶片封裝。 希望以製造者與使用者之觀點來看,該電子組裝需要的 外部連接越少越好,因為此類連接會增加製造成本(最終會 轉給該使用者)’而且當由外部組件傳輸信號時,會對該封 裝產生干擾。 因此,本發明實現改善半導體裝置封裝之需要,包括一 有成本效益之方法,以放置被動組件接近一晶片,而且包 裝該等被動.組件與晶片於單一封裝。 【發明内容】 以一種半導體裝置封裝克服或減輕先前技藝在上面所描 述及其他缺點與缺陷,該半導體裝置封裝包括:一封裝主 體;一置於該封裝主體之半導體裝置;至少一置於該封裝 主體之被動裝置;以及由電傳導材料所形成之導線架。該 導線架包括複數個引腳電連接該半導體裝置之1/〇墊,一從 該封裝主體暴露之第一表面,複數個電連接該至少一被動 裝置之第一内插器。該至少一被動裝置選自包含電晶體、 感應器器與電阻器之群組。藉由一模封材料封裝該半導體 晶片至少一部分,該至少一被動裝置至少一部分,以及該 導線架至少一部分,以形成該封裝主體。該等引腳可被暴 露且幾乎完全與該封裝主體之一表面共面。 該半導體裝置之該等I/O墊可與該複數個引腳線銲或膠 黏合。於一實施例中,該導線架進一步包括一晶片墊,該 半導體裝置牢牢固定在該晶片墊。於另一實施例中,該半 9l449.doc 山 4212 =裝置之-料從該封裝主體暴露1 體裝置之該等1/0墊與該導線架之接合座焊接,與該等!: 固二腳接合’以形成—覆晶接合。支撑桿可放在該等:― 和/或第二内插器之該等接合座下面 封裝主體之表面。 寻文保彳干暴路在該 於另一觀點中,一半练髀姑 +導體裝置封裝包括:一形成 部分第一封裝表面之模封姑粗· >成至V — 蓋至少-被動”. 模封材料至少部分覆 u該㈣材料至少部分覆i _半導
裝置,該-半導體裝£包括複數個J 邻八F φ # ,s 蛩以及以該杈封材料 。刀I 傳導材料所形成之導線架。該導線架包括. 複數個引腳與複數個電連接至少_被動裝置之第—内插 益’該複數個引腳各自具有一形成_接合座,且電連接至 該複教個I/O墊之至少一 1/〇墊 °墊之第一表面,以及-暴露在該 第一封裝表面之第二表面。該複數個第—内插器各自呈有 -與該複數個引腳之第一表面共面之第三表面,而且該複 數個第-内插器之每一個第一内插器至少一部分該第一封 裝表面間隔開。 而於另一觀點中,一種形成半導體裝置封裝之方法包 括:由-電料材料形成—導線架,包括:以該電傳導材 料形成複數個引腳與複數個第一内插器,以及蝕刻該複數 個引腳與該複數個第一内插器之底面,該蝕刻在該等接觸 器上界定複數個第一表面,電連接一半導體裝置之I/O墊至 該複數個引腳;通過該複數個第一内插器之成對第一内插 器電連接至少一被動裝置;以及以模封材料覆蓋該導線 91449.doc 1334212 架、料導體裝置與該至少一被動裝置之每一㈤至少—部 分。該模封材料形成第一封裝表面至少一部分。每―,丨腳 之第-表面暴露在該第一封裝表面,而且每一第一内插器 至少一部分與該第一封裝表面間隔開。 該半導體裝置之該等I/Q墊可與該複數個㈣線銲或膠 黏合。形成該導線架進—步可包括由該電傳導材料形成一 晶片塾,於該實施例中’該方法進一步包括將該半導體裝 置牛牢固定在該晶片墊。於另—實施例中,該半導體裝置 之-部分暴露在該第-封裝表面。而於另一實施例中,電 連接該半導體裝置之該等1/0墊與該複數㈣腳,其包括= 接該等I/O塾與該導線架之接合座,以形成―覆晶接合。於 該實施例中,形成該導線架進—步可包括形成複數個連接 該複數個引腳之第二内插器’該等接合座形成於該等第二 内插器。同樣於該實施例中,該蝕刻可界定放在該等第二 内插器之接合座下面之支撐桿’以該模封材料覆蓋之後, 該支撐桿暴露在該第一封裝面。 於該方法中,該蝕刻可進一步界定一從該複數個第一内 插器之至少-第-内插器擴充之支撐桿,以該模封材料覆 蓋之後,該支撐桿暴露在該第一封裝面。以該模封材料覆 蓋之前’該支撐桿與每一引腳之第—表面黏著在一表面。 於下面之該等附加圖示與描述提到本發明之一或更多實 施例之詳述。由該描述與圖示,以及該申請專利範圍可瞭 解本發明之其他特性、目的與優點。 【實施方式】 91449.doc •9-
Ill =Γ:Γί置14電連接至-共用之導_。該 暮、 卩Μ刻金屬結構所形成,並包括複數個傳 導引腳16與複數個内插器20。該被動裝置14可包括電連1 該内插器20之電容器,誘導$ C括電連接 ^ ^ ^ ^ * 電1^^,或任何其他此類 動電子裝置。於該顯示實施例中,在該晶片12之⑻墊22 由金屬線26電連接形成在該等引㈣之接合然而, 會在下面進—步詳細描述,使用其他的方法電連接該1/0塾 22與該接合座24。再者’於所顯示之實施例中,該導線架 17包括一晶片支撐墊54,該晶— ' 乂日日月12固疋在其上。以模封材 料28封裝該晶片12,被動裝置14,金屬線^與導線㈣, 以形成具有分別為頂面、底面與側面(表面)32, 34與36之封 裝主體30。該等引腳16之底面38暴露在該封裝ι〇之底面^, 而且可電連接一外部電路,例如一印刷電路板,或諸如此類。 圖2顯示該導線架17在該半導體裝置封裝製程之單切步 驟刖之上視圖。圖3是圖2之該導線架17之下視圖,而圖4 疋該導線架17在圖3之4-4部分之側視圖。參考圖2,一些導 ’線架16彳由外部框架50互相連接,以使多封裝1〇之製造容 » 1 \ 易°於單切步驟期間,該模封材料28(圖1)被應用之後,通 >常會執行沿著線52切割該等導線架丨6,以移動該外部框架 50 ’並分開該等個別之導線架16。 * · j 於圖2-4所顯示之導線架17中,四引腳丨6被配置在一晶片 支樓墊(晶片墊)54之兩面對面的邊上,擴充該晶片墊54之每 一個角的是一繫桿56,其作用是固定位於該模封材料28(圖 9l449.doc •10· 1334212 1)之晶片墊54。該内插器20配置於該兩繫桿56之間所形成 之空間。於該實施例中,顯示該導線架丨7包括兩普通L_型 内插器20,與一配置在該兩普通l-型内插器2〇之間之普通 T-型内插器20。應瞭解可隨著被動裝置14(圖1}類型之需 要,改變該等内插器20之數量與配置。此外,應瞭解可隨 著特定應用之需要,修改該等引腳16之數量、配置與位置。 例如,雖然顯示該等引腳16被放置在接近該封裝之底面 34的周圍,但另一選擇是可將該等引腳16放置在該底面% 之其他位置.。在單切製程之後,該等引腳16與内插器2〇互 相間隔開’並與該晶片塾54間隔開,因此該等引腳^與内 插器20互相電絕緣,也與該晶片墊54電絕緣。 如圖3與4所顯示,擴充各個普通乙_型内插器“之底部的 是-支撐桿58,有-底面6()與該等引腳16之底面38及該晶 片墊54之底面62共面…凸出部咐置在料繫桿%之 包括由此擴充之識別桿66,其底部與該等引腳 晶片墊54及支撐桿58之底面共面。 由任何適合之電傳導材料薄片形成該導線架”,最好是 銅或以銅為主之合金。關於以銅為主之合金,意指該材料 就重ϊ來說包含超過鳩的銅。形成該導線架17之傳導材 料薄片之厚度是標示於圖4之丁丨 取好疋介於大約0.01 mm 至大約0.25 mm,而最理想是介於 、八约ϋ.15 mm至大約〇 2〇 mm。使用任何已知之方法 ’ , 之方法例如’壓印,化學蝕刻,雷射 嫁削,或諸如此類,开;? $ #道& Λ ^ 以料_17之祕之前導, 晶片塾54、該等㈣16、内插器2〇與繫桿561導 9I449.doc 1334212 線架17包括一減少厚卢 岡心 取力子度之£域’於圖3以交叉排線表示,於 二:Γ::2。可使用一控制_製程,例如,化學㈣或 W減少該材料之厚度’以形成減少厚度之區域。例 ^可使用—化學抗㈣塗佈,以分別形成該等引腳16, 支撐桿58及晶片墊54之麻而3 塋4之底面38 ’ 60與62之每一表面,而未 ιΐ=:暴露於一適合之钮刻劑一段有效時間,以移除 =料’而達到厚度Τ2β該厚度Τ2最好介於該導線架 之厚度Ti之大約25%至大約6〇%(即, 17之材料厚度),而最 成m 取里•。疋"於該厚度之大約40%至大約 位於該最佳範圍内之厚度提料夠的^,但低於 ^八厚度部分,以接受該模封材料,以使該導線㈣ 固疋於該封裝10。 形成該導線架17之各種特徵之後,該等支擇桿58、該 f引腳16與該晶片墊54之底面黏著在表面_,如圖5所顯 不於該實施例中,該表面1〇〇被形成在—膠布上 固、定幾乎完全共面之表祕,38與62,而表面6g,3_2 刀別形成該等支撐桿58、該等引腳16與該晶片墊54之底 面。雖然圖5顯示單—導線架17,應瞭解可提供如圖2旬 所顯示之複數個互連之導線架16。 /、 由於該導線架Π黏著在該表面1〇〇,接著該等被動裝置μ 可電連接該導線架17。於該實施例中,顯示每一被動裝置 從一内插器2〇擴充至另-個,該等内插器2G之間有_:間 k例如’兩被動裝置14電連接在兩普通L-型内插器20與 曰通T-型内插器20之間,而一被動裝置"電連接在兩普 9l449.doc 12 ⑴ 4212 通L-型内插器20之間。可使用任何便利之方法例如焊 接:導電膠或環氧化物,或諸如此類,使該等被動裝置Μ 附者在該等内插!I 2 〇。有利於設計可使用任何數量或不同 類型之内插器2〇之導線架17。 圖6疋金屬線26接合晶片12之1/〇墊22,該等引腳μ之接 合座24與該等内插器2〇之接合座1〇4後,該導線架η之上視 圖。銲線之前,使用任何便利的方法,將該晶片12固定在 該晶片墊54,例如,焊料’環氧化物,雙面膠布,料。該 日曰片12固定在該晶片墊54之後,金屬線%分別連接在該晶 片12之I/O墊22與各自之引腳16之接合座以之間,並在該等 内插器20之接合座1〇4與一或更多引腳“之接合座μ之 間。支撐桿58被放置在該等内插器2〇之接合座1〇4下面以 維持.該等接合座1G4與該等共面,使㈣金屬線% 準確接合,因而,減少該封裝1〇之製造缺點。此外,該等 支撐桿58傳輸與該等金屬線%之接合相關之影響給該表面 1 〇〇(圖5),因此,能夠使用多種銲線方法。例如,該銲線可 由下列執行:使用超音波接合,其應用壓力與超音波振動 迸裂之組合,以形成一冶金冷卻焊接;使用熱壓接合,其 應用壓力與升高溫度之組合,以形成一焊點;或使用熱超 曰波接σ,其應用壓力、升高溫度與超音波振動迸裂之組 口’以形成一焊點。用於該接合之金屬線之類型最好是由 金,以金為主之合金,鋁,或以鋁為主之合金所形成《可 使用捲帶式自動接合(TAB)替代銲線。 在該等金屬線26被接合之後,以該模封材料28覆蓋該晶 9l449.doc •13- 1334212 片12、導線架17、被動裝置14與金屬線%,如圖1與7所顯 示的。可使用任何便利之技術,應用該模封材料28,例如, 轉左或/主入製模處理。該模封材料2 8是一種電絕緣材料, 最好是聚合物成形樹脂,例如,環氧化物,具有一回流溫 度,該溫度範圍大約25(TC至大約3〇(rc。該模封材料 可以是一低溫熱玻璃合成物。 於該模封材料28之應用期間,支撐桿58、引腳16與晶片 墊54各自之底面60、38與62,保持黏著在該表面ι〇〇(圖”, 以,該導線架17移動,因而,幫忙確保該銲線不是亂的 或知壞的。此外,形成在該導線架17之減少厚度部分下面 的空間,以接受該模封材料28’而且用於將該等内插器2〇、 引腳16與晶片墊54固定於封裝1〇。 在應用該模封材料28之後,該黏附面1G0(圖5)被移除, 而且如果需要’以衝壓,或具有刀片的鋸子,水噴,雷射, 或諸如此類,切單該附著之封裝…圖以該封裝ι〇在切單 後之代表上視圖,而且圖8是該封裝1()在切單後之下視圖。 參考圖7與8’移除該黏附面⑽(圖5)與切單之後,暴露每一 封裝10之導、㈣17之—料。尤其mi㈣之-部分, 該等内插1120之-部分,以及該等繫桿56之—部分被暴露 在該1裝ίο之側面36。如圖8所顯示,該晶片塾54,引腳16, 支撐#58,與識別桿66之底面被暴露在該封裝之底面μ。 於該實施例中,顯示每-引腳16暴露在該側_之部分 …、m之底面38由;^封材料28隔開’形成封裝之整個 底邊。另一選擇,可配置-或更多之引腳16,使該引腳16 9l449.doc 14 1334212 暴露在該側面36之部分與該引腳16之底面38在該封裝1〇之 底邊連接。於該實施例中,一或更多之引腳16形成該封裝 ίο之部分底邊。於一典型配置中,只有該引腳16之底面38 被用於連接一外部電路。然而,如果需要,該支撐桿58之 底面60也可以連接一外部電路。 參考圖9-11 ’顯示用於該封裝10之替代導線架120。該導 線架1 20大體上與圖2_4所顯示之導線架1 7類似,除了配置 該導線架120具有内插器122之外,使用覆晶方法電連接在 該晶片12與引腳16之間。換言之,該晶片12被覆蓋,使該 I/O墊22面朝下,而且該1/〇墊22以焊接或類似之方法,直接 電連接形成在該等内插器丨22表面之接合座124。該導線架 120也可隨意包括在該等普通L_型内插器2〇與一或更多之 引腳-16之間擴充之内插器126。支揮桿128形成在該等内插 器122之接合座124下面,以在該焊接與封裝處理期間,支 撐該等接合座124。 因為於該封裝10中,該等内插器122支撐晶片12,所以額 外的内插器122可排除圖2-4所需要之晶片墊54。此外,額 外的内插器122與126排除上述之線銲或膠黏合步驟。除此 之外,使用該導線架120製造該封裝1〇大體上與上述類似, 所產生之封裝10具有一底面34,如圖12所顯示。 如圖12所顯示,該等引腳16 '支撐桿“與支撐桿us之底 面暴露在該封裝10之底面34。於一並刑斯里丄 ' 一 !配置中,只有該等 引腳16之底面38被用於連接一外部雷拉。 ^ 热而,如果需要, 該等支撺桿58和/或128之底面38也可連接—紅 ’ 外部電路。該 9I449.doc 15 1334212 等支樓杯58之底面60被用於連接一外部電路,該導線架120 排除5亥等引腳16與内插器122。於該案例中,該等支撐桿128 作為該封裝1 0之引腳。隨著於此所描述之該等實施例,應 瞭解特疋應用有需要時’可修改該等引腳16之數量、配置 與位置°例如,雖然顯示該等引腳16被放置在接近該封裝 10之底面34的周圍’但另一選擇是該等引腳16可被放置在 該底面34之其他位置。 參考圖13-15,顯示另一使用於該封裝1〇之替代導線架 b〇。該導線架150大體上與圖2_4所顯示之導線架17類似, 除了該導線架13〇不包括一晶片墊54之外。於該配置中,於 線鲜與封裝處理期間’由該表面1〇〇(圖5)支撐該晶片12。除 此之外,使用該導線架15〇製造該封裝1〇大體上與上面所描 述的顧似,所產生之封裝1〇具有一底面34,如圖16所顯示。 該晶片12之底面、弓丨腳16與支撐桿“暴露在該封裝1〇之底 面34。 於此所描述之該等實施例中,放置該等被動裝置1 4緊密 接近該晶片12 ’所生產之封裝1〇的全部大小比慣用之多組 件晶片封裝小。本發明利用該發明創造之配置,示範此等 組件之間㈣速之電連接’雖然該等組件之間的外部引腳 較少且金屬線長度較短^該封裝可被用作―投人取代雙面 無引腳組裝’例如’小外型積體電路(s〇ic),超薄小型緊 縮封裝(TSS〇P)’四分之-號小型封裝(QSOP),等等。” 雖然已經以最佳實施例描述說明本發明 技藝者所瞭解的 但如熟悉此項 不需違背本發明之精神與範圍,即可進 91449.doc 1334212 行許夕的變化與修改。經由示範,應能瞭解於本發明之範 圍内,可利用替代之封裝配置。各種的修改包括,例如, 曰曰片女裝和/或線銲前或後之電鍍應用。 因此’本發明之講授並不受限於任何特定半導體晶片封 置例如上面詳細描述之該等配置。因此,本發明於 該附加申請專利範圍所提到,並不受限於上面所提出之明 確描述之架構,例如,熟悉此項技藝者應瞭解,其他的變 化與修改必須包括於本發明所定義之申請專利範圍内提出 之精神與範.圍。 【圖式簡單說明】 由上面結合該等附加圖示之詳細描述,可更加瞭解本發 明’其中以相同之號碼標示相同之元件,其中: 圖1是根據本發明之一實施例,裝置一導線架且包括被動 裝置之半導體裝置封裝之透視部分剖面圖; 圖2是圖1之該裝置之導線架之上視圖; 圖3是圖2之導線架之下視圖; 圖4是該導線架在圖3沿著4_4部分之側視圖; 圖5是有被動裝置與其連接之圖2之導線架之透視圖; 圖6是有一晶片及被動裝置與其連接之圖2之導線架之上 視圖; 圖7是裝置導線架之半導體裝置封裝,在單切後之上透視 图 , 圖8是裝置導線架之半導體裝置封裝,在單切後之下視 園, 91449.doc 1334212 圖9是裝置在半導體裝置封裝之導線架之一替代導線架 之上視圖; 圖10是圖9之替代導線架之下視圖; 圖Π是圖9之替代導線架在圖1 〇沿著1丨_丨丨部分之側視 圖, 圖12是包括圖9之替代導線架之半導體裝置封裝之下視 園, 圖13是裝置在半導體裝置封裝之導線架之另一替代導線 架之上視圖…; 圖14是圖13之替代導線架之下視圖; 圖1 5是圖1 3之替代導線架在圖1 4沿著1 5 _ 1 5部分之側視 Γξΐ · 園, 圖16是包括圖13之替代導線架之半導體裝置封裝之下視 圖。 【主要元件符號說明】 10 半導體封裝 14 被動裝置 12 半導體裝置 16 傳導引腳 17、 120 ' 150 導線架 20、 122、 126 内插器 22 I/O墊 24 ' 104、 124 接合座 26 金屬線 9l449.doc •18· 1334212 28 模封材料 30 封裝主體 32 頂面 34 封裝底面 36 側面 38 ' 引腳底面 50 外部框架 52 線 54 晶片支撐墊 56 繫桿 58 、 128 支撐桿 60 支撐桿底面 62 晶片墊底面 64 凸出部 66 識別桿 100 表面 ΤΙ 傳導材料薄片之厚度 Τ2 減少厚度之區域 9l449.doc - 19-
Claims (1)
- 丄 第093104345號專利申請案 中文申凊專利範圍替換本(99年7月) 十、申請專利範圍: 種包連接夕卜部電路之半導體裝置封裝(⑺),該半導體 裝置封裝(10)包括: 一封裝主體(30); —配置於該封裝主體(3〇)之半導體裝置(12); 至乂配置於5亥封裝主體(30)之被動裝置(14);及 一由電傳導材料所形成之導線架(17),該導線架(17)包 括: 複數個電連接该半導體裝置(12)之Κ㈣(U)之引腳 ^ 引腳(16)之每-個包括-從該封裝主體(30)暴 露,以電連接該外部電路之第一表面(38),及 一被動裝置(14)之第一内插器 複數個電連接至少 内插器(20)電連接該 以電連接該至少一被 (20),該複數個内插器(2〇)中至少一 複數引腳(16)中之至少一引腳(16), 動裝置(14)與該外部電路。 2.如申請專利範圍第!項之半導體裝置封裝⑽,其中由封 裝該半導體裝置(12)至少一部分、該被動裝置⑽至少— 部分以及該導線架(17)至少一部分之模封材料(28),以形 成該封裝主體(30)。 3.如申請專利範圍第2項之半導體裝置封裝⑽),其令該等 弓/腳(16)之該等第—表面(38)被暴露,且幾乎完全與該封 裝主體(30)之一表面(34)共面。 4.如申請專利範圍第丨項之半導體裝置封裝(1〇),其中嗦至 少一被動裝置〇4)係選自包含電晶體、感應器與電阻器 93449-9907J5.doc 1334212 群組 ff? /5 5. 如申請專利範圍第1項之半導體裝置封裝⑽,兑中今導 線架(17)進一步句妊 a μ .. · 八r孩導 )進/ L括—日曰片墊(54),該半導 牢固定在該晶片墊(54)。 ( 2)牛 6 · 7. =:利範圍第,項之半導體裝置封裝⑽,其中該半 導體裝置(12)之一部分從該封褒主體(30)暴露。 圍第1項之半導體裝置封裝⑽,其中將該 丰導體裝置⑽之該等1/〇塾(22)谭接在該導線架⑼之 接合座(124),以形成一覆晶接合。 8. 如申請專利範圍第7項之半導體裝置封裝〇〇),㈠ 在第二内插器〇22)之該接合座⑽),連接至該複數個引 腳(16)。 w 9. 如申請專利範圍第8項之半導體装置封褒⑽,盆卜亥等 第二内插器⑽)各自包括一放在該接合座(124)下面之 支轉桿(叫,該切桿⑽)暴露在該封裝主體之一 表面(34)。 10·如申請專利範圍第8項之半導體裝置封裝(1〇),其中該複 數個内插器(20)之至少一内插器(2〇),由至少一第三内插 器(126)電連接該複數個引聊(16)之至少—引腳⑽。 11. 如申請專利範圍第!項之半導體裝置封裝⑽,其中該半 導體裝置(12)之該等1/0塾(22)與該複數個引腳(16)線銲 或膝黏合。 12. 如申請專利範圍第!項之半導體襄置封裝⑽,其中該等 第-内插器(20)至少之一第一内插器(2〇)包括一由此擴 9l449-990715.doc 1334212 充之支撐桿(58), 一表面(34)。該支撐桿(58)暴露在該封裝主體(1〇)之 13· —種半導體裝置封裝(1〇),其包括·· 一形成至少一部分第一封裝表面(34)之模封材料(28); 以該模封材料(28)至少部分覆蓋至少一被動裝置(34); 以該模封材料(28)至少部分覆蓋一半導體裝置(12),該 半導體裝置(12)包括複數個1/0墊(22);及 以該模封材料(28)部分覆蓋由一電傳導材料所形成之 導線架(17),該導線架(17)包括: 複數個引腳(16),各自具有一形成一接合座之第一表 面,電連接至該複數個1/0墊(22)之至少一 1/〇墊(22),與 一暴露在該第一封裝表面(34)之第二表面Ο”,及 複數個電連接至少一被動裝置(14)之第一内插器 ㈣,該複數個第一内插器(2〇)各自具有一與該複數個引 腳(16)之帛纟面共面之第三表面,該複數個第—内插器 (2〇)之每-個第—内插器㈣至少—部分與該第一封裝 表面(34)間隔開。 14_如申請專利範圍第13項之半導體裝置封|(1()),其中該至 v被動裝置(14)係選自包含電晶體、感應器與電阻器之 群組。 15.如㈣專利範圍第13項之半導體裝置封裝⑽,其中該導 線架〇7)進一步包括-晶片塾(54),該半導體裝置(12)牢 牢固定在該晶片墊(54)。 16·如申請專利範圍第13項之半導體裝置封裝⑽,其中該半 91449-990715.doc 導體裝置(12)之-部分從該第一封装ϋ3—4)暴露 1 了.如申請專利範圍第π項之半導體裝置封褒⑽,其中該半 導體裝置(12)之該等1/0塾(22)與該導線架(17)之接合座 (124)焊接,以形成一覆晶接合。 18.如_請專利範圍第17項之半導體裝置封裝⑽其中形成 在第一内插器(122)之該接合座(12句連接該複數個引腳 (16)。 19·如申請專利範圍第18項之半導體裝置封裝⑽其中該等 第一内插盗(122)各自包括一放在該接合座(124)下面之 支撐桿(128),該支禮桿(128)暴露在該第一封裝表面⑽。 20.如申請專利範圍第13項之半導體農置封裝⑽,其中該複 數個内插器(2〇)之至少-内插器⑽,包括-由此擴充之 支撐桿⑽’該支樓桿(58)暴露在該第一封裝表面(Μ)。 儿如^請專利範圍第13項之半導體裝置封裝⑽,其中該半 導體裝置(12)之該等1/〇墊(22)與該複數個引腳(】◦線銲 或勝黏合。 22·如中請專利範圍第13項之半導體裝置封裝⑽,其中該複 數個引腳(16)之至少_引腳(16)電連接該複數個第一内 插器(2〇)之至少一第-内插器(20)。 23. -種用於形成—半導體裝置封裝⑽之方法,該方法包 括: 由電傳導材料形成-導線架(1 7),包括: 以°玄電傳導材料形成複數個引腳(16)與複數個第一 内插器(20),及 91449-990715.doc 1334212钱刻 之底面, (38); 該複數個引腳(16)與該複數個第一内插器(2 〇) 該蝕刻在該等引腳(16)界定複數個 第一表面 :連接—半導體裝置(12)之㈤塾(22)與該複數個引腳 通過該複數個第一内插器(20)之成對第 電連接至少一被動裝置(14);及 以模封材料(28)覆蓋該導線架(17)、該半導體裝置(12 ㈣至少一被動裝置(14)之每—個至少一部>,該模封材 料(28)形成-第—封裝表面(34)至少__部分,#中每一引 腳(16)之該第-表面(38)暴露在該第一封裝表面句而 且每一第一内插器(20)至少一部分與該第一封裝表面(34) 間隔開。 24·如申請專利範圍第23項之方法,其中該至少一被動裝置 (14)係選自包含電晶體、感應器與電阻器之群組。 25.如中請專利範圍第23項之方法,其中形成該導線架⑼ 進一步包括由該電傳導材料形成一晶片墊(54),而且該方 法進一步包括: 使該半導體裝置(1 2)牢牢固定在該晶片墊(54)。 26.如申請專利範圍第23項之方法,其中該半導體裝置 之一部分暴露在該第一封裝表面(34)。 27·如申請專利範圍第23項之方法,其中電連接該半導體裝 置(12)之該等I/O墊(22)與該複數個引腳(16),包括: 焊接該等I/O墊(22)與該導線架(17)之接合座(124),以 91449-990715.doc 形成一覆晶接合。 28. 如申請專利範圍第27項之方法,其中形成該導線架(17) 進步包括形成複數個連接該複數個引腳(丨6)之第二内 插器(m) ’在該等第二内插器(122)上形成該等接合座 (124)。 29. 如申請專利範圍第28項之方法,其中該蝕刻進一步包括 界疋放在忒等第二内插器(122)之接合座(124)下面之支 樓桿(128),以該模封材料(28)覆蓋之後,該支稽桿(128) 暴露在該第一封裝表面(34)。 戈申叫專利範圍第23項之方法,其中該触刻進一步界定 k该複數個第一内插器(2〇)之至少一第一内插器(2〇) 擴充之支撐桿(5 8),以該模封材料(28)覆蓋之後,該支撐 才干(58)暴露在該第一封裝表面(μ)。 31. 如申請專利範圍第3〇項之方法,進一步包括·· 以該模封材料(28)覆蓋之前,該支撐桿與每一引腳 (16)之該第一表面(38)黏著在一表面〇〇〇)。 32. 如申請專利範圍第幻項之方法,其中電連接該半導體裝 置(12)之該等1/〇墊(22)與該複數個引腳(16),包括: 線焊或膠黏合該等I/O墊(22)與該複數個引腳(16)。 33·如申請專利範圍第23項之方法,進一步包括: 電連接該複數個引腳(16)之至少一引腳(16)與該複數 個第一内插器(20)之至少一第一内插器(2〇)。 91449-990715.doc • 6 ·
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US (1) | US7489021B2 (zh) |
EP (1) | EP1602130A4 (zh) |
JP (1) | JP2007521643A (zh) |
KR (1) | KR20050109502A (zh) |
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-
2004
- 2004-02-17 US US10/563,172 patent/US7489021B2/en not_active Expired - Lifetime
- 2004-02-17 CN CNB2004800047021A patent/CN100416815C/zh not_active Expired - Fee Related
- 2004-02-17 JP JP2006503649A patent/JP2007521643A/ja not_active Abandoned
- 2004-02-17 WO PCT/US2004/004676 patent/WO2004077508A2/en active Application Filing
- 2004-02-17 KR KR1020057015419A patent/KR20050109502A/ko not_active Application Discontinuation
- 2004-02-17 EP EP04711876A patent/EP1602130A4/en not_active Withdrawn
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Also Published As
Publication number | Publication date |
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EP1602130A2 (en) | 2005-12-07 |
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JP2007521643A (ja) | 2007-08-02 |
US7489021B2 (en) | 2009-02-10 |
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CN100416815C (zh) | 2008-09-03 |
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EP1602130A4 (en) | 2008-11-05 |
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