TW200933852A - Semiconductor chip package - Google Patents

Semiconductor chip package Download PDF

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Publication number
TW200933852A
TW200933852A TW097122846A TW97122846A TW200933852A TW 200933852 A TW200933852 A TW 200933852A TW 097122846 A TW097122846 A TW 097122846A TW 97122846 A TW97122846 A TW 97122846A TW 200933852 A TW200933852 A TW 200933852A
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TW
Taiwan
Prior art keywords
lead
wafer
chip package
package
semiconductor chip
Prior art date
Application number
TW097122846A
Other languages
Chinese (zh)
Inventor
Rainer Kastner
Frank-Michael Doberschutz
Original Assignee
Diodes Zetex Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Diodes Zetex Ltd filed Critical Diodes Zetex Ltd
Publication of TW200933852A publication Critical patent/TW200933852A/en

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    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

A semiconductor chip package (30) comprising a semiconductor chip (31), a lead frame comprising at least one lead (32) and an encapsulating layer (34) at least partially encapsulating the semiconductor chip (31) and the lead frame. The lead (32) comprises a first portion (36) defining a lead frame pad at least partially exposed at an exterior surface of the package and a second portion extending from the first portion (36) towards the semiconductor chip (31) electrically connecting a surface portion of the semiconductor chip (31) to the lead frame pad. The first portion (36) has a first thickness and the second portion comprises a thinned portion (37), the thinned portion (37) having a thickness smaller than the first thickness. The lead (32) further comprises a bent portion, and wherein the thinned portion comprises at least part of the bent portion.

Description

200933852 九、發明說明： 【發明所屬之技術領域】 發明領域 本發明係有關半導體晶片的封裝，尤其是，作、 5 ❹ 10 15 ❹ 獨地，本發明係有關於具有一成型封裝體的半導體f非唯 且特別是無引線式表面安裝的半導體晶片封裝體。日日片’ 造此一半導體晶片封裝體的方法亦被提供。 種製 t先前技術】 發明背景 對於具有緊密結構俾能最小化在消費用品中之 間的半導體晶片封裝體目前已有逐增的需求。&，所，空 定的用品，譬如行動電話等，需要重量輕且節省空=些特 裝結構。雖近年來，半導體晶片封裝體的尺寸和重^的封 十分可觀的縮減，但仍須要更多的改良。 蕙已有 目前已有許多習知的半導體晶片封裝技術。陶 膠材料皆曾被用來包封，並且保護該半導體a 和塑 丁平耻日日乃，而 一成型的封裝體。經由封裝體的端子來對該晶片的互战 常係藉導線接結及/或引線框來提供。 、接通 導線接結包括在該晶片的表面部份與該封襞體外土 η 一引線框的封裝體端子之間連接短長度的撓性導線。^或 結線則最後會被該包封材料至少部份地覆蓋來保護它們"等 一引線框可在製造時對一半導體晶片提供機械性支 撐，且該引線框的某些部份最後會將該晶片電連接於封装 體的端子。該引線框的-部份係在該封裝體内部，即被該 20 200933852 包封材料所包封。該引線框的某些部份可由該封裝體向外 伸出以供外部地電連接該封裝體，且亦可容該晶片内之過 多的熱消散。-引線框可包含一晶片接墊係被該晶片附 接，及引線等會將該晶片電連接於所完成之晶片封裝體的 5外部。該等引線可被直接連接於該晶片，或透過結線來連 接該曰曰片接墊可被暴露在該封裝體的底部。若沒有晶片 — 接墊，則該晶片的背面可被暴露以供直接電連接。暴露的 ❹ 日日日片接墊或暴露的晶片背面亦能將該晶片中所產生的熱， 透過該晶片所附接的基材有效地傳送至該環境中。 10 引線框係由扁平金屬片藉冲壓或蝕刻所構製者。冲壓 是一種機械製法，其中該引線框結構係經由一連串的壓印/ 冲孔步驟除去該金屬片的某些部份來形成。蝕刻包含以一 對應於該引線框之所需圖案的阻抗層來選擇地覆蓋該金屬 片，並將該金屬片暴露於化學蝕刻劑，其會除去未被該阻 15抗劑所覆蓋的區域。在該領域中所習知的擇代蝕刻技術亦 〇 可被使用於該等引線框的製造。該金屬片的整體厚度或其 一部份厚度係可被蝕掉。在冲壓或蝕刻之後該引線框會被 清潔和下沈定位《下沈定位包括相對於該引線框的相鄰部 份來將該引線框的某些部份推壓沈降，而使該下沈定位區 20域能相對於該引線框的其餘部份（尤其是該等引線接墊)將 該晶片容裝在正確的高度。此對決定該晶片的背面是否暴 露在該封裝體的底部是很重要的。 美國專利No. 6143981揭露一種塑膠覆蓋的積體電路 封裝體和一種引線框。美國專利N〇_ 6696747揭露一種用以 200933852 支推一晶片的金廣引線框’其係接合於該引線框之一中麥 晶片接墊區。結線會將該晶片上的接墊電連接於該弓丨線樞 的各別引線。該晶片、晶片接墊和引線等係被一包封材料 所包封。該封裝體的高度會藉部份地蝕刻該晶片接塾以使 5其厚度相對於該引線框的其餘部份減少而被最小化。 傳統的半導體晶片封裝體，例如雙個共線(DIL)封裝 — 體’會使用陶瓷或塑膠結構物並將晶片線結於引線框。該 ^ 專傳統设計的主要缺點係使用由該晶片封裝體向下伸出的 引線需要在一印刷電路板中設有鍍著的貫孔等，而該等弓丨 10線會被***其中益焊接於定位。此係為該板空間之一無效 率的使用，且製造谷裝該等晶片的板會較為費時和昂貴。 覆晶總成係為種利用設在晶片外部的導電凸體來將 正面朝下（故稱“翻覆”)的電子構件直接電連接於基材上，例 如印刷電路板或引線框的方法。覆晶設計會使用銅、金或 15焊劑凸體來將晶片互接於該引線框。相對地，導線接結典 〇 型會使用正面朝上的晶片，而以一導線連接於各晶片端 子。覆晶總成會免除導線接結的電阻。且，免除結線會減 少該等晶片中之連接物的電感和電容，並縮短電路徑長 度’而造成更高的晶片傳訊速度並改良該晶片封裝體的高 20頻特性。又，結線連接物係被限制於該半導體晶粒的周緣， 故其必須增加該晶片尺寸才能增加連接物的數目。相反 地，覆晶連接物可連接於該晶粒的整個面積。 美國專利申請公開案No_ 2004/01 〇858〇(Tan等人)揭露 無W線式（即沒有引線實質地突出超過該封裝體的外表面） 200933852 倒轉覆晶半導體封裝結構。該結構包含一半導體晶片互接 於—凹陷的引線框，且所形成的總成被包封在一成型的化 合物中。其最終產品係為一種呈一無引線四合扁平封裝構 形的倒裝式半導體晶片。 5 Ο 10 15 Ο 覆晶總成是一種表面安裝技術的形式，其中從該晶片 封裝體對印刷電路板的連接並不需要鍍著的貫孔。該封裝 體的外部引線係併附於該陶瓷或塑膠的本體結構中。該半 導體晶片的底部亦可被暴露於該封裝體的底部，以容直接 電連接於該晶片。該引線框之頂面的某些部份亦可被暴 露。此乃是較有利的，因其能容許過多的熱被發散◊且、， 免除該封裝體外部的引線會大大地減少所需的板面積，及 該封裝體的高度和重量。 —般而該，無引線封裝體，譬如覆晶組合的晶片封裴 體會較小，並會有比設具外部引線之封裝體更佳的熱和電 特性，且能被更有效率地製造。大部份被組合於無？丨線封 裝體中的晶片只須在該晶片頂面上設有電連接物，意即覆 晶總成會特別地適合。 C發明内容;j 發明概要 本發明之一目的係為消除或減免如上所述或其它之石 知技術的一或多個問題。本發明的另_目的係為提供 可擇的半導體晶片封裝形式。 依據本發明之-第-態樣係在提供一種半導體晶 裝體’包含：-半導體晶片；—引線植含有至少 20 200933852 及-包封層至少部份地包封 中則線包含一第一部份界定一5=和該引線框;其 在該封袭體之一外表面處，及=線框塾至少部份地暴露 該半導體晶片延伸而將:半:體=份:該第-_ 於該弓丨線框墊，且其讀第部份電連接 第二部份肖#具有-第—厚度，而該 第-厚心=份’該薄化部份具有-厚度小於該 ❹ 10 15 Ο 包含該f曲部份的至少_部份箱，且其中該薄化部份 $的是，本發明提供_種可靠的半導 其中具有-引線框結構，其*^ & 对輯 抗。|έ荖# 、 生一非常低之電和熱的阻 藉者減少部份引線的厚度 體晶片封1 彳該半導 長度會!將能被減少該等弓|線的 彎:的…“:传減;該弓丨線的電阻。該等部份薄化且 的弓丨線亦可用以減少該包封材料與該引線框剝離的發 率。該引線框係可輕易適配於容裝不同的晶片厚度，而 不必太大地重新設計該引線框。 ,該薄化部份可包含該引線的—部份，於該處該弓！線會 從其一面被減少厚度β或者，該薄化部份可包含該引線的 一部份，其中該引線會從兩面被減少厚度。 該變曲部伤可元全在該薄化部份内。該引線可只在該 彎曲部份内被薄化。該薄化部份可由該引線墊伸出。 該引線墊與該薄化部份之間的接合處可在該封装體的 外部形成該引線厚度之一階狀變化處，以使該包封層終結 在該階狀變化處而鄰接於該引線墊之一暴露部份。 20 200933852 該引線可包含一彎曲部沿一第一方向， 一第二方向，而使該弓丨線框界定—下沈定位區可 該晶片。該引線框可在該下沈定位區的至少一部份中被薄化。 5 ο 10 15 ❹ 該等引線實質上不可突出超過該晶片封」匕 則線框的某些雜可郷露在該“封㈣_面°。較 好疋，該暴露的晶片底部是被覆層於一可焊接材料中。 該半導體晶片封裝體可包含多數的引線。該半導體曰 片封裝體可包含二或更多個晶片。該或各晶片可被該接^ 層完全地包封。該晶片或至少一晶片的底部之至少一部份 可被暴露在該晶片封裝體的底部。 至少一導電凸體可被提供在該或各晶片的頂面上，且 該或各引線會與至少一凸體電接觸，而使該晶片透過該凸 體電連接於該引線。 該或各引線可被多數個凸體電連接於該晶片。 依據本發明之一第二態樣係在提供一種製造一半導體 晶片封裝體的方法，該方法包含：提供一半導體晶片；提 供一引線框含有至少一引線；及將該半導體晶片的至少一 部份和該引線框的至少一部份包封在一包封層内；其中該 引線包含一第一部份具有一第一厚度並界定一引線框墊至 少部份地暴露在該封裝體之一外表面，及一第二部份由該 第一部份向該半導體晶片延伸，並將該半導體晶片之一表 面部份由連接於該引線框墊’且其中該方法更包含：薄化 該第一部份的至少一部份來形成一薄化部份，而使該薄化 部份比該第一部份更薄；及彎曲該薄化部份的至少一部份 20 200933852 5 Ο 來形成該引線的第二部份之一彎曲部份的至少一部份。 薄化該第二部份的至少一部份來形成一薄化部份可包 含由該引線的一面來減少該引線的厚度。或者，薄化該第 二部份的至少一部份來形成一薄化部份可包含由該引線的 兩面減少該引線的厚度。 該方法更可包含只彎曲該薄化部份中的引線。 該方法包更可包含只薄化該彎曲部份中的引線。 該薄化部份可由該引線墊伸出。 該引線墊與該薄化部份之間的接合處可在該封裝體的 10 外部形成該引線厚度之一階狀變化處，以使該包封層終結 在該階狀變化處而鄰接於該引線墊之一暴露部份。 彎曲該引線的至少一部份來形成一彎曲部份包含沿一 第一方向彎曲該引線，及沿一第二方向彎曲該引線，而使 該引線框界定一下沈定位區可適於容裝該晶片。 15 Ο 該方法可更包含薄化在該下沈定位區之至少一部份内 的引線框。 該等引線實質上不可突出超過該晶片封裝體的外部。 該方法可更包含暴露在該晶片封裝體頂面上的部份引 線框。 20 該方法可更包含提供多數的引線。該方法可更包含提 供二或更多個晶片。 該方法可更包含將該或各晶片完全地包封在樹脂層 内0 該方法可更包含暴露在該晶片封裝體底部之該晶片或 11 200933852 至少-該等晶片的底部之至少 可被覆層在-可焊接的材料中。"〜暴露的晶片底部 頂面i方去可更包含提供至少—導電凸體於該或各晶片的 =:使該或各引線與至少-凸體電接觸，而將該晶 月電連接於該引線。 該晶片 =方去可更包含以多數個凸體將該或各引線電連接於 月0 、 〇 〇 該薄化該第二部份的至少一 步驟可包含部份地_，第/ 4一薄化部份的 10厚度。 …第—精的至少-部份來減少其 圖式簡單說明 本發明現將參照所關式僅作舉例地描述制，其 示::示出—習知形式的半導體晶片封裝體: 2圖係不意麵出第1圖之半導體晶片封裝體的底面. 第形式的半導體晶片封装體； 二截“一-依據本發明的半導雜晶 第5圖係以截面示意地示出 在製造之-中間階段時之二可擇的部件形狀片封裝體 0形狀第6_示出第5圖的部件在另—製造中間階段之後的 第7圖係以截面示意地示出第4^ 的一部份，及第3圖之半導體晶片封裝體 們能被併排地比較； M各它 200933852 第8圖係示意地示出一依據本發明之一可擇實施例的 半導體晶片封裝體； 第9圖係示意地示出一依據本發明之又另—可擇實施 例的半導體晶片封裝體； 5 Ο 10 15 ❹ 20 第10圖係示意地示出本發明的另一實施例其可適合於 多晶片用途； 第11圖係示意地示出第10圖的封裝體之一截面圖；及 第12圖係示意地示出第4圖的半導體晶片封裝體之另 一修正例。200933852 IX. OBJECTS OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to the packaging of semiconductor wafers, and in particular, the invention relates to semiconductors having a molded package. Non-only and especially leadless surface mount semiconductor chip packages. A method of making this semiconductor chip package is also provided. BACKGROUND OF THE INVENTION There is an increasing demand for semiconductor chip packages that have a compact structure that minimizes the need for consumer products. &, the empty supplies, such as mobile phones, need to be lightweight and space-saving = some special structures. Although the size and weight of semiconductor chip packages have been considerably reduced in recent years, more improvements are needed. There are many conventional semiconductor chip packaging technologies available. Ceramic materials have been used to encapsulate and protect the semiconductor a and plastic, and a molded package. The warfare of the wafer via the terminals of the package is often provided by wire bonding and/or leadframe. Turning on the wire bond includes connecting a short length of flexible wire between the surface portion of the wafer and the package body terminal of the package body. ^ or the junction is finally covered at least partially by the encapsulation material to protect them "a lead frame can provide mechanical support for a semiconductor wafer at the time of manufacture, and some parts of the lead frame will eventually The wafer is electrically connected to the terminals of the package. The portion of the lead frame is internal to the package, i.e., encapsulated by the 20 200933852 encapsulating material. Portions of the lead frame may extend outwardly from the package for externally electrically connecting the package and may also dissipate excessive heat within the wafer. The lead frame may include a die pad attached to the die, and leads or the like electrically connecting the die to the exterior of the finished chip package 5. The leads may be directly attached to the wafer or connected via a bond to the die pad to be exposed at the bottom of the package. If there is no wafer-pad, the back side of the wafer can be exposed for direct electrical connection. The exposed day-to-day wafer pads or exposed wafer backsides can also effectively transfer the heat generated in the wafer to the environment through the substrate to which the wafer is attached. 10 The lead frame is constructed by stamping or etching a flat metal sheet. Stamping is a mechanical process in which the leadframe structure is formed by removing portions of the metal sheet through a series of embossing/punching steps. Etching includes selectively covering the metal sheet with a resistive layer corresponding to the desired pattern of the lead frame and exposing the metal sheet to a chemical etchant that removes areas not covered by the resist. The alternative etching techniques known in the art can also be used in the fabrication of such leadframes. The overall thickness of the metal sheet or a portion thereof may be etched away. The lead frame is cleaned and sunken after stamping or etching. "Sinking positioning includes pushing and sinking certain portions of the lead frame relative to adjacent portions of the lead frame to position the sinker The region 20 can accommodate the wafer at the correct height relative to the remainder of the leadframe, particularly the lead pads. This pair is important to determine if the back side of the wafer is exposed to the bottom of the package. U.S. Patent No. 6,143,981 discloses a plastic-covered integrated circuit package and a lead frame. U.S. Patent No. 6,696,747 discloses a gold-plated lead frame for pushing a wafer with 200933852, which is bonded to the wafer pad region of one of the lead frames. The junction will electrically connect the pads on the wafer to the respective leads of the bow pivot. The wafer, wafer pads, leads, etc. are encapsulated by an encapsulating material. The height of the package is minimized by partially etching the wafer interface such that its thickness is reduced relative to the remainder of the lead frame. Conventional semiconductor chip packages, such as dual collinear (DIL) packages, will use ceramic or plastic structures and wire the wafers to the leadframe. The main disadvantage of this conventional design is that the use of leads extending downward from the chip package requires a plated through hole or the like in a printed circuit board, and the bow 10 lines are inserted therein. Soldering in position. This is the use of one of the board spaces' inefficiencies, and it can be time consuming and expensive to manufacture panels in which the wafers are loaded. The flip chip assembly is a method of directly electrically connecting an electronic component facing downward (so called "overturning") to a substrate, such as a printed circuit board or a lead frame, by using an electrically conductive projection provided outside the wafer. The flip chip design uses copper, gold or 15 solder bumps to interconnect the wafers to the lead frame. In contrast, the wire bond pattern uses a wafer facing up and a wire to connect to each wafer terminal. The flip chip assembly eliminates the resistance of the wire bond. Moreover, eliminating the junction line reduces the inductance and capacitance of the connections in the wafers and shortens the electrical path length' resulting in higher wafer transfer speeds and improved high frequency characteristics of the chip package. Also, the junction connection is limited to the periphery of the semiconductor die, so it is necessary to increase the size of the wafer to increase the number of connectors. Conversely, a flip chip connector can be attached to the entire area of the die. U.S. Patent Application Publication No. 2004/01 〇 858 (Tan et al.) discloses a W-free type (i.e., no lead substantially protrudes beyond the outer surface of the package) 200933852 Inverted flip-chip semiconductor package structure. The structure includes a semiconductor wafer interconnected to a recessed leadframe, and the formed assembly is encapsulated in a formed compound. The final product is a flip-chip semiconductor wafer in a leadless quad flat package configuration. 5 Ο 10 15 Ο The flip chip assembly is a form of surface mount technology in which the connection from the wafer package to the printed circuit board does not require a plated through hole. The outer leads of the package are attached to the body structure of the ceramic or plastic. The bottom of the semiconductor wafer can also be exposed to the bottom of the package to accommodate direct electrical connection to the wafer. Some parts of the top surface of the lead frame may also be exposed. This is advantageous because it allows for excessive heat to be dissipated and the elimination of leads outside the package greatly reduces the required board area and the height and weight of the package. As a general rule, leadless packages, such as flip chip combinations, will have smaller wafer packages and will have better thermal and electrical characteristics than packages with external leads and can be manufactured more efficiently. Most of them are combined in nothing? The wafer in the tantalum package only has to have an electrical connection on the top surface of the wafer, meaning that the flip chip assembly will be particularly suitable. C SUMMARY OF THE INVENTION j SUMMARY OF THE INVENTION One object of the present invention is to eliminate or eliminate one or more of the problems of the above-described or other known techniques. Another object of the present invention is to provide an alternative semiconductor wafer package form. The first aspect of the present invention provides a semiconductor wafer body comprising: - a semiconductor wafer; - the lead implant contains at least 20 200933852 and - the encapsulation layer is at least partially encapsulated and the line comprises a first portion Defining a 5= and the lead frame; at an outer surface of the encapsulant, and = the wire frame 塾 at least partially exposing the semiconductor wafer to extend: half: body = part: the first - _ The bow wire frame pad, and the reading portion thereof is electrically connected to the second portion XI# having a -th thickness, and the first center portion = the portion of the thinned portion having a thickness less than the ❹ 10 15 Ο At least a portion of the box containing the f-curved portion, and wherein the thinned portion is $, the present invention provides a reliable semi-conductor having a - lead frame structure, which is *^ &|έ荖#, a very low electric and thermal barrier borrower reduces the thickness of part of the lead body wafer seal 1 彳 the semi-conductive length will! Can be reduced by the bow | line bend:...": The resistance of the bow line is such that the thinned bow line can also be used to reduce the rate of peeling of the encapsulating material from the lead frame. The lead frame can be easily adapted to accommodate different contents. The thickness of the wafer without having to redesign the lead frame too much. The thinned portion may comprise a portion of the lead where the bow! line will be reduced in thickness from one side of the bend or the thinned portion The portion may include a portion of the lead, wherein the lead is reduced in thickness from both sides. The bend portion may be entirely within the thinned portion. The lead may be thinned only within the curved portion. The thinned portion may protrude from the lead pad. The joint between the lead pad and the thinned portion may form a step change of the thickness of the lead outside the package to make the encapsulation layer Terminating at the step change adjacent to an exposed portion of the lead pad. 20 200933852 The lead may include a The curved portion is along a first direction, a second direction, such that the bow wire frame defines a sinking positioning region for the wafer. The lead frame can be thinned in at least a portion of the sinking positioning region. 5 ο 10 15 ❹ The leads are substantially not protruded beyond the wafer seal.” Some of the wires of the wire frame are exposed to the “four” surface. Preferably, the exposed wafer bottom is coated with In a solderable material, the semiconductor chip package may comprise a plurality of leads. The semiconductor chip package may comprise two or more wafers. The or each wafer may be completely encapsulated by the layer. At least a portion of the bottom of at least one of the wafers may be exposed at the bottom of the chip package. At least one conductive bump may be provided on a top surface of the or each wafer, and the or each lead may be associated with at least one of the protrusions Electrically contacting, the wafer is electrically connected to the lead through the protrusion. The or each lead may be electrically connected to the wafer by a plurality of protrusions. According to a second aspect of the present invention, a semiconductor wafer is provided A method of a package, the method comprising: Providing a semiconductor wafer; providing a lead frame comprising at least one lead; and encapsulating at least a portion of the semiconductor wafer and at least a portion of the lead frame in an encapsulation layer; wherein the lead includes a first portion Having a first thickness and defining a leadframe pad at least partially exposed to an outer surface of the package, and a second portion extending from the first portion to the semiconductor wafer and the semiconductor wafer a surface portion is connected to the lead frame pad' and wherein the method further comprises: thinning at least a portion of the first portion to form a thinned portion, wherein the thinned portion is compared to the first portion Partially thinner; and bending at least a portion of the thinned portion 20 200933852 5 形成 to form at least a portion of a curved portion of the second portion of the lead. Thinning at least a portion of the second portion Forming a thinned portion in part may include reducing the thickness of the lead from one side of the lead. Alternatively, thinning at least a portion of the second portion to form a thinned portion can include reducing the thickness of the lead from both sides of the lead. The method may further comprise bending only the leads in the thinned portion. The method package may further comprise thinning only the leads in the curved portion. The thinned portion can be extended by the lead pad. The junction between the lead pad and the thinned portion may form a step change of the thickness of the lead outside the package 10 such that the encapsulation layer terminates at the step change adjacent to the One of the lead pads is exposed. Bending at least a portion of the lead to form a curved portion includes bending the lead in a first direction and bending the lead in a second direction such that the lead frame defines a recessed positioning area adapted to receive the lead Wafer. 15 Ο The method may further include thinning the lead frame in at least a portion of the sinking location. The leads are substantially not protruded beyond the exterior of the chip package. The method can further include a portion of the leadframe exposed on the top surface of the chip package. 20 This method can include more leads. The method may further comprise providing two or more wafers. The method may further comprise completely encapsulating the or each wafer in the resin layer. The method may further comprise exposing the wafer to the bottom of the wafer package or 11 200933852. At least - at least the coating layer at the bottom of the wafers is - Can be welded in the material. "~ the top surface i of the exposed wafer bottom may further comprise providing at least - a conductive protrusion on the or each wafer =: making the or each lead electrically contact with at least the convex body, and electrically connecting the crystal moon to The lead. The wafer = square may further include electrically connecting the or each lead to the month 0 by a plurality of protrusions, and at least one step of thinning the second portion may include a portion of the _, a / 4 thin The thickness of the part is 10 . BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described by way of example only with reference to the accompanying drawings, which show: a semiconductor chip package of the conventional form: 2 The bottom surface of the semiconductor chip package of FIG. 1 is omitted. The semiconductor chip package of the first form; the second section of the semiconductor wafer package according to the present invention is schematically shown in cross section in the middle of manufacturing. Optional component shape sheet package 0 shape 6th - shows the portion of the fifth diagram after the intermediate stage of the other manufacturing process, a portion of the 4th portion is schematically shown in cross section, And the semiconductor chip package of FIG. 3 can be compared side by side; M each of it 200933852 Fig. 8 is a schematic view showing a semiconductor chip package according to an alternative embodiment of the present invention; A semiconductor chip package according to still another alternative embodiment of the present invention is shown; 5 Ο 10 15 ❹ 20 FIG. 10 is a schematic view of another embodiment of the present invention which is suitable for multi-wafer use; 11 is a schematic view showing a section of the package of FIG. ; And another modified example of FIG. 12 schematically shows a line of FIG. 4 of the semiconductor chip package.

t實施方式;J 較佳實施例之詳細說明 首請參閱第1圖，其以截面示意地示出一習知形式的表 面安裝式無引線半導體晶片封裝體丨。該晶片封裝體丨包含 一引線框2,其含有一晶片墊3及多數的引線墊4。—半導體 晶片5係藉一黏性化合物附接於該晶片墊3。該半導體晶片5 的某些表面部份係經由結線6被連接於該等引線塾4。該引 線框2、晶片5和、结線6等係被一樹脂層7包封。在本說明書 中所述的樹脂層係 '指任何能部份或完全地包封該半導體晶 片和其匕構件的材料。刻語並無意要被限制於任何特定 的材料。該等弓|線塾4的侧面8和底面9部份及該晶片私的 底面10會暴露在鮮導體晶片封裝則的外㈣供 (即該樹月旨層7不會完全地包圍該晶片封裝則。該暴露的曰曰 片塾3可容來自該晶片5的熱消散。該等引線沒有由該日^ 封裝體1伸出外部將可減少-印刷電路板上被該晶片i曰裝 13 200933852 體1所占用的空間量。 第2圖示意地示出第1圖之半導體晶片封裝則的底 面，第2圖示出引線墊4等沿該晶片封裝體i的兩側排列。 但，應可輕易瞭解其中可有任何數目㈣ 5片亦可被完全地包圍。更概言之，引線塾係可被提供在遍 及該晶片之表面區域的任何處。 請參閱第3圖’其係以截面示意地示出一習知形式的倒 〇 料導體晶片2G在一無引線半導體晶片封裝體21中。晶片 2〇係以覆晶接結法連接於-引線框22。引線㈣包含⑽ m等會由該晶片封裝體21的外部，即它們界定引線墊以之 處，朝向該晶片20延伸。可以看出該引線_沒有晶片塾’ 但亦可提供-個。凸體25等係由_導電材料所形成，而被 提供在該晶片20的表面上。該等凸體25會接觸引線23等， ⑽該晶片能電連接於該晶片封裝體21的外部。晶片2〇和 15引線框22係被樹脂層26部份地包封。晶片底面煎該等引 〇 線墊24的側面和底面部份係暴露於該晶片封裝體21的外部。 引線23等沿它們之整體長度係為實質上均一的厚度。 在該等引線由該晶片封裝體的底面f離的區域28處 ，該樹 脂層會在引線23上形成一薄層。此樹脂薄層係容易由該等 20引線剝離，而對該晶片封裝體造成損害。 第4圖係以截面示意地示出一依據本發明的半導體晶 片封裝體30。半導體晶片31係被由一導電材料形成的凸體 33等連接於-引線框，其含有引線32等。包封層34(譬如一 樹脂層）會部份地覆蓋晶片31和引線框32。該晶片31的底面 14 200933852 35係暴露在該封裝體3〇的外部。該晶片31的暴露部份在本 發明的某些實施例中可被塗覆一可焊接材料。 5 ❹ 10 15 ❹ 20 引線32包含第一部份36界定引線墊，其具有部份暴露 的侧面和底面在該封裝體3〇的外部。引線32係連接於凸體 33，而使該晶片31的某些表面部份電連接於該等引線墊 36。在本發明之可擇實施例中可能沒有導電凸體”，而使 該等引線直接與該晶片31接觸。或者，引線32亦可被以結 線連接於該晶片31。當由上方觀之，晶片31可被引線32等 完全地包圍，或可有-些引線設在該晶片之任意數目的側 邊。亦可在該晶片的每一側邊設有任何數目的引線。 引線32更包含第二部份37。帛二部份37係比該引線势 36更薄，且亦比該引線連接於凸體33的端部更薄。即是， 該第-部份具有-第—厚度，係沿該封裝體的職方向所 測得，而該第二部份包封含一薄化部份具有一厚度小於該 第一厚度。在第4圖所示的截面圖中，該第一部份的厚度係 沿垂直方向所測得者。第二部份37在此係可被另稱為薄化 部份37。應請瞭解在本發明的可擇實施例中，該等引線連 接於凸體33的一端亦可不比該薄化部份π更厚。 引線框32係由金屬片以㈣（或藉冲壓或該兩者的組 合)來形成。該金屬片的某些部份可被完全地蝕刻，而使該 金屬被完全地除去來形成該引線框的圖案。該薄化部份37 係藉半#卿金屬片以使該金屬的某些厚度被除去而來形 成。所述之半侧乙詞並非欲予㈣薄化部份精確地限制 為該金廣片的一半厚度(雖有可能)。該薄化部份37係被示出DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to FIG. 1, a schematic form of a surface mount leadless semiconductor chip package body is schematically illustrated in cross section. The chip package 丨 includes a lead frame 2 including a wafer pad 3 and a plurality of lead pads 4. - The semiconductor wafer 5 is attached to the wafer pad 3 by means of an adhesive compound. Some of the surface portions of the semiconductor wafer 5 are connected to the lead wires 4 via the junction wires 6. The lead frame 2, the wafer 5, the junction line 6, and the like are enclosed by a resin layer 7. The resin layer as used in the specification refers to any material which can partially or completely enclose the semiconductor wafer and its crucible member. The inscription is not intended to be limited to any particular material. The side 8 and bottom 9 portions of the bows 4 and the bottom 10 of the wafer are exposed to the outer (four) of the fresh conductor chip package (ie, the tree layer 7 does not completely surround the chip package) The exposed cymbal cymbal 3 can dissipate heat from the wafer 5. The leads are not extended by the outer surface of the package 1 and can be reduced - the printed circuit board is mounted by the wafer i 13 200933852 The amount of space occupied by the body 1. Fig. 2 is a view schematically showing the bottom surface of the semiconductor chip package of Fig. 1, and Fig. 2 is a view showing the lead pads 4 and the like arranged along both sides of the chip package i. It is easy to know that there can be any number (4) 5 pieces can also be completely surrounded. More generally, the lead wire can be provided anywhere in the surface area of the wafer. Please refer to Figure 3 A conventionally-formed inverted conductor wafer 2G is shown in a leadless semiconductor chip package 21. The wafer 2 is connected to the lead frame 22 by flip chip bonding. The lead (4) includes (10) m, etc. The outside of the chip package 21, that is, where they define the lead pads, toward the The sheet 20 is extended. It can be seen that the lead _ has no wafer 塾' but can also be provided. The convex body 25 or the like is formed of a _ conductive material and is provided on the surface of the wafer 20. The convex body 25 Contacting the lead 23 or the like, (10) the wafer can be electrically connected to the outside of the chip package 21. The wafer 2 and the lead frame 22 are partially encapsulated by the resin layer 26. The bottom surface of the wafer is fried by the substrate pad 24 The side and bottom portions are exposed to the outside of the chip package 21. The leads 23 and the like are substantially uniform in thickness along their entire length. At the regions 28 where the leads are separated from the bottom surface f of the chip package, The resin layer forms a thin layer on the lead 23. The resin thin layer is easily peeled off by the 20 leads and causes damage to the chip package. Fig. 4 is a schematic cross-sectional view showing a cross-sectional view according to the present invention. The semiconductor chip package 30. The semiconductor wafer 31 is connected to a lead frame by a protrusion 33 or the like formed of a conductive material, and includes a lead 32, etc. The encapsulation layer 34 (such as a resin layer) partially covers the wafer 31. And lead frame 32. The bottom surface 14 of the wafer 31 20093 The 3852 35 is exposed to the outside of the package 3. The exposed portion of the wafer 31 can be coated with a solderable material in certain embodiments of the invention. 5 ❹ 10 15 ❹ 20 Lead 32 includes the first portion The portion 36 defines a lead pad having a partially exposed side and a bottom surface outside the package body 3. The lead 32 is attached to the protrusion 33 to electrically connect certain surface portions of the wafer 31 to the leads Pad 36. In an alternative embodiment of the invention there may be no conductive bumps", such that the leads are in direct contact with the wafer 31. Alternatively, the leads 32 may also be connected to the wafer 31 by wire bonding. The wafer 31 can be completely surrounded by the leads 32 or the like, or some of the leads can be provided on any number of sides of the wafer. Any number of leads may also be provided on each side of the wafer. Lead 32 further includes a second portion 37. The second portion 37 is thinner than the lead potential 36 and is also thinner than the end of the lead connected to the projection 33. That is, the first portion has a -th thickness which is measured along the direction of the package, and the second portion includes a thinned portion having a thickness smaller than the first thickness. In the cross-sectional view shown in Fig. 4, the thickness of the first portion is measured in the vertical direction. The second portion 37 can be referred to herein as a thinned portion 37. It should be understood that in an alternative embodiment of the invention, the ends of the leads connected to the projections 33 may not be thicker than the thinned portions π. The lead frame 32 is formed of a metal piece by (d) (or by stamping or a combination of the two). Portions of the metal sheet can be completely etched such that the metal is completely removed to form the pattern of the lead frame. The thinned portion 37 is formed by removing a portion of the metal sheet to remove some of the thickness of the metal. The half of the word is not intended to be (4) the thinned portion is precisely limited to half the thickness of the gold piece (although possible). The thinned portion 37 is shown

15 200933852 只由一面來被薄化，但其亦可由兩面來被薄化。 5 ❹ 10 15 ❹ 20 該引線框32會在該晶片31的區域被下沈定位。即是， 當在製造時，引線32等會被彎曲如所示地形成一S狀的彎曲 部，而使引線墊36的底部係大約在該晶片31底面35的同一 平面中。即是，由該下沈定位區所形成之腔穴的深度係如 同該晶片31的厚度加上凸體33的高度。在可擇實施例中， 該晶片31的底面35係可比該等引線墊36的底部更高些，而 使該晶片能被樹脂層34完全地包封（即該晶片的底面35並 不暴露）。所述之“下沈定位”乙詞係指當在製造時，該封裝 體會被以倒反的方式組合，直到其示出如第4圖的完成封裝 體為止。晶片31會被置於該引線框的下沈定位區上，而使 其在被樹脂層34包封之前能藉由凸體33等形成電接觸。該 用語並無對所完成封裝體30中的晶片31或引線框32之定向 賦予任何的限制。在本發明的可擇實施例中，該等引線亦 可具有更多或較少的彎曲部，而使它們能以不同的角度接 近該晶片。 該引線框3 2的總深度係等於形成該引線框3 2的金屬片 厚度（即在非薄化區中的引線厚度)加上彎曲的程度。應請瞭 解藉改變該引線框32的彎曲度及/或改變該二彎曲部之間 的引線長度，則不同厚度的晶片將可被容納。此能被容納 的晶片之類型和尺寸可調適性會令第4圖中所示的晶片封 裝體可以非常廣泛地應用。 如在第4圖中可見，該等引線32的彎曲部是在薄化部份 37中。藉著減少要被彎曲之引線32的厚度，該等彎曲部的 16 200933852 半徑將能被減小。減小該等膏曲半徑會大大地減少被該等 引線32所占去的空間，並減少所完成之晶片封裝體3〇的尺 寸’且特別的面積。在本發明的可擇實施例中亦可只設 有-彎曲部（即-彎曲部僅只沿一方向）。該彎曲部可係完全 5在該薄化部份37中，或者該彎曲部亦可延伸超過該薄化部 份37。 又，在第4圖中亦可看到該等弓丨線32的薄化部份37延伸 〇 线判線㈣的邊緣。因此在引線墊36之暴露底部的邊 緣處會有-引線32厚度的階狀變化處38。此會具有一較佳 1〇的效果來防止該樹脂層在接近化線墊36處（即該等引線32 由該封裝體30的底面彎離處)形成—非常薄的轉變區。此一 樹脂薄層（亦被稱為塑膠毛邊)乃是不佳的，因其會使該樹脂 層由引線框32剝離而損及該封裝體3〇。階狀變化處38係較 為有利，因其會將引線32更緊密地鎖固於該樹脂層34中， 15 而增加該晶片封裝體30的整體強度。 Q 引線框32可由許多不同的材料製成。這些材料僅被它 們係為導電性並能良好地接合於該樹脂層和凸體33等之要 件所限制。典型地，該引線框32係由一金屬例如 一銅合金 或一鐵鎳合金所形成。該引線框32的暴露部份可被鍍以 2〇 銀、鎳或金來減少它們的電阻。 在本發明的某些實施例中，該封裝體係能夠經由引線 32等來將大量的熱由該晶片31傳送消除。該等引線32的頂 部可被暴露在該晶片封裝體的外部以協助此熱傳導。且， 該晶片的底面35可被連接於一印刷電路板冷却區來將過多 17 200933852 Ο 10 15 ❹ 20 的熱傳導排掉。 -可線塾Μ和晶片背面35可在組合之前被艘以 或金屬層中爽於該封裝體與該 間來改良該焊劑連接於印刷電路板的強度。 現請參閱第5圖，其係以截面示意地示出在-中間製造 階段時該引線32之二變化开η 3…/在中間製& 形式。引線32係被示出在餘刻之 彎曲成其最後的下沈定位形狀之前的狀態。引 線為—如第4圖。所示之引線32的類似形狀。引線純 3引線墊箱36a和薄化部份37a。該引線32a相反於引線塾 3如的端包3 _第二較厚部份4〇,該引線μ最後會在該點 處被附接於凸體33。 引線32b係類似於引線仏，只是其中沒有第二較厚部 份。即是，該薄化部份37b會由該引線墊灿延伸至該引線 32的另：端’應請瞭解該等引線的變化構形亦有可能。例 如’該薄化部份的厚度可相對於該引線的其餘部份之厚度 而來改變°或者，該薄化部份37可非緊接於引線塾36之後 開始。第5圖中所示的舉例引線32具有薄化部份大約為該引 線之其餘部份的-轉。如前所述，料引線财可由兩 面被薄化。該薄化部份的比例和位置亦可與所示之例不同。 第6圖示出引線32&和321?在被彎曲來形成一引線框在 一下沈定位區的部份之後的狀態。該等引線係被示出沿二 相反方向彎曲，而使引線的兩端大致在平行的平面中。應 請瞭解於本發明的可擇實施例中，該彎曲度和方向係可改 變而來在引線墊36與晶片之間提供適當的連接。 18 200933852 現請參閱第7圖，其係以截面示意地示出第4圖之半導 體晶片封裝體30的一部份，及第3圖之半導體晶片封裝助 的一部份。晶片封裝體30為依據本發明者。晶片封裝體2ι 是一種習知類型。 5 ❹ 10 15 Ο 20 圖示區域50a、50b代表引線32、23與樹脂層％、^之15 200933852 It is thinned by one side only, but it can also be thinned by two sides. 5 ❹ 10 15 ❹ 20 The lead frame 32 is recessed in the area of the wafer 31. That is, when manufactured, the lead wires 32 and the like are bent to form an S-shaped bent portion as shown, and the bottom portion of the lead pad 36 is formed in the same plane of the bottom surface 35 of the wafer 31. That is, the depth of the cavity formed by the sinking positioning zone is the same as the thickness of the wafer 31 plus the height of the convex body 33. In an alternative embodiment, the bottom surface 35 of the wafer 31 can be higher than the bottom of the lead pads 36 so that the wafer can be completely encapsulated by the resin layer 34 (ie, the bottom surface 35 of the wafer is not exposed) . The term "sinking positioning" as used herein means that when manufactured, the package is combined in an inverted manner until it shows the finished package as in Fig. 4. The wafer 31 is placed on the sinking positioning area of the lead frame so that it can be electrically contacted by the projections 33 or the like before being encapsulated by the resin layer 34. This term does not impose any limitation on the orientation of the wafer 31 or leadframe 32 in the finished package 30. In alternative embodiments of the invention, the leads may also have more or fewer bends to enable them to approach the wafer at different angles. The total depth of the lead frame 32 is equal to the thickness of the metal sheet forming the lead frame 32 (i.e., the thickness of the lead in the non-thinned region) plus the degree of bending. The wafers of different thicknesses will be accommodated if the bending of the lead frame 32 is changed and/or the length of the leads between the two bends is changed. The type and size of the wafer that can be accommodated allows the wafer package shown in Figure 4 to be used very widely. As can be seen in Figure 4, the bends of the leads 32 are in the thinned portion 37. By reducing the thickness of the lead 32 to be bent, the radius of the 16 200933852 of the bends can be reduced. Reducing the radius of the pastes greatly reduces the space occupied by the leads 32 and reduces the size and particular area of the finished chip package 3. In an alternative embodiment of the invention, it is also possible to provide only a curved portion (i.e., the curved portion is only in one direction). The bent portion may be completely 5 in the thinned portion 37, or the bent portion may extend beyond the thinned portion 37. Further, in Fig. 4, it can be seen that the thinned portion 37 of the bow line 32 extends the edge of the 判 line judgment line (4). Thus there will be a step change 38 in the thickness of the lead 32 at the edge of the exposed bottom of the lead pad 36. This would have a preferred effect to prevent the resin layer from forming a very thin transition zone at the proximity line pad 36 (i.e., where the leads 32 are bent away from the bottom surface of the package 30). This thin layer of resin (also referred to as a plastic burr) is undesirable because it causes the resin layer to be peeled off by the lead frame 32 to damage the package. The step change 38 is advantageous because it more closely locks the leads 32 in the resin layer 34, 15 increasing the overall strength of the chip package 30. The Q lead frame 32 can be made from many different materials. These materials are only limited by the requirements that they are electrically conductive and can be joined well to the resin layer and the projections 33. Typically, the lead frame 32 is formed of a metal such as a copper alloy or an iron-nickel alloy. The exposed portions of the leadframe 32 can be plated with 2 Å of silver, nickel or gold to reduce their electrical resistance. In some embodiments of the invention, the package system is capable of removing a significant amount of heat from the wafer 31 via leads 32 or the like. The tops of the leads 32 can be exposed to the outside of the chip package to assist in this heat transfer. Moreover, the bottom surface 35 of the wafer can be connected to a printed circuit board cooling zone to drain excess heat of 17 200933852 Ο 10 15 ❹ 20 . The reticle and wafer backside 35 can be tempered by the ribbon or metal layer prior to assembly to improve the strength of the solder connection to the printed circuit board. Referring now to Figure 5, it is schematically shown in cross-section that the second change of the lead 32 during the intermediate manufacturing stage is η 3 ... / in the intermediate & form. The lead 32 is shown in a state before it is bent into its final sinking positioning shape. The lead is - as shown in Figure 4. A similar shape of the lead 32 is shown. The lead is a pure 3-lead pad 36a and a thinned portion 37a. The lead 32a is opposite to the end pack 3, the second thicker portion 4, of the lead 塾3, at which point the lead μ is finally attached to the projection 33 at that point. Lead 32b is similar to lead turns except that there is no second thicker portion therein. That is, the thinned portion 37b may extend from the lead pad to the other end of the lead 32. It is also possible to understand the varying configuration of the leads. For example, the thickness of the thinned portion may vary relative to the thickness of the remainder of the lead or the thinned portion 37 may begin immediately after the lead turn 36. The example lead 32 shown in Figure 5 has a thinned portion that is approximately the turn of the remainder of the lead. As mentioned earlier, the material leads can be thinned on both sides. The proportion and position of the thinned portion may also differ from the example shown. Fig. 6 shows a state in which the leads 32 & and 321 are bent to form a lead frame after the portion of the positioning portion is lowered. The leads are shown bent in two opposite directions such that the ends of the leads are substantially in parallel planes. It should be understood that in alternative embodiments of the invention, the curvature and direction can be varied to provide a suitable connection between the lead pad 36 and the wafer. 18 200933852 Referring now to Figure 7, a portion of the semiconductor wafer package 30 of Figure 4 is schematically illustrated in cross-section, and a portion of the semiconductor wafer package of Figure 3 is shown. The chip package 30 is in accordance with the present invention. The chip package 2i is a conventional type. 5 ❹ 10 15 Ο 20 The illustrated areas 50a, 50b represent the leads 32, 23 and the resin layer %, ^

間層離分開的關鍵區域。於習知的晶片封裝體以中，該W 線框具有引線23等遍及其長度皆有一固定的厚度。此會造 成一樹脂漸變區。在本發明的某些實施例中，該包封材料 可包含-樹脂材料其含有一預定的填充微粒濃度。該等填 充微粒會影響該包封層的機械和熱特性。當在包封時，該 樹脂(含有填級粒)會紅該半導Μ置之表φ上可達到 的每個間隙中。若—間隙係小於該填充微粒的直徑，則大 夕數的該等填充微粒將會被阻止不能進入該間隙，因此該 間隙ν、會容裝樹脂和較小的填充微粒。此將形成—‘‘樹月旨毛 邊的漸變區，其會具有與該包封層的其餘部份不同的機械 和熱性質。此在機械和熱性質的改變會使一包封層之此區 域易於層分剝離。此—窄小的間隙會發生於習知類型的半 導體封裝體之所示區域5〇b處。相反地，該晶片封裳體3〇在 =曲處具有一薄化部份η延伸至該引線塾％的邊緣，該處 又有樹知毛邊。此會形成—機械性更穩定的晶片封裝體， 而較不會層分剥離。 么又’可看出該具有—薄化部份37之引線的弯曲半徑51a 古、於該沒有薄化部份的引線之彎曲半徑训。因此，該具 ?化縣之？丨線的封魏在該引線塾邊緣與該晶片邊緣 [.S 1 19 200933852 之間所占㈣長度52_會比該習知晶片封裝似的對應 測量值52b更’】、此會造成該封裝體内的空間之更有效率使 用，並因而能形成更小且更輕的晶片封裝體。 5 ο 10 15 ❹ 20 第8圖示出依據本發明之-可擇實施例的半導體晶片 封裝體6G之部份截面頂視圖。晶片61係被包封在樹脂層^ 内日9片61在其頂面上具有一陣列的凸體幻等接觸一陣列 的弓丨線64。有些引線64係被示出連接於多個凸體63，其會 改良來自晶片61的熱傳導1及該等引線64對晶片61的電 ί接。引線64具有如同第4圖所示的W封裝體之引線32的 溥化和彎曲部份等。 第9圖示出第4圖之晶片封裝體的另-變化例。在晶片 7^70中引輸_背_面，以編73的底面 :==_外部連接。但除此之外， 用、W'暴露在該封裝體·上的下沈定區75中， 、良來自該封裝體的熱傳導。類似於第8圖的封裝體， 體76。連接於—凸體％，而其它引線框係連接於單—凸 可適第1G圖，其係示出本發明的另—實施例，而 引線塾途。时體⑽包含錄的引線81各由 該弓丨線框85的_: 83'之一者，而接觸各凸體84。 之間形成―接橋姆會在該下沈定位區中的晶片83a_b 該等^日片^不出第1G圖的封裝體⑽之—截面圖。其可看出 係由於弓I線81的不同餘刻程度而被佈設在該封裝 20 200933852 體80内的不同水平處。在用於晶片83b之下沈定位腔穴中引 線81係被部份地蝕刻，而增加該腔穴的深度，並因而提高 晶片83b在所完成封裝體中的高度。其結果係該晶片83a的 底面會暴露，而晶片83b的底面不會暴露（即晶片83b會被樹 5 脂層86完全地包封）。 第12圖示出第4圖之半導體晶片封裝體儿的變化例，其 中引線32的f曲度已被改變，而使晶片叫皮完全地包封在 樹脂層34内。 ❹ 本發明的上述各實施例全都能提供優於習知技術的相 10同改良。藉著減少在彎曲區域中的引線厚度，則該封裝體 的尺寸得紐減小。在依據本發明所製成的晶片封裝體 中，已可看到減少10%的封裝體面積。且，一05mm至07mm 的封裝體高度減少亦已被觀察到。將該等引線連接於銅凸 體相較於使用導線接結的同等晶片封裝體會具有超過50% 15料觀電阻減降。在本發明之某些特定實施例中，該等引 © 纟的薄化#延伸至在晶片外部的引線塾處將會減少樹脂 毛邊，因而有助於防止層分剝離。 依據本發明之改良的半導體晶片封裝係可應用於-廣 泛的產品範圍，包括以雙極電晶體或UMOS電晶體為基礎 20的產品’而來提供改良的電特性，包括—減低的導通電阻。 又，依據本發明的半導體封裝能為個別晶片的共封裝提供 一種有效率的封裝方案。在發光用途中，該減小的封裝體 面積能夠提供更佳的每單位面積功率耗散。電感的減少能 提供改良的RF性能，此對例如在直接廣播衛星量放大器中 21 200933852 乃是特別有利的。 業人士輕易得知 本發明之進一步的修正和應用將可為專 【圖式簡單說明】 片封裝體 =1、示咅意地示出一習知形式的半導體晶片封裝體； 意地示出第1圖之半導體晶片封裝體的底面； 意地示出另，形式的半導體晶片封裝體; Ά截面不意地不出—依據本發明的半導體晶Separate key areas separated by layers. In conventional chip packages, the W-wire frame has leads 23 and the like having a fixed thickness throughout its length. This creates a resin gradient zone. In certain embodiments of the invention, the encapsulating material may comprise a resin material containing a predetermined fill particle concentration. The filling of the particles affects the mechanical and thermal properties of the encapsulating layer. When encapsulated, the resin (containing the fill-in particles) will be red in each of the gaps achievable on the semi-conducting table φ. If the gap is smaller than the diameter of the filled particles, the filled particles of the number of days will be prevented from entering the gap, so the gap ν will accommodate the resin and the smaller filled particles. This will result in a '' gradual change of the edge of the tree, which will have different mechanical and thermal properties than the rest of the envelope. This change in mechanical and thermal properties tends to facilitate delamination of this region of an encapsulation layer. This - a narrow gap can occur at the indicated area 5〇b of a conventional type of semiconductor package. Conversely, the wafer sealing body 3 has a thinned portion η extending to the edge of the lead 塾% where there is a burr. This results in a more mechanically stable chip package that is less delaminated. It can be seen that the bending radius 51a of the lead having the thinned portion 37 is ancient, and the bending radius of the lead having no thinned portion is taught. So, what about the county? The seal of the 丨 line is at the edge of the lead 与 and the edge of the wafer [.S 1 19 200933852 (4) length 52_ will be more than the corresponding measured value 52b of the conventional chip package], which will cause the package The space in the body is used more efficiently, and thus a smaller and lighter chip package can be formed. 5 ο 10 15 ❹ 20 Fig. 8 is a partial cross-sectional top view showing a semiconductor wafer package 6G according to an alternative embodiment of the present invention. The wafer 61 is encapsulated in a resin layer. The inner sheet 9 has an array of convex phantoms that are in contact with an array of bowing lines 64 on its top surface. Some of the leads 64 are shown coupled to a plurality of protrusions 63 which improve the thermal conduction 1 from the wafer 61 and the electrical connection of the leads 64 to the wafer 61. The lead 64 has a deuterated and bent portion of the lead 32 of the W package as shown in Fig. 4. Fig. 9 is a view showing another variation of the chip package of Fig. 4. The _ back_face is introduced in the wafer 7^70 to align the bottom surface of the 73: ==_ external connection. However, in addition to this, W' is exposed to the heat sinking region 75 of the package, and heat conduction from the package is good. Similar to the package of Figure 8, body 76. Connected to the % of the convex body, and the other lead frames are connected to the single-convex 1G, which shows another embodiment of the present invention. The body (10) includes recorded leads 81 each of which is one of _: 83' of the bow frame 85 and contacts each of the projections 84. A wafer 83a_b in which the junction is to be formed in the sinking positioning region is formed as a cross-sectional view of the package (10) of the 1Gth image. It can be seen that the different levels of the bow line I 81 are disposed at different levels within the body 80 of the package 20 200933852. The lead 81 is partially etched in the recessed positioning cavity for the wafer 83b to increase the depth of the cavity and thereby increase the height of the wafer 83b in the finished package. As a result, the bottom surface of the wafer 83a is exposed, and the bottom surface of the wafer 83b is not exposed (i.e., the wafer 83b is completely encapsulated by the resin layer 86). Fig. 12 is a view showing a modification of the semiconductor chip package of Fig. 4, in which the curvature of the lead 32 has been changed, so that the wafer is completely encapsulated in the resin layer 34.上述 All of the above embodiments of the present invention can provide improvements over the prior art. By reducing the thickness of the leads in the curved regions, the size of the package is reduced. In the chip package made in accordance with the present invention, a 10% reduction in package area has been seen. Moreover, a reduction in the height of a package of 05mm to 07mm has also been observed. Connecting the leads to the copper bumps will have a material resistance reduction of more than 50% compared to an equivalent wafer package bonded using wires. In some particular embodiments of the invention, the thinning of the leads 延伸 to the lead turns on the outside of the wafer will reduce the resin burrs and thus help prevent delamination. The improved semiconductor chip package in accordance with the present invention can be applied to a wide range of products, including products based on bipolar transistors or UMOS transistors, to provide improved electrical characteristics, including - reduced on-resistance. Moreover, the semiconductor package in accordance with the present invention provides an efficient packaging solution for co-packaging of individual wafers. In luminescent applications, this reduced package area provides better power dissipation per unit area. The reduction in inductance provides improved RF performance, which is particularly advantageous, for example, in direct broadcast satellite amplifiers 21 200933852. It will be readily apparent to those skilled in the art that further modifications and applications of the present invention will be described as a simplified description of a package, a semiconductor package in a conventional form; The bottom surface of the semiconductor chip package; intentionally showing another form of the semiconductor chip package; the cross section is unintentional - the semiconductor crystal according to the present invention

第5圖係以截面示意地示出第4圖的半導體晶片封裝體 10在製造之一中間階段時之二可擇的部件形狀； 第6圖係示出第5圖的部件在另—製造中間階段之後的 第7圖係以截面示意地示出第4圖之半導體晶片封裝體 I部份，及第3圖之半導體晶片封料的―部份，以容它 15 們能被併排地比較； 〇 以圖係示意地示出-依據本發明之一可擇實施例的 半導體晶片封裝體； 第9圖係示意地示出一依據本發明之又另— 例的半導體晶片封裝體； 20 第10圖係示意地示出本發明的另一實施例其可商人； 多晶片用途； 載面圖；及 封装體之另 第11圖係示意地示出第10圖的封褒體之_ 第12圖係示意地示出第4圖的半導體晶片 一修正例。 200933852 【主要元件符號說明】 1，21...習知封裝體 31，6卜 73，83a、b...晶片 2，22，85".引線框 34. · ·包封層 3...晶片墊 36...第一部份 4，24，71，82...引線墊 36a、b…引線墊部份 5，20…半導體晶片 37a、b.. ·薄化部份 6...結線 37...第二部份 7，26，62，86...樹脂層 38...階狀變化處 8...侧面 40…第二部份 9，10，27，35，72...底面 50a、b...層離區域 23，32，64，74，81 …引線 51a、b...彎曲半徑 25，33，63，76，84…凸體 52a、b…長度 28...彎離區 75...下沈定位區 30，60，70，80...封裝體Fig. 5 is a cross-sectional view schematically showing the alternative component shapes of the semiconductor chip package 10 of Fig. 4 in an intermediate stage of manufacture; Fig. 6 is a view showing the components of Fig. 5 in the middle of another manufacturing Figure 7 after the stage schematically shows a portion of the semiconductor chip package portion I of Fig. 4 and a portion of the semiconductor wafer package of Fig. 3 in a cross section to allow them to be compared side by side; BRIEF DESCRIPTION OF THE DRAWINGS A semiconductor chip package in accordance with an alternative embodiment of the present invention is schematically illustrated; FIG. 9 is a schematic view of a semiconductor chip package in accordance with still another embodiment of the present invention; The figure schematically shows another embodiment of the present invention, which can be used by a merchant; a multi-wafer use; a carrier map; and another 11th view of the package, which schematically shows the package of FIG. A modified example of the semiconductor wafer of Fig. 4 is schematically shown. 200933852 [Description of main component symbols] 1, 21... conventional package 31, 6b 73, 83a, b... wafer 2, 22, 85 " lead frame 34. · · encapsulation layer 3... Wafer pad 36...first portion 4, 24, 71, 82... lead pad 36a, b... lead pad portion 5, 20... semiconductor wafer 37a, b.. thinned portion 6... The junction line 37...the second portion 7,26,62,86...resin layer 38...the step change 8...the side 40...the second part 9,10,27,35,72. .. bottom surface 50a, b... delamination area 23, 32, 64, 74, 81 ... lead 51a, b... bending radius 25, 33, 63, 76, 84... convex body 52a, b... length 28. ..Blinding area 75...sinking positioning area 30,60,70,80...package

23twenty three

Claims (1)

200933852 1. 、申請專利範圓·· 一種半導體晶片封裝邀，包含 —半導體晶片； 引線框含有至少一引線；及 Ο 10 15 ❹ 20 一包封層至少部份地包封該半導體晶片和診 其中該引線包含一第一部份界定一弓丨線 部份地暴露難該封裝體之—外表面處。及1 =至少 該第-部份朝向該半導體晶片延伸，而將^ 份由 之一表面部份電連接於該引線框墊，且其中讀第體晶片 具有-第-厚度，而該第二部份包含—薄化部、部灸 化部份具有-厚度小於該第—厚度，該引線該薄 曲部份，且其中該薄化部份包含該贊曲部份的至含一彎 2. 如申請專利範圍第旧之半導體晶片封裝體，少—部份。 化部份包含該引線的一部份，於該部份 1中該薄 面被減少厚度。 緣會由其〜 3. 如申請專利範圍第1項之半導體晶片封震體 化部份包含該引線的一部份，於該部份該’其中該薄 面被減少厚度。 Λ線會由其兩 4. 如申請專利範圍第1、2或3項之半導體晶片、 中該彎曲部份係完全在該薄化部份内。曰曰封裝體，其 5. 如申請專利範圍第卜2、3或4^半導體晶 其中該引線係僅在該彎曲部份内被薄化。 裝體， 6. 如申請專利範圍第1、2、3、4“tS 次5項之半導體晶片封骏 框 線 24 200933852 體，其中該薄化部份係由該引線墊伸出。 7. 如申請專利範圍第6項之半導體晶片封裝體，其中該引 線墊與該薄化部份之間的接合處會在該封裝體外部形 締！丨線厚度之-階狀變化處，赠該包封層終結在該 5 階狀變化處而鄰接於該引線墊之一暴露部份。 8. 如申請專利範圍第卜2、3、4、5、6或7項之半導體晶 片封㈣’其中該引線包含—沿—第—方向的f曲部及 〇 —沿—第二方㈣f曲部，喊該㈣框界定__下沈定 位區可適於容納該晶片。 10 9·如申請專利範圍第8項之半導體晶片封裝體，其中該引 線框係在該下沈定位區的至少一部份中被薄化。 说如申請專利範圍第卜卜^^卜八喊轉之半 導體晶片封裝體，其中該等引線不會實質地突出超過該 晶片封裝體的外部。 15 U·如申請專利範圍第1、2、3、4、5、6、7、8、9或1〇項 © 之半導體晶片封裝體，其中該引線框的某些部份係暴露 在該晶片封裝體的上表面處。 12·如申請專利範圍第卜2、3、4、5、6、7、8、9、10或 11項之半導體晶片封裝體，包含有多數的引線。 20 13.如中請專利範圍第 1、2、3、4、5、6、7、8、9、1 〇、 11或12項之半導體晶片封裝體，包含有二或更多個晶片。 14·如申請專利範圍第1、2、3、4、5、6、7、8、9、10、 U、12或13項之半導體晶片封裝體，其中該或各晶片係 被該樹脂層完全地包封。200933852 1. Patent application for a semiconductor wafer package, comprising: a semiconductor wafer; the lead frame comprising at least one lead; and Ο 10 15 ❹ 20 an encapsulation layer at least partially encapsulating the semiconductor wafer and The lead includes a first portion defining a bow line that is partially exposed to the outer surface of the package. And 1 = at least the first portion extends toward the semiconductor wafer, and the portion is electrically connected to the lead frame pad by a surface portion, and wherein the read first wafer has a -th thickness, and the second portion The portion includes a thinned portion, a moxibustion portion having a thickness smaller than the first thickness, the thin portion of the lead, and wherein the thinned portion includes the curved portion to include a bend 2. The patented semiconductor chip package is the first to be patented. The portion includes a portion of the lead in which the surface is reduced in thickness. The edge of the semiconductor wafer sealing body portion of claim 1 includes a portion of the lead wire in which the thin surface is reduced in thickness. The twisted wire will be two of them. 4. For the semiconductor wafer of claim 1, 2 or 3, the curved portion is completely within the thinned portion. A ruthenium package, which is as disclosed in the patent specification No. 2, 3 or 4, wherein the lead is thinned only in the bent portion. Mounting body, 6. For example, the patented range 1, 2, 3, 4 "tS times 5 semiconductor wafer sealing frame line 24 200933852 body, wherein the thinned portion is extended by the lead pad. The semiconductor chip package of claim 6 , wherein the joint between the lead pad and the thinned portion is formed outside the package; the thickness of the wire is changed in a step-like manner, and the package is provided The layer terminates at the 5th step change adjacent to one of the exposed portions of the lead pad. 8. The semiconductor wafer package (4) of claim 2, 3, 4, 5, 6 or 7 wherein the lead Including - along the - direction of the f-curve and 〇----the second (four) f-curve, shouting the (four) frame definition __ sinking the positioning area can be adapted to accommodate the wafer. 10 9 · as claimed in the scope of the 8th The semiconductor chip package of the semiconductor chip package, wherein the lead frame is thinned in at least a portion of the sinking positioning region. The semiconductor chip package is as claimed in the patent application scope. The leads do not substantially protrude beyond the outside of the chip package. 15 U·如申Patent No. 1, 2, 3, 4, 5, 6, 7, 8, 9, or 1 of the semiconductor chip package, wherein portions of the lead frame are exposed on the upper surface of the chip package 12. A semiconductor chip package as claimed in the scope of claim 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11. Contains a large number of leads. 20 13. The semiconductor chip package of item 1, 2, 3, 4, 5, 6, 7, 8, 9, 1 , 11 or 12 includes two or more wafers. A semiconductor chip package of item 2, 3, 4, 5, 6, 7, 8, 9, 10, U, 12 or 13 wherein the or each wafer is completely encapsulated by the resin layer. 25 200933852 15.如中請專利範圍第1、2、3、4、5、6、7、8、9、1()、 U、12、13或14項之半導體晶片封裝體，其中該晶片或 該等晶片之至少一者的至少部份底部係暴露在該晶片 封裝體的底部處。 5 Μ.如申請專利範圍第15項之半導體晶片封裝體，其中該晶 片或該等晶片之至少一者的暴露部份係被覆層在一可 焊接材料中。 Ο 17 ‘如中請專利範圍第 1、2、3、4、5、6、7、8、9、1 〇、 Η、12、13、14、15或16項之半導體晶片封裝體，其中 1〇 至少有一導電凸體會被提供在該或各晶片的上表面 上，且該或各引線會與至少一凸體電接觸，而使該晶片 經由該凸體電連接於該引線。 18.如申請專利範圍第17項之半導體晶片封裝體，其中該或 各引線係以多數個凸體電連接於該晶片。 19·種製造一半導體晶片封裝體的方法，該方法包含： 〇 提供一半導體晶片； 提供一引線框含有至少一引線；及 將該半導體晶片的至少一部份和該引線框的至少 一部份包封在一包封層内； 2〇 其中該引線包含一第一部份具有一第一厚度並界 定一引線框墊至少部份地暴露在該封裝體一外表面 處’及一第二部份由該第一部份朝向該半導體晶片延 伸，而將該半導體晶片之一表面部份電連接於該引線框 墊；且其中該方法更包含：25 200933852 15. A semiconductor chip package as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 1 (), U, 12, 13 or 14 wherein the wafer or At least a portion of the bottom of at least one of the wafers is exposed at the bottom of the wafer package. 5. The semiconductor chip package of claim 15 wherein the exposed portion of the wafer or at least one of the wafers is coated in a solderable material. Ο 17 'In the patent range 1, 2, 3, 4, 5, 6, 7, 8, 9, 1 〇, Η, 12, 13, 14, 15 or 16 of the semiconductor chip package, 1 At least one conductive bump is provided on the upper surface of the or each wafer, and the or each lead is in electrical contact with at least one of the bumps to electrically connect the wafer to the lead via the bump. 18. The semiconductor chip package of claim 17, wherein the or each lead is electrically connected to the wafer by a plurality of protrusions. 19. A method of fabricating a semiconductor chip package, the method comprising: providing a semiconductor wafer; providing a leadframe comprising at least one lead; and at least a portion of the semiconductor wafer and at least a portion of the leadframe Encapsulating in an encapsulation layer; wherein the lead includes a first portion having a first thickness and defining a lead frame pad at least partially exposed to an outer surface of the package and a second portion And extending from the first portion toward the semiconductor wafer, and electrically connecting one surface portion of the semiconductor wafer to the lead frame pad; and wherein the method further comprises: 26 200933852 薄化該第二部份的至少一部份以形成一薄化部 份，而使該薄化部份比該第一部份更薄；及 彎曲該薄化部份的至少一部份以形成該引線的第 二部份之一彎曲部份的至少一部份。 5 Ο 10 15 ❹ 20 20. 如申請專利範圍第19項之製造一半導體晶片封裝體的 方法，其中薄化該第二部份的至少一部份以形成一薄化 部份乃包含由該引線的一面減少該引線的厚度。 21. 如申請專利範圍第19項之製造一半導體晶片封裝體的 方法，其中薄化該第二部份的至少一部份以形成一薄化 部份乃包含由該引線的兩面減少該引線的厚度。 22. 如申請專利範圍第19、20或21項之製造一半導體晶片封 裝體的方法，更包含僅彎曲該薄化部份中的引線。 23. 如申請專利範圍第19、20、21或22項之製造一半導體晶 片封裝體的方法，更包含僅薄化該彎曲部份中的引線。 24. 如申請專利範圍第19、20、21或22項之製造一半導體晶 片封裝體的方法，其中該薄化部份係由該引線墊伸出。 25. 如申請專利範圍第24項之製造一半導體晶片封裝體的 方法，其中該引線墊與該薄化部份之間的接合處會在該 封裝體外部形成該引線厚度之一階狀變化處，以使該包 封層終結在該階狀變化處而鄰接於該引線墊之一暴露 部份。 26. 如申請專利範圍第19、20、21、22、23、24或25項之製 造一半導體晶片封裝體的方法，其中彎曲該引線的至少 一部份以形成一彎曲部份乃包含沿一第一方向彎曲該 27 200933852 帛一方向彎曲該弓丨線，而使該引線框界定一 下沈定位區可適於容納該晶片。 Α如申請專利範圍第19、2()、21、22、23、24、25或26項 之製造-半導體晶片封裝體的方法，更包含薄化在該下 沈定位區之至少一部份中的弓I線框。 %如申請專利範圍第19、2〇、21、22、23、24、25、26或 Ο 1026 200933852 thinning at least a portion of the second portion to form a thinned portion such that the thinned portion is thinner than the first portion; and bending at least a portion of the thinned portion Forming at least a portion of the portion of the second portion of the lead. Ο 10 15 ❹ 20 20. The method of manufacturing a semiconductor chip package according to claim 19, wherein thinning at least a portion of the second portion to form a thinned portion comprises the lead One side reduces the thickness of the lead. 21. The method of fabricating a semiconductor chip package of claim 19, wherein thinning at least a portion of the second portion to form a thinned portion comprises reducing the lead from both sides of the lead thickness. 22. The method of manufacturing a semiconductor wafer package of claim 19, 20 or 21, further comprising bending only the leads in the thinned portion. 23. The method of fabricating a semiconductor wafer package of claim 19, 20, 21 or 22, further comprising thinning only the leads in the bent portion. 24. A method of fabricating a semiconductor wafer package as claimed in claim 19, 20, 21 or 22, wherein the thinned portion is extended by the lead pad. 25. The method of manufacturing a semiconductor chip package according to claim 24, wherein a junction between the lead pad and the thinned portion forms a step change of the thickness of the lead outside the package So that the encapsulation layer terminates at the step change and is adjacent to an exposed portion of the lead pad. 26. The method of fabricating a semiconductor chip package of claim 19, 20, 21, 22, 23, 24 or 25, wherein bending at least a portion of the lead to form a curved portion comprises The first direction bends the 27 200933852 to bend the bow line in a first direction, so that the lead frame defines a sinking positioning area that can be adapted to receive the wafer. For example, the method of manufacturing a semiconductor chip package of claim 19, 2 (), 21, 22, 23, 24, 25 or 26 further includes thinning in at least a portion of the sinking positioning area Bow I wireframe. %If the patent application scope is 19, 2, 21, 22, 23, 24, 25, 26 or Ο 10 20 27項之製造-半導體晶片封裝體的方法，其中該等引線 不會實質地突出超過該晶片封I體的外部。 29.如申請專利範圍第 19、2〇、21、22、23、24、25、26、 27或28項之製造-半導體晶片封裝體的方法，更包含暴 露該引線框在該晶片封裝體之上表面處的部份。 见如申請專利範圍第19、20、21、22、23、24、25、％、 27、28或29項之製造-半導體晶片封裝體的方法，包含 提供多數的引線。 31.如中請專利範圍第 19、20、21、22、23、24、25、26、 27、28、29或30項之製造一半導體晶片封裝體的方法， 包含提供二或更多個晶片。 32·如申請專利範圍第 19、20、21、22、23、24 ' 25、26 ' 27、28、29、3G或31項之製造—半導體晶片封裝體的方 法，更包含將該或各晶片完全地包封在該樹脂層中。 33·如申請專利範圍第 19、20、21、22、23、24、25、26、 27、28、29、30、31或32項之製造一半導體晶片封裝體 的方法，更包含將該晶片或該等晶片之至少一者的底部 之至少一部份暴露在該晶片封裝體的底部處。 28 200933852 34.如申請專利範圍第33項之製造一半導體晶片封裝體的 方法，更包含將該晶片或該等晶片之至少一者的暴露部 份覆層在一可焊接材料中。 35·如申請專利範圍第 19、20、21、22、23、24、25、26、 5 27、28、29、30、31、32、33或34項之製造一半導體晶 片封裝體的方法，更包含在該或各晶片的上表面上提供 至少一導電凸體，以使該或各引線與至少一凸體電接 觸，而將該晶片電連接於該引線。 36. 如申請專利範圍第35項之製造一半導體晶片封裝體的 10 方法，更包含以多數個凸體將該或各引線電連接於該晶片。 37. 如申請專利範圍第 19、20、21、22、23、24、25、26、 27、28、29、30、31、32、33、34、35或36項之製造一 半導體晶片封裝體的方法，其中薄化該第二部份的至少 一部份以形成一薄化部份的步驟乃包含部份地蝕刻該 15 第二部份的至少一部份來減少其厚度。 38. —種半導體晶片封裝體，實質上係參照所附圖式如前所 描述者。 39. —種製告一半導體晶片封裝體的方法，實質上係參照所 附圖式如前所描述者。 29A method of fabricating a semiconductor wafer package of claim 27, wherein the leads do not substantially protrude beyond the exterior of the wafer package. 29. The method of fabricating a semiconductor chip package of claim 19, 2, 21, 22, 23, 24, 25, 26, 27 or 28, further comprising exposing the lead frame to the chip package The part at the upper surface. See the method of fabricating a semiconductor-semiconductor package as claimed in claim 19, 20, 21, 22, 23, 24, 25, %, 27, 28 or 29 of the patent application, including providing a plurality of leads. 31. A method of fabricating a semiconductor chip package according to claim 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 or 30 of the patent, comprising providing two or more wafers . 32. A method of manufacturing a semiconductor chip package as claimed in claim 19, 20, 21, 22, 23, 24 '25, 26 '27, 28, 29, 3G or 31, further comprising the or each wafer It is completely encapsulated in the resin layer. 33. A method of manufacturing a semiconductor chip package as claimed in claim 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 or 32, further comprising the wafer Or at least a portion of the bottom of at least one of the wafers is exposed at the bottom of the chip package. The method of manufacturing a semiconductor chip package of claim 33, further comprising coating the exposed portion of at least one of the wafer or the wafers in a solderable material. 35. A method of manufacturing a semiconductor chip package as claimed in claim 19, 20, 21, 22, 23, 24, 25, 26, 5 27, 28, 29, 30, 31, 32, 33 or 34, Further comprising providing at least one conductive protrusion on the upper surface of the or each wafer such that the or each lead is in electrical contact with at least one of the protrusions to electrically connect the wafer to the lead. 36. The method of fabricating a semiconductor chip package of claim 35, further comprising electrically connecting the or each lead to the wafer with a plurality of protrusions. 37. Manufacturing a semiconductor chip package as claimed in claim 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 or 36 The method of thinning at least a portion of the second portion to form a thinned portion comprises partially etching at least a portion of the second portion of the 15 to reduce thickness thereof. 38. A semiconductor chip package substantially as hereinbefore described with reference to the drawings. 39. A method of making a semiconductor chip package substantially as hereinbefore described with reference to the accompanying drawings. 29
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GB2451077A (en) 2009-01-21
WO2009010716A1 (en) 2009-01-22

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