TWI234251B - Ball grid array package with stacked center pad chips and method for manufacturing the same - Google Patents

Ball grid array package with stacked center pad chips and method for manufacturing the same Download PDF

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Publication number
TWI234251B
TWI234251B TW091137746A TW91137746A TWI234251B TW I234251 B TWI234251 B TW I234251B TW 091137746 A TW091137746 A TW 091137746A TW 91137746 A TW91137746 A TW 91137746A TW I234251 B TWI234251 B TW I234251B
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Taiwan
Prior art keywords
package
circuit board
ball
wafer
pin
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TW091137746A
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English (en)
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TW200306652A (en
Inventor
Hyung-Gil Baik
Ki-Ill Moon
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Hynix Semiconductor Inc
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Publication of TW200306652A publication Critical patent/TW200306652A/zh
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Publication of TWI234251B publication Critical patent/TWI234251B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

1234251 五、發明說明（1) 【本發明所屬之技術領域】 本發明係有關半導體封 ^ Λ 以上的中心腳位型半導體；以：言：，為有關將二個 列（fine ball grid array .片F =二疊層而實現微細球格式陣 位晶片的疊層球格式陣二= 【先前技術】 術，㊁”封裝(叩―)技 同:;因r製品的高性』受著限 之作更多數的半導體封裝而持續地努力著。在此努^ 的一％即中係提案有所謂的"疊層封裝（stack pack 。 ，層^係將相同大小及相同機能的記憶晶 使記憶容篁增大’或將彼此不同大小及機能的各種類型的‘ 導體晶片予以組裝成一個封裝’以使製品的性能及效率性能 予以最大化者。疊層封裝係依欲適用的製品，製造會社 素使得種類非常多樣化。先行技術的疊層封裝之一 1圖所例示。 本戈弟 第1圖所示之疊層封裝1 〇係將個別封裝丨丨、i 2予以聂 的封裝疊層式之TSOP (薄小外形封裝）（thin smaU 〇υ；Ππ package)類型。在第1圖之疊層封裝1〇中，各自的個別封裝 1 1、1 2係使用内藏有一個一個半導體晶片i 3的L〇c 、 (lead-on-chip)(在晶片上的引腳）導線架（leaci f rame) 導線架之内部引腳14係依粘著帶15粘著在半導體晶片13的上 部面且依金屬導線1 6被電性連接。疊層的個別封裳11、1 2係
1234251 五、發明說明（2) 使用7 : Ϊ的連接用引腳1 7而彼此電性連接。此時’連接用 腳17接&於各導線架的外部引腳18 ^ 連接端子。 π立曰訂衣1 0的外部 但J ?匕種類型的疊層封裝10係封裝的組 度：，對於在要求小型化，薄型化的資訊通信機器等 的適用上係有其困難。且因使用導線架1 4、1 7、；1 8，所以統 不適合於高速元件掣σ ，出 所从並 墓_曰Μ4L I 口口由方；自封裝地點到上部封裝12的丰 導脰日日片1 4為止的路徑係較之於封裝地點至下部封 導體晶片13為長之故、所以電氣特性差。 、 半 n!ΐ且：半導體封裝的表面封裝面積成為最小化，且電 ϊ ί ϊ t長度成為最小化以提升電氣特性等等為目的，俜接 案出，外部連接端子上使用錫球(solder bal 式二 列（ball grid町ay ;BGA)封裝。基本上，係按照^格式^ 列封裝之形態在封裝的内部疊層半導體晶片之所謂的"/ 的疊層球格式陣列封裝”係如第2圖所示。 ^第2圖所示般，晶#的疊層球格式陣列封裝2〇係在封身 模27的内部將個別半導體晶片23 , 24予以疊層之疊層式曰 ’且利用印刷電路基板21和錫球28，以取代導線架。在= 有配線22的印刷電路基板21上，使㈣著劑25以㈣下 導體晶片23，且在下部半導體晶片23上係枯著上部 片24。各半導體晶片23、24係依金屬導線26而與印刷電路2 板2 1的配線22作電性連接，在印刷電路基板2丨的下部面形成 複數個錫球28而與配線22作電性連接，成為封裝2〇的外部連 接端子。
第8頁 1234251 五、發明說明（3) 使用=二種::型之晶片的疊層球格式陣列封裝20係僅能 之半導體曰n腳位（Slde pad)型半導體晶片π。在如同dram 個擔任Γ:卜動面(active surface)上’雖然形成多數 但^在日 輸入輸出的晶片腳位（chip pad)23a、24a， 腳位於近來高速元件之落實具有其優點，所以晶片 長的問題，所：乃ΐ古層困難及金屬導線的長度變 晶片的缺點〇 7 此使用此類型的中心腳位型半導體 的上。而裝20的類型係因熱應力集中在封裝 而產生封裝_^warpage)現象。 導體晶片來際上係僅利用1個中心腳位型、 曰η木貫現球格式陣列封奘。 式陣列封裝例係如圖3所示。、有關中心腳位晶片的球格 如第3圖所示，中心腳位日 形成有晶片腳位32a的半導體曰曰:$格式陣列封裝30係’ 基板31後，透過金屬導線33將曰曰二曰主動面予以枯著在電 J性連接。半導體晶片32和金屬㊁：曰;片32和電路基板31作 4，作成在電路基板31形成有係受封裝模34所保 球格式陣列封裝之形態。 、、σ卩連接端子之錫球3 5的 【本發明之内容】 如以上之說明，疊層封裝 球格式陣列封裝，以及Φ^、 1234251 一1 _ ___ 五、發明說明（4) 腳位型半導體晶片雖 以上3個要求之封 /、有自身的優點，但是在同時滿足 工程安全性方面來、考旦’J糸了士解到在其構造方面或製造成本』 因此，本發q 里係具有相當程度的困難。 和微細球袼式陣產生，疊層封裝的優點 之全部優點的新類型^ ^俗站以及中心腳位型半導體晶片等 及其製造方法。、 中心腳位晶片的疊層球格式陣列封裝 自晶Si 提供-種，疊層包含有沿各 ;導體晶片，以實個中心腳位型 腳位晶片的疊層球格式陣列、二，。在本發明之中心 晶:主動面彼此相互面對般、枯：：：二導體晶片係以 個“腳位係透過金屬導線各路基板’ 基板，上下部電路基板 电注連接至上下部電路 作電性連接，i部電路基^且透過形成在其間的凸塊 板之兩側端部分係露出二封事：d裝模内’下部電路基 在本發明之中心腳位曰u:下部側為其特徵。 部電路基板係以具柔軟性：絕緣；陣列封裝中，下 露出的兩側端部分可形成複數個錫ί成且在：部電路基 基板之兩側端部分接合印刷踢衣且，在下部電路 部面可形成複數個錫球。又，τ:板，在印刷電路基板之下 成。 σ卩電路基板係可以導線架構 又，本發明係提供一種，疊声勺人 中央所形成的複數晶片腳位夕t二^含有沿各自晶片主動面 個中心腳位型半導體晶片， 弟10頁 五、發明說明（5) = = = 之製造方法。本發明之製造方法 晶片各自粘著至上下部am::對般地將複數個半導體 數個晶片腳位各自電性連# ^ =驟；透過金屬導線將複 凸塊而被電性連二路基板之步驟；透過 兩側端部分在封裝模内，且下部電路基板在 構成。出方、封裝核的下部側般地形成封I模等步驟所 又’本發明之製造方法係包含 板帶片之步驟，該上下部電路；；ί h、供-上下部電路基 以一定間隔形成，基板你、土 f π片係，各個介層孔和窗 的圖案形成，且形：多數個：配：、以及連接腳位係以-定 伸至該下部電路下部電路基板，而該配線係延 接腳位形成層孔内部’且形成球陸，且在該連 枯著步驟’係該複數個晶片腳位透過該窗 於該電路基板帶片之各電路基板㈣該半導二^ 、—二=導線將露出之複數個晶片腳位予以；：連接至兮 複數個基板腳位的步驟； 电T生運接至5哀 „接步驟，係該半導體晶片彼 上下部電路基板彼此枯著 面對觳地使該 作電性連接； 丘依J凸塊將该上下部電路基板 陸，：ί 該介層孔按壓該下部電路基板之該球 陸而L伸至違下部電路基板的介層 般地使該球陸露出以形成 線朝下方％曲 1234251 "-----— 五、發明說明（6) 在該球陸形成複數個錫球之步驟； 由該電路基板帶W及 此時，形成封裝模：牛：：封裝予以分離的步驟。 模製裝置的鑄孔内般地二:：下：：各自的電路基板位在 上下部鑄模所構成之模製】 = 路；板f片提供於以 球陸抵接該下部鑄模般地，使护成=兮，以下σ卩電路基板的 透過該電路基板帶片 來二；士部鑄模之加壓部、 並硬化==將液狀模製樹脂注入該鑄孔内，使 A更^以形成该封裝模等之步驟為較佳。 便 考針lt ^ t明的目的和其他特徵以及優點等等係可參 發明較佳實施例的說明而更明確。 【發明之實施方式】 例。：：件=件之圖面以詳細地說明本發明之較佳實施 解，係多=部份的構成要素中，為了有助於明確理 其實際大^ : β面绔張地表示且概略地圖示，並未全部反映 (第1實施例 故斗ΐ4圖h表不本發明第1實施例之中心腳位晶片的疊層球 1ΐ 2 ί裝的剖面圖。參考第4圖，其係將二個中心腳位 3 ¥肢晶片1 0 2、1 0 4予以疊層以實現微細球格式陣列封裝 半V體晶片1 〇 2、1 〇 4的晶片腳位1 0 6、1 0 8係沿著晶片主 動面中央而形成，二個半導體晶片102、104係以晶片主動面 為彼此相互面對般地各自被粘著在上下部電路基板11 2、 第12頁 1234251 五、發明說明（7) ----- 122。半導體晶片1〇2、1〇4的晶片腳位1〇6、1〇8係透過金屬 導線130而各自被電性連接至上下部電路基板112、122。彼 此被接合的上下部電路基板1 12、1 22係透過形成在其間的凸 塊140而被電性連接。上部電路基板112係具有與半導體晶片 104幾乎類似的大小，且完全包含在封裝模15〇内，下部電路 基板122係’其兩側端部分被露出於封裝模150的下部側。在 露出的下部電路基板122上形成複數個錫球16〇以作為封裝 1 0 0的外部連接端子來作用。 本實施例之封裝1 〇 〇係依如下之方法所製造。由以下所 說明之製造方法可使封裝的構造更加明確。第5圖至第8圖係 表示第4圖所圖示之中心腳位晶片的疊層球格式陣列封裝的 製造方法之工程圖。 首先，如第5圖的剖面圖所示，在上下部電路基板Η?、 1 2 2上粘著各自半導體晶片1 〇 4、1 0 2之後，與金屬導線丨3 〇連 接。如第6圖之平面圖所示般，上下部電路基板丨丨2、1 2 2係 各自以電路基板帶片（strip) U0、120形態形成。 ^電路基板帶片1 1 〇、1 2 0係，在捲筒（r e e 1)形態的絕緣薄 膜’以一定間隔形成介層孔（h〇le)丨n、121及窗 (w i n d 〇 w) 11 3、1 2 3，基板腳位 1 1 4、1 2 4，配線 11 5、1 2 5、 128 ’連接腳位Π6、126，以及球陸（ball land) 127係一定 圖案形成，以形成各自的電路基板112、122。不同於上部電 路基板帶片110，下部電路基板帶片120之特徵為，配線！ 延伸至介層孔1 2 1的内部且球陸1 2 7被形成。絕緣薄膜係以具 柔軟性之聚合物（polymer)材質所成，基板腳位1 14、1 24，
第13頁 1234251 --------1--------- - 五、發明說明（8) 配線1 1 5、1 2 5、1 2 8，連接腳位11 6、丨2 6，以及球陸1 2 7係以 銅所構成。 在電路基板帶片110、120之各電路基板n2、122上粘著 有半導體晶片1 0 4、1 0 2，各半導體晶片！ 〇 4、1 〇 2的晶片腳位 10Θ、108係，透過電路基板帶片、ι2〇的窗113、i23而露 出於外部。露出的晶片腳位丨〇 6、1 〇 8係依金屬導線} 3 〇而與 基板腳位1 1 4、1 2 4作電性連接。此外，在第5圖及第6圖並未 圖不，在上下部電路基板112、122之任一單方或兩侧的連接 腳位1 1 6、1 2 6上，形成有使上下部電路基板丨丨2、1 2 2作電性 連接的凸塊（第7圖的1 4 0 )。可在連接腳位丨丨6、1 2 6上鍍錫以 取代凸塊。 然後’如第7圖之剖面圖所示，半導體晶片丨〇 2、1 〇 4係 彼此相互面對般地使上下部電路基板丨丨2、1 22彼此粘著。上 下部電路基板11 2、1 2 2係，藉由施加熱及壓力而彼此粘接且 依凸塊140作電性連接。第7圖係僅圖式了1個上下部電路基 板112、122，而在第6圖所圖示之電路基板帶片11〇、12〇的 狀態下作枯接為較佳。 米占著’ 一邊按壓下部電路基板一邊進行模製工程。如第 8圖所示，彼此粘著的上下部電路基板帶片丨丨〇、1 2 〇係，被 置於以上下部鑄模220、210所構成的模製裝置内，此時，枯 著有半導體晶片102、104之各自的電路基板112、122係，位 在換製裝置之鑄孔（cavity )23〇内。且，由於形成在上部镑 模220的加壓部222係透過電路基板帶片11()、ι2〇的介層孔 m、121而按壓下部電路基板122之球陸127，所以延伸至下
1234251 五、發明說明（9) ' - 部電路基板122的介層孔121内之配線ι28係成為朝下方彎曲' 且球陸127成為抵接下部鑄模210。 士在此種狀態下，透過注入口（未圖示）將液狀模製樹脂注 入鑄孔23 0内之後使其硬化，則形成如第4圖所示之封裝模 150，且下部電路基板122之球陸127係露出於封裝模15〇的下 部侧。接著在露出於外部的球陸丨27上形成錫球16〇，且由電 路基板f片11 〇、12 〇，將各自複數個個別封裝丨〇 Q作分離。 (第2實施例） 、第9圖係表示本發明第2實施例之中心腳位晶片的疊層球 格式陣列封裝3 〇 0的剖面圖。在第9圖中，與前述第i實施例 相同之構成要素係使用同一參考符號。參考第9圖，其為使 工程性優越，係使用另外的印刷電路基板丨7〇，使下部電路 基板1 2 2之兩側端部分接合至印刷電路基板丨7 〇以形成封裝模 1 5 0。錫球1 6 〇係形成在取代球陸之印刷電路基板丨7 〇的下部 面。 (第3貫施例） 第1 0圖係表示本發明第3實施例之中心腳位晶片的疊層 球格式陣列封裝4 0 0之剖面圖。在第1 〇圖中，在與前述第j實 施例相同的構成要素上係使用同一參考符號。依據第丨〇圖， 係使用導線架1 8 0來取代以絕緣薄膜所成之下部電路基板， 而露出在封裝模1 50外面之導線架1 80的兩侧端部分係，以透 過錫膏（solder paste)190的方式來取代錫球，而直接接合 於外部基板5 0 0。外部基板5 0 0係組裝有封裝丨〇 〇、3 〇 〇、4 〇 〇 來使用之系統基板。使用在第3實施例之導線架丨8〇係，與半
第15頁 1234251
五、發明說明（10) 二=果連】結的部分係施作往上一 ^ 球格ΚΐΠ Γ月；：：中本發明之中心腳位晶片的疊層 現晶片疊層球“陣心腳位型半導體晶片以具體實 ^ I f封裝係在單—封裝内可使記憶容量增大為2件 以上的疊層封裝，可產生微細球格式陣列封穿之；2 : 腳位型半導體晶片的全部優點式陣列^之優點及中心 成，戶2:::導體晶片為以上下對稱構造所形 特別是在L實=匕封= 圍錫球為止的距離為大者^ ’係與由封裝的中央至最外 道麵曰μ 離為大者热關，因在錫球的上側不存在有半 肢日日，所以具有錫球接合之可靠性優越的優點。 ^ 口 〃邊進行模製工程，且同時彎曲下部電路基板，所 性=柏t形成工程可容易實現，且在將上下部電路基板作電 ^日、’透過形成在電路基板的凸塊，以熱壓搾方式使其 枯者，所以可確保充分的可靠性。 g 本°兒明書及圖面上係對本發明之最佳實施例加以揭示， 曰更使用了夕個特定用語，其只不過是使用了容易說明本發 ^ 技術内各且為有助ϋ理解發明之一般意思，並非想對本 :明之範圍作限定。很明顯的，除在此所^示之實施例以 ’對於在本發明之技術領域所屬之具有一般知識者’係可 依據本發明的技術思想而實施其他變ς例。 1234251
圖式簡單說明 第1圖為先行技術之一燊層封裝例之剖面圖。 第2圖為先行技術之晶片的疊層球格式 圖。 夕]封裝的剖面 第3圖為先行技術之中心腳位晶片的球 剖面圖。 ^式陣列封裝的 第4圖為本發明第1實施例之中心腳位晶月 陣列封裝的剖面圖。 且層球格式 第5圖係第4圖所示之中心腳位晶片的疊層妹故 ㈡以法：工程圖，係表:在上下部電路基以π 导，曰曰片之後，以導線連結後之狀態的剖面圖。 目 弟6圖係第4圖所示之中心腳位晶片的疊層电 =造方法之工程圖，係本實施例之製造；i:二車= 下#包路基板帶片的概略平面圖。 穿的ΪΙ®係第4圖所示之中心腳位晶片的疊層球格式陣列封 ^ &二迈方法之工程圖，係表示上下部電路基板彼此枯著& 怨的剖面圖。 和考狀 狀、Ξ 8圖係第4圖所示之中心腳位晶片的疊層球袼式陣列封 ί的ΐ造方法之工程圖，係表示一邊按壓下部電路基板一邊 仃模製工程的狀態之概略刹面圖。 第9圖為本發明第2實施例之中心腳位晶片的疊芦域枚斗 陣列封裝的剖面圖。 ι層球格式 第1 0圖為本發明第3實施例之中心腳位晶片的4層球格 式陣列封裝的剖面圖。 曰
1234251 圖式簡單說明 .【符號 說 明 ] 10 疊 層 封 裝 13 半 導 體 晶片 15 粘 著 劑 20 疊 層 球 格式 陣 列封裝 22 酉己 線 25 粘 著 劑 27 封 裝 模 30 球 格 式 陣列 封 裝 32 半 導 體 晶片 33 金 屬 導 線 35 封 裝 模 100 、300 400 :球格式陣 106 > 1 08 晶片 腳 位 1 11、1 2 1 :介層孔 1 13、123 :窗 115 、1 2 5 、1 2 8 :配、線 1 2 7 :球陸 1 4 0 :凸塊 1 6 0 :錫球 1 8 0 :導線架 2 22 :加壓部 5 0 0 :外部基板 1 1、1 2 :個別封裝 14、1 7、18 ··導線架 1 6 :金屬導線 21 :印刷電路基板 23、24 :半導體晶片 2 6 :金屬導線 2 8 :錫球 31 :電路基板 3 2 a :晶片腳位 34 :封裝模 1 0 2、1 0 4 :半導體晶片 列封裝 110、120 :電路基板帶片 112、122 :電路基板 1 1 4、1 2 4 :基板腳位 1 1 6、1 2 6 :連接腳位 1 3 0 :金屬導線 1 5 0 :封裝模 1 7 0 :基板 21 0、22 0 :鑄模 2 3 0 :鑄孔
第18頁

Claims (1)

1234251 六、申請專利範圍 1、一種中心腳位晶片的疊層球格式陣 ^ 包含有沿各自晶片主動面中央所形成的複 f裝，係疊層 中心腳位型半導體晶片，以實現微細 2片腳位之二個 徵為： 七式陣列封裝，其特 該複數個半導體晶片係，該晶片主 _ 般地各自粘著在上下部電路基板，該複數c目互面對 過金屬導線各自被電性連接在該上下部電：π位係’透 電路基板係彼此相互接合，且透過其：J丄該上下部 :連接’該上部電路基板係包含在封裝模‘，兮2而被電 板之兩側端部分係露出於該封裝模的下部侧。 ρ電路基 陣列2封^中心—晶片的曼層球格式 所構成ί。 亥下部電路基板係以具柔軟性之絕緣薄； 陣列3封/，=專^•㈣2項之中⑽位晶片的叠層球格式 係，形成有複數個錫^了部電路基板之露出的兩側端部分 陣列封骏，其Η中專,:广圍第^::中心腳位晶片的疊層球格式 路基板接合。λ下邰電路基板之兩側端部分係與印刷電 陣列封：，V中專利上圍第4項之中心腳位晶片的疊層球格式 個錫球。'、在该印刷電路基板的下部面係形成有複^ 6、如申請專利笳 陣列封裝，豆中，兮圍弟2項之中心腳位晶片的疊層球格式 ’、通下部電路基板係以導線架所構成者。
第19頁 1234251
申請專利範圍 7 一種中心腳位晶片的疊層诚故4、成 法，係疊層包含有沿各自曰片 列封裝的製造方 日日月主動面中麥戶斤你士、ΑΑ Β " 之二個中心腳位型半導體晶片而製造微细找抵Ϊ I 腳位 其特徵為具有·· 展&从細球格式陣列封裝， 晶心：地，將該複數個半導想 :數個晶片腳位各自電性連接至該部J 導線將該 步驟；該上部電路基板：包也；;^ :路ίΪ彼此接合的 裝模之步驟。 、忒封裝核的下部侧般地形成該封 8、一種中心腳位晶片的疊層球 法，係疊層包含有沿各自晶片主動j Λ陣列封裝之製造方 片聊位之二個中心聊位型半導體形成的複數個晶 封裝，其特徵為包含有： 曰片而製造微細球格式陣列 提供一上下部電路基板帶 帶片係’各個介層孔和窗以下部電路基板 線、以及連接腳位係以一定二成，基板腳位、配 成球陸：且在該連接腳位形：板之"層孔内 於該電：ϊί帶位透過該窗被露出般地， 依金屬導半導體晶片； 複數個基板腳位的步驟； S日片腳位予以電性連接至該
1234251 六、申請專利範圍 ---- 電性連接步驟，係該半導體晶片彼此相互面對般地使該 上下部電路基板彼此粘著，且依該凸塊將該上下部電路基板 形成步驟，係透過該介層孔按壓該下部電路基板之該球 陸，而延伸至該下部電路基板的介層孔内之配線&下方g曲 般地使該球陸露出以形成封裝模； 在該球陸形成複數個錫球 、 由該電路基板帶片將各自 9、如申請專利範圍第8項 陣列封裝之製造方法，其中， 各自的電路基板位在模製裝置 路基板帶片提供於以上下部鑄 驟；該下部電路基板的球陸抵 該上部鑄模之加壓部透過該電 球陸之步驟；以及透過該模製 脂注入該鑄孔内，使其硬化以 之步驟； 的個別封 之中心腳 形成該封 的鑄孔内 模所構成 接該下部 路基板帶 裝置之注 形成該封 以及 裝予以 位晶片 裝模之 般地， 之模製 每模般 片的介 入〇 ， 裝模的 分離的 的疊層 步驟為 將該上 装置内 地，使 層孔來 將液狀 步驟所 步驟。 球格式 :使該 下部電 的步 形成在 按壓該 模製樹
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