TW520553B - Method of manufacturing a contact of a semiconductor device using cluster apparatus having at least one plasma pretreatment module - Google Patents
Method of manufacturing a contact of a semiconductor device using cluster apparatus having at least one plasma pretreatment module Download PDFInfo
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- TW520553B TW520553B TW090127753A TW90127753A TW520553B TW 520553 B TW520553 B TW 520553B TW 090127753 A TW090127753 A TW 090127753A TW 90127753 A TW90127753 A TW 90127753A TW 520553 B TW520553 B TW 520553B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 98
- 239000010410 layer Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 230000008021 deposition Effects 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000004380 ashing Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 70
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 35
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 33
- 239000011737 fluorine Substances 0.000 claims description 33
- 229910052731 fluorine Inorganic materials 0.000 claims description 33
- 238000006243 chemical reaction Methods 0.000 claims description 28
- 238000004140 cleaning Methods 0.000 claims description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- 238000007781 pre-processing Methods 0.000 claims description 21
- 229910052757 nitrogen Inorganic materials 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- 239000012495 reaction gas Substances 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 239000001257 hydrogen Substances 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 9
- 238000002203 pretreatment Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- VPAYJEUHKVESSD-UHFFFAOYSA-N trifluoroiodomethane Chemical compound FC(F)(F)I VPAYJEUHKVESSD-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 4
- 238000003756 stirring Methods 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000010248 power generation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 description 10
- 238000001816 cooling Methods 0.000 description 7
- 239000000112 cooling gas Substances 0.000 description 6
- 239000000498 cooling water Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 239000000356 contaminant Substances 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004043 dyeing Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010102 embolization Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- -1 fluoride ions Chemical class 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
520553 A7
裝 訂
發明説明(2 ) 何在界定接觸孔底部的表面受損後之栓塞植入法。此外, 亦已知一種除去在接觸孔底部的受損層之方法。 圖1顯示一種自形成接觸孔時至形成上導電或半導體斧 時的習用製造方法。參照圖1,接觸孔係藉電漿乾燥蚀刻 裝置(S10)形成。通常,接觸孔係藉形成絕緣層在半導體基 材或其他特定底層(或”底部層")上,使用光刻技術形成光 阻圖案在絕緣層上及使用光阻圖案作爲蝕刻罩蝕刻絕緣層 形成。 其次’半導體基材移動至灰磨裝置,光阻圖案在其上灰 磨及除去(S12)。然後,實施光阻(PR)帶法(S14)。在此法中 ,半導體基材係自灰磨裝置轉移至填滿硫酸的濕桶以除去 未由灰磨法除去的光阻圖案的殘餘物。 其次,實施殘餘物加工法以藉電漿乾燥蝕刻法除去形成 在半導體基材的表面或在界定接觸孔(S16)底部特定底層表 面的受損層。使用低偏壓條件與CF4或氧氣實施殘餘2加 工法。其次,在濕桶(S18)内實施預處理清潔法以除去另一 由殘餘物加工法形成的受損層並自接觸孔除去任何殘餘污 染物如碳。 隨後,預加工半導體基材轉移至沉積裝置,上層形成於 其上以填充接觸孔(S20)。 、 然而’先行製造方法卻具有下面問題。 首先,光阻(PR)帶法需要較長加工時間而增加半導體基 材:染的可能性,因爲PR帶法在填滿硫酸的濕桶内實施。土 罘二’由接觸孔暴露的表面會被乾燥蝕刻裝置進行的殘 3 五、發明説明( 餘物加工法損害。然而,即使受損層可藉實施預處理清潔 法於濕桶内除去,界定接觸孔侧璧的各層蝕刻速率亦會隨 用於預處理清潔法的清潔溶液改變。因此,界定接觸孔的 侧璧變成不平坦而形成在半導體基材上的圖案由於過度蚀 刻而劣化。 第一,即使在實施預處理清潔法後,當半導體基材轉移 、貞裝置時,新天然氧化物膜亦會形成在界定接觸孔底 部的表面上。天然氧化物膜會妨礙界定接觸孔底部的下層 表面與沉積法形成的上層間達成之良好接觸。 罘很難整合各種方法,目爲乾㈣刻與沉積法通常 在日田圓上實施一次,而具有使用濕桶特性的光阻p &夢 、、:、預處理潔法爲分批法。因&,半導體基材必須透過 刀離加工裝置轉移,而使基材更容易污染。因此,雖钬花 費許多加工時間,許多裝置仍會具有較劣電性。 本發明的目的爲解決上述先行技藝的問題。 觸 短 明確而言,本發明的目的爲提供一種形成半導體裝置 二Γί,其中形成良好接觸所需的預處理法可在相當 時間内實施。 、、貧㈣另-目的爲提供一種形成半導體裝置觸點 、、/、中形成良好接觸所需的-預處理法可實施而半導 材不會在方法間之暫時被污染。 、馬了達成此等目W,本發明提供一種方法,其中自 本纸張尺度適用中而 接觸孔時至_充接觸孔時的預處理法係使用電漿實施^ 一 ----' 520553 A7
接觸孔係使用光阻圖案作爲蝕刻罩形成,其中暴露包本 矽的底材表面。隨後,半導體基材裝入具有一個或以上^ 過可保持眞空的構件互相連接之電漿預處理與沉積模組的 集束裝置内。在第-預處理過程中,絲圖案係藉灰磨除 去。在第二預處理過程中,除去在由接觸孔暴露的表面的 受損層。在第三預處理過程中,清潔半導體基材。然後, 半導體基材轉移至沉積模組而基材保持於眞空内。薄膜形 成在基材上以%充接觸孔,因而與底層成立電接觸。 底層可爲矽、聚矽或矽化物層。填充接觸孔形成的上層 爲導電膜如由聚矽層與金屬層形成。 電漿預處理模組設計成使用微波產生遙控電漿。在此方 面,灰磨光阻圖案的過程係使用呈電漿狀態之氮氣與氧氣 ,接著施加UV光線實施。除去受損層的過程係使用呈電 漿狀態之氮氣與氧氣及呈電漿狀態或正常氣體狀態之氟基 底氣體實施。此外,清潔過程包括使用呈電t狀態之氣氣 與氟基底氣體以造成與氧化物層在暴露在接觸孔底部的底 層表面上的化學反應,藉以形成反應層,及退火反應層汽 化之。 根據本發明,灰磨法、殘餘物加工法及預處理清潔法可 在集束裝置的電漿預處理模組内連續地實施。因此,預處 理加工時間可降至最低。此外,污染物被防止堆積於接觸 孔内,相對照於其中半導體基材在各種先行加工裝置中轉 移的情況。 此外,由接觸孔暴露的沉積材料與表面互相良好接觸,
520553
因馬眞空保持在電漿預處理模組與沉積模組之間以防止在 實施預處理清潔法後天然氧化物膜生長在暴露表面上。 p付圖的簡述 本發明的上述及其他目的、特性與優點參照附圖以及其 較佳具體例的下列詳述當可更佳明白,其中: 圖1爲半導體裝置製程中形成觸點的習知方法的方塊圖; 圖2爲形成根據本發明半導體裝置觸點的方法的方塊圖; 圖3爲在根據本發明半導體裝置製程中形成觸點的裝置 的概略平面圖; 圖4爲圖3所示裝置的電漿預處理模組第一具體例的概略 圖表; 圖5爲電漿預處理模組另一具體例的概略圖表;及 圖6至10爲顯示形成根據本發明觸點方法的基材的截面 圖。 較佳具體例的詳細發昍 本發明現在參照附圖進一步詳述。但是應知當一層被説 明爲在另一層或基材"上”時,該説明意旨所述層可直接配 置在其他層或基材上,或***層可插於其間。 圖2顯示構成形成根據本發明觸點方法的基本過程。簡 s之’在使用乾燥蚀刻裝置形成接觸孔後(步驟S40),灰 磨過程(步驟S42)、殘餘物加工過程(步驟S44)及預處理過 程(步驟S46)皆在預處理模組内實施。隨後,上層形成於 沉積模組内(步驟S48)。 然而’在詳述形成根據本發明觸點的方法以前,將説明 - ~ 8 - 本紙浪尺度適用中國國家標準(CNS) A4規格(21GX297公釐) " -----
裝 訂
520553 A7 B7 五、發明説明(6 ) 執行方法的裝置。現在參照圖3,裝置包括一組各個加工 模組。保持均勻眞空的轉移模組100配置於裝置的中間。 裝卸模組110、120、冷卻模組130、預處理模組140、150及 160以及沉積模組170、180環繞轉移模組100排列。 轉移裝置(圖未示)設於轉移模組100之中心。晶圓係藉 轉移裝置自裝載模組110轉移至特定預處理模組140、150或 160。在實施預處理過程後,晶圓係透過保持眞空的轉移 模組100自預處理模組轉移至沉積模組170或180。填充接觸 孔的上層形成在沉積模組内晶圓上。在最後預處理過程後 ,若晶圓的溫度太高時,晶圓可在形成上層前轉移至冷卻 模組130。冷卻模組130在沉積過程後但是在晶圓轉移至卸 下模組120前亦可用以冷卻晶圓至適當溫度。雖然三種預 處理模組與二種沉積模組示於圖3,必要時,裝置亦可具 有其他數目的預處理及沉積模組。 圖4顯示一種包含遙控電漿產生裝置的預處理模組的具 體例。該遙控電漿產生裝置揭示於韓國專利申請案99-46365號。 參照圖4,預處理模組包含一眞空室10、一構成遙控電 漿產生裝置供激起反應氣體進入電漿内並轉移呈電漿狀態 的反應氣體至眞空室10之微波導件44、一氣體擴散器、一 實施退火過程於相同室内之加_熱器54及一定位晶圓於眞空 室10内之感受器12。 明確而言,其上安裝有晶圓14的感受器12配置在眞空室 10的中心。感受器12可藉由軸20及馬達22自眞空室10的下 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 520553 A7 B7 五、發明説明(7 ) 部移至眞空室10的上部,反之亦然(如箭頭:D所示)。晶圓 14的溫度係由感受器12的溫度所控制。冷卻線16a透過供應 冷卻水或冷卻氣體的感受器12延伸以控制感受器12進而晶 圓14的溫度以便確保過程的再製性。自冷卻水或冷卻氣體 供應裝置18供應冷卻水或冷卻氣體的第一管道16連接至冷 卻線16a。 反應氣體透過氣體擴散器供應至眞空室10。氣體擴散器 包含一自延伸眞空室10外側的第二與第三管道32、34接收 反應器體的預備室50,以及連接至預備室50底部供均勻分 佈氣體遍佈眞空室10的多孔板52。第二管道32用來供應呈 電漿狀態的氣體。氫氣體供應源(標示爲"H2”)與氟基底氣 體供應源(標示爲nNF3n )連接至第二管道32的一端。轉換閥 36、38及控制氣體量的質量流動控制器(MFC) 40、42分別靠 近氫氣體供應源與氟基底氣體供應源安裝。自氟基底氣體 供應源與氫氣體供應源的氣體分別通過轉換閥36、38及質 量流動控制器40、42到達其上激起氣體的微波導件44。第 三管道34用來供應天然氟基底氣體。氟基底氣體供應源( 標示爲” NF3n )連接至第三管道34之一端。轉換閥46及MFC 48安裝於靠近氟基底氣體供應源的第三管道34内。 然而,用於本發明方法的源氣體不限於氫(H2)與氟基底 (NF3)氣體。例如,氧氣(02)、_氮氣(N2)及氬氣(Ar)亦可用 作源氣體。 排氣口 24設在眞空室10的底部供排除眞空室10的氣體以 便保持眞空室10内正常眞空準位。第四管道26連接至排氣 -10- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂
520553 A7 B7 五、發明説明(8 ) 口 24,而轉換閥28及眞空泵30安裝於第四管道26内。 眞空室内側的壓力由安裝於眞空室10的底部的靈敏閥( 圖未示)自動控制。供晶圓14退火的加熱器54插在預備室50 頂部與眞空室10的頂部之間。加熱器54可爲紫外線(UV)燈 或雷射。 圖5概略顯示預處理模組的另一具體例。此具體例的預 處理模組包含一眞空室60、一構成激起反應氣體進入電漿 内及轉移呈電漿狀態的反應器體至眞空室60之遙控電漿產 生裝置的微波導件90、一氣體擴散器。在室60内實施退火 過程的UV燈78及一支持晶圓64的感受器62。 眞空室60的内璧塗佈有陽極化膜以防止内璧被氟離子腐 蝕。眞空室60的側璧設有加熱器96。眞空室的上璧76成圓 頂狀。明確而言,上璧包含一整合UV燈78的光線固定單元 76及一延伸在UV燈78下方由藍寶石製成的透明窗74。 其上安裝有晶圓64的感受器62配置於眞空室60下部的中 心。移動晶圓64上、下的起模針72延伸過感受器62。起模 針72安裝至上、下驅動的針固持器70。晶圓64的溫度係由 感受器62的溫度所控制。冷卻線延伸過供應冷卻水或冷卻 氣體的感受器62以控制感受器62進而晶圓64的溫度以便確 保過程的再製性。自冷卻水或冷卻氣體供應裝置68供應冷 卻水或冷卻氣體的第一管道66連接至冷卻線。 反應氣體透過氣體擴散器供應至眞空室60内。氣體擴散 器包含一自延伸眞空室60外側的第二管道98接收反應氣體 的預備室80以及一連接至預備室80底部供均勻分佈氣體遍 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)
裝 訂 520553 A7 B7 五、發明説明(10 ) 參照圖8,對蝕刻停止層212具有蝕刻選擇率的氧化矽夾 層介電膜214形成至預定厚度。其次,接觸孔係使用乾燥 蝕刻裝置形成於夾層介電膜214内(步驟S40)。明確而言, 接觸孔係藉SAC過程所形成。 在此方面,光組圖案216形成於預處理模組内。光組圖 案用以形成對應於閘極電極圖案間空間寬度的接觸孔。閘 極電極圖案間之空間越小,使用典型光刻過程形成光阻圖 案變成越困難,因爲過程的解析度方面的固有限制。因此 ,設計光阻圖案以形成大於閘極電極圖案間空間寬度的接 觸孔。夾層介電膜214係使用光阻圖案作爲蚀刻罩各向異 性地蚀刻,因而接觸孔係藉各閘極電極圖案的罩層208與 隔件210而自行對準。當蝕刻夾層介電膜214時,蝕刻停止 層212暴露在閘極電極圖案之間。 參照圖9,閘極電極圖案間之矽基材200係在不同於蝕刻 夬層介電膜214的蚀刻條件下藉蝕刻蚀刻停止層212暴露。 因此,形成接觸孔。此時,受損層218係在閘極電極圖案 間暴露矽基材200的表面產生。此外,各種污染物留在閘 極電極圖案間暴露矽基材200的表面上。 在形成接觸孔的矽基材200轉移至圖4或5所示的預處理 模組後,按序實施灰磨過程S42、殘餘物加工過程S44及預 處理清潔過程S46。現在説明在此等過程中預處理模組通 行的條件。 首先,實施除去光阻圖案216的灰磨過程。在此過程中 ,UV燈發出具有波長爲200-500 nm的UV光線並在電力爲 -13 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 520553 A7 B7 五、發明説明(Μ ) 300-1,000 W下操作。微波導件的電力爲500-2,000 W。預處 理模組内的壓力爲0.1-10 Torr。矽基材200的溫度爲25-300 °C。灰磨過程係在此等條件下藉速率分別爲10-2,000 seem 及K)-2,000 seem下供應至呈電漿狀態的模組内的氮氣與氧 氣實施。須知,光阻圖案係藉UV光線較習知灰磨過程所用 的手段更有效地除去。因此,不需要附加帶狀過程。 其次,除去受損層218的殘餘物加工過程係藉供應氮氣 及氧氣於呈電漿狀態的模組内並藉供應氟基底氣體於模組 内實施。在此過程中,微波導件的電力爲500-2,000 W。預 處理模組内的壓力爲0.1-10 Torr。矽基材200的溫度爲5 - 300 °C。氮氣作爲反應氣體係在速率爲10-2,000 seem,氧氣在 速率爲10 _ 2,000 seem及氟基底氣體(NF3)在速率爲30-300 seem下供應。 使用電漿除去受損層在底層中較當使用習知殘餘物加工 過程時產生較低損害。此外,矽基材200的暴露表面不會 被碳污染,因爲使用NF3,相對照於CF基底氣體。 最後,以二個步驟,即,化學反應步驟與退火步驟,實 施預處理清潔過程。化學反應步驟涉及供應氫與氟基底氣 體於模組内,化學反應二種氣體與形成在界定接觸孔底部 的矽基材200表面上的氧化物膜以形成反應層。退火步驟 除去如此形成的反應層。 — 其次,説明形成反應層的步驟中特定條件。微波導件的 電力爲500-2,000 W。電漿預處理模組内的壓力爲1 - 10 Ton* 。秒基材的溫度爲0-50°C。氮氣作爲反應氣體係在速率爲 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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520553 A7 B7 五、發明説明(12 ) 10-2,000 seem,氫氣在速率為5-200 seem及NF3在速率為10-300 seem下供應。因此,天然氧化物膜變形成例如(NH4)2SiFd$ 反應層。該反應層可被汽化而除去。 氟基底氣體可呈電漿狀態或正常氣體狀態供應。NF3、 SF6或CIF3可用作用過的氟基底氣體。在較佳具體例中,使 用NF3。氫供應於呈電漿狀態的模組·内。當呈電漿狀態供應 氫與氟基底氣體時,NF3氣體對氫電衆的比率設定為例如 0.1 - 100,而混合物與氧化物膜(其為Si02)化學反應。形成 反應的副產物,即,(NH4 )2SiF6,其中混合物與氧化物膜配 合。一旦反應層達到某種厚度時,反應層作為障壁層操作 有關化學反應。因此,化學反應停止。在供應氣體與氧化 物膜間的化學反應停止後,實施退火過程,藉以反應層被 汽化並排放至模組外側。最後,退火過程較佳在100- 5 00 °C 下實施20-600秒。在除去污染物如天然氧化物及表面氧化 物後,與氫原子組合的純化層形成在暴露表面上。因此, 可防止半導體基材的表面被再氧化。 若欲除去的氧化物膜與天然氧化物膜一樣薄時,氧化物 膜可在預處理清潔過程的一循環中除去。然而,若保證欲 除去氧化物膜的厚度時,可重複實施預處理清潔過程的二 個步驟。 此外,在預處理清潔過程中,化學反應步驟與退火步驟 按序於預處理模組内實施。當使用圖4的預處理模組時, 當半導體基材定位於真空室10的下部時可實施化學反應步 驟,而當半導體基材定位於配置UV燈54的真空室10的上部 時則可實施退火步驟。 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 520553 A7 B7 五、發明説明(13 ) :--—~—— 參照圖10,已進行預處理清潔過程的矽基材2〇〇係自預 處理模組140、150或16〇(圖3 )透過轉移膜1〇〇而在眞空内轉 移至圖3的沉積模組17〇或18〇。然後形成後續(上)層22〇。 各種導電金屬模皆可用作上層220。 熟習此技藝者當可明白,本發明比較先行技藝時可減少 加工時間及製造成本,因爲⑴灰磨過程、殘餘物加工過程 及預處理清潔過程係使用電漿按序實施於預處理模組内, 及(2)不而要pr帶狀過程,因爲光阻劑反而藉使用氧電漿與 UV光線進行的灰磨過程有效地除去。 第二,本發明可用以製造具有改良電特性的半導體裝置 ,因爲氟基底氣體與氧氣取代含碳的氣體用以除去在接觸 孔底部的受損層。即,本發明的殘餘物加工過程對暴露在 接觸孔底邵的層任何進一步損害降至最小且其上不會留下 任何碳污染。 第三,使用本發明不會退化接觸孔的輪廓或留下水污點 ,因爲使用電漿乾燥蝕刻取代習用濕蝕刻實施預處理過程。 第四,本發明使基材的污染降至最低並防止在二個過程 之間天然氧化物膜被再生長,因爲預處理模組與沉積膜組 會集束並透過可保持於眞空内的手段連接。 雖然本發明已特別顯示並參照閘極電極圖案間sac的形 成説明,熟習此技藝者當可明_白,本發明不受限制並可應 用於製造半導體裝置各種其他方法,如形成金屬及位元線 觸點的万法。此外,本發明可應用於形成配置在含有矽底 層上的夾層内接觸孔,例如,關於暴露聚矽層或矽化物層 1^ __ -16· 本紙張尺度適用中g @家標準(CNS) A4規格(210X297公釐) 一一 -- 520553 A7 B7 五、發明説明(14 ) 的接觸孔的形成。因此,所有該在所附申請專利範圍的範 圍内之應用被視爲在本發明的眞正精神内。 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
Claims (1)
- 520553 A8 B8 C8 D8 ~、申請專利範圍 1. 一種製造半導體裝置之一觸點之方法,包括步驟爲: 提供一種半導體基材,其上有一夾層形成在一含矽的 底層上; 使用一光阻圖案作爲一姓刻罩形成一接觸孔於該夾層 内’其中該底層的一表面暴露在該接觸孔的底部; 將該半導體基材裝入具有互相連接的一電漿預處理模 組與一沉積模組的裝置内; 將該半導體基材轉移至該電漿預處理模組; 灰磨該電漿預處理模組内的光阻圖案以除去該光阻圖 案; 隨後除去在該電漿預處理模組内定義該接觸孔底部的 底層表面的一受損層; 隨後清潔該電漿預處理模組内的半導體基材; 隨後轉移在眞空中之半導體基材至該沉積模組;及 沉積材料在該沉積模組内填充接觸孔的基材上。 2 ·如申請專利範圍第1項的方法,其中該灰磨、受損層之 去除及預清潔各包括使用微波激起氣體在預處理模組 外側’以謗發一電漿狀態,及指引呈電漿狀態之氣體 朝向該預處理模組内的基材。 3.如申請專利範圍第2項的方法,其中該灰磨包括在該預 處理模組内加熱該基材。 一 4 ·如申请專利範圍第3項的方法,其中該加熱包括在該預 處理模組内產生紫外(UV)光線。 --------- - 18 - 尽紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閎讀背面之注意事項再填寫本頁) 4 訂 經濟部中央榡準局員工消費合作衽印製 520553 A8 B8 C8 D8 六、申請專利範圍 5 .如申請專利範圍第4項的方法,其中該灰磨包括使用微 波激起在預處理模組外側之氮氣與氧氣,以謗發該電 漿狀態,及供應呈電漿狀態的氮氣與氧氣朝向該預處 理模組内的基材。 6 .如申請專利範圍第5項的方法,其中該灰磨包括以10-2,000 seem的速率供應氮氣,且以10-2,000 seem的速率供 應氧氣作爲反應氣體,用500-2,000 W的微波電力激起氣 體,在該電漿預處理模組内保持屢力0.1-10 Torr,調節 該基材的溫度於25-300°C及在電力爲300-1,000 W下操作 UV燈以供應UV光線。 7 .如申請專利範圍第1項的方法,其中該受損層之去除包 括激起在預處理模組外側之氮氣與氧氣,使用微波以 謗發電漿狀態,及供應呈電漿狀態的氮氣與氧氣及一 氟基底氣體朝向該預處理模組内的基材。 8 .如申請專利範圍第7項的方法,其中該氟基底氣體爲 NF3。 9 .如申請專利範圍第8項的方法,其中該受損層之去除包 括在以10-2,000 seem之速率供應氛氣,以10- 2,000 seem之 速率供應氧氣及30-300 seem之速率供應NF3氣作爲反應 氣體,用500-2,000 W之微波電力激起氮氣與氧氣,在 電漿預處理模組内保持壓力0.1-10 Torr及調節半導體基 材的溫度至5 - 300°C。 10.如申請專利範圍第1項的方法,其中該清潔包括: -19 - 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂 線_卜 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 •供應呈一電漿狀態的氫氣及一氟基底氣體至該基材上 以造成一化學反應發生在含石夕底層上的氧化物層,藉 以形成一反應層,以及退火反應層以汽化之。 11. 如申請專利範圍第10項的方法,其中該氟基底氣體呈 氣體狀態供應。 12. 如申請專利範圍第10項的方法,其中該氟基底氣體的 供應包括使用微波激起在預處理模組外側之氟基底氣 體,以謗發一電漿狀態,及指引呈電漿狀態的氟基底 氣體至基材上。 13. 如申請專利範圍第10項的方法,其中該氟基底氣體係 選自NF3、SF6& CIF3所組成之群。 14. 如申請專利範圍第10項的方法,其中該清潔包括以10-2,000 seem之速率供應氣氣,以5-200 seem之速率供應氧 氣及以10-300 seem之速率供應氟基底氣體作爲反應氣體 ,用500-2,000 W之微波電力激起氣體,在電漿預處理 模組内保持壓力爲0.1-10 Ton*及調節半導體基材的溫度 至 0-50°C。 15. 如申請專利範圍第10項的方法,其中該清潔包括定位 半導體基材於預處理模組的一下部而供應氣體以造成 該化學反應,及定位半導體基材於預處理模組的一上 部而實施退火。 16. 如申請專利範圍第10項的方法,其中該退火包括加熱 半導體裝置至100-50(TC範圍内。 -20- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 六、申請專利範圍 17. —種製造半導體裝置觸點的方法,包括步驟爲: 提供一種半導體基材,其上有一夾層形成在一含矽的 底層上; 使用一光阻圖案作爲一蝕刻罩形成一接觸孔於夾層内 ,其中底層的一表面暴露在接觸孔的底部; 使用電漿及UV光線灰磨光阻圖案以除去一電漿預處 理加工室内的光阻圖案; 隨後使用一電漿及一氟基底氣體除去在一電漿預處理 加工室内定義接觸孔底部的底層表面的一受損層,藉 以形成氧化物在該表面; 隨後清潔半導體基材以除去一電漿預處理加工室内該 氧化物,該清潔包括指引與氧化物在表面上進行化學 反應的一電漿以形成一反應層,及退火基材以汽化反 應層; 隨後轉移在一眞空中半導體基材至一沉積裝置;及 沉積材料在沉積裝置中填充接觸孔的基材上。 18. 如申請專利範圍第17項的方法,其中該灰磨、受損層 之去除及清潔各包括使用微波激起氣體。 19. 如申請專利範圍第17項的方法,其中該灰磨包括使用 微波激起氮氣及氧氣以謗發一電漿狀態。 20. 如申請專利範圍第19項的方灰,其中該灰磨包括以10-2,000 seem之速率供應氣氣而以10-2,000 seem之速率供應 氧氣作爲反應氣體,用500-2,000 W微波電力激起氣體, -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 六、申請專利範圍 在實施灰磨過程的電漿預處理加工室内保持壓力爲 0.1-10 Torr,調節基材的溫度至25-300°C及在電力爲300-1,000W下操作UV燈以供應UV光線。 21. 如申請專利範圍第17項的方法,其中該氟基底氣體爲 NF3 0 22. 如申請專利範圍第21項的方法,其中該受損層之去除 包括以10-2,000 seem之速率供應氮氣,以10- 2,000 seem 之速率供應氧氣及以30-300 seem之速率供應NF3氣作爲反 應氣體,用500-2,000 W之微波電力激起氮氣與氧氣, 在實施該受損層之去除的預處理加工室内保持壓力爲 0.1-10 Ton*及調節半導體基材的溫度至5-300°C。 23. 如申請專利範圍第17項的方法,其中該清潔包括: 供應呈一電漿狀態的氫氣及氮氣與一氟基底氣體至基材 上。 24. 如申請專利範圍第23項的方法,其中該氟基底氣體呈 一氣體狀態供應。 25. 如申請專利範圍第24項的方法,其中該氟基底氣體的供 應包括使用微波激起氟基底氣體以謗發一電漿狀態。 26. 如申請專利範圍第25項的方法,其中該氟基底氣體係 選自NF3、SF6& CIF3所組成之群。 27. 如申請專利範圍第23項的方_法,其中該清潔包括以10-2,000 seem之速率供應氮氣,以5-200 seem之速率供應氫 氣及以10-300 seem之速率供應氟基底氣體作爲反應氣體 -22- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 520553 A B c D 六、申請專利範圍 •,用500-2,000 W之微波電力激起氣體,在實施清潔的 預處理加工室内保持壓力爲0.1-10 Torr及調節半導體基 材的溫度至0-50°C。 28. 如申請專利範圍第17項的方法,其中該清潔包括定位 半導體基材於預處理加工室的一下部而造成該化學反 應發生,及定位半導體基材於預處理加工室的一上部 而實施退火。 29. 如申請專利範圍第17項的方法,其中該退火包括加熱 半導體基材至100-500 °C範圍内。 -23 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
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GB9715013D0 (en) * | 1997-07-17 | 1997-09-24 | Cambridge Consultants | Liquid feed bottle |
US6107192A (en) | 1997-12-30 | 2000-08-22 | Applied Materials, Inc. | Reactive preclean prior to metallization for sub-quarter micron application |
US6110836A (en) | 1999-04-22 | 2000-08-29 | Applied Materials, Inc. | Reactive plasma etch cleaning of high aspect ratio openings |
US6346489B1 (en) * | 1999-09-02 | 2002-02-12 | Applied Materials, Inc. | Precleaning process for metal plug that minimizes damage to low-κ dielectric |
US6228563B1 (en) * | 1999-09-17 | 2001-05-08 | Gasonics International Corporation | Method and apparatus for removing post-etch residues and other adherent matrices |
US6492272B1 (en) * | 2001-02-15 | 2002-12-10 | Advanced Micro Devices, Inc. | Carrier gas modification for use in plasma ashing of photoresist |
-
2000
- 2000-11-24 KR KR10-2000-0070491A patent/KR100382725B1/ko active IP Right Grant
-
2001
- 2001-10-25 US US09/983,790 patent/US6767834B2/en not_active Expired - Lifetime
- 2001-11-08 TW TW090127753A patent/TW520553B/zh not_active IP Right Cessation
- 2001-11-15 JP JP2001349915A patent/JP2002222861A/ja active Pending
- 2001-11-22 DE DE10157223A patent/DE10157223B4/de not_active Expired - Lifetime
- 2001-11-23 CN CNB011396091A patent/CN1187796C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6767834B2 (en) | 2004-07-27 |
KR20020040445A (ko) | 2002-05-30 |
DE10157223B4 (de) | 2006-11-16 |
JP2002222861A (ja) | 2002-08-09 |
CN1187796C (zh) | 2005-02-02 |
DE10157223A1 (de) | 2002-06-27 |
KR100382725B1 (ko) | 2003-05-09 |
CN1356719A (zh) | 2002-07-03 |
US20020064944A1 (en) | 2002-05-30 |
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