TW495958B - Semiconductor device and method for fabricating the device - Google Patents
Semiconductor device and method for fabricating the device Download PDFInfo
- Publication number
- TW495958B TW495958B TW090116507A TW90116507A TW495958B TW 495958 B TW495958 B TW 495958B TW 090116507 A TW090116507 A TW 090116507A TW 90116507 A TW90116507 A TW 90116507A TW 495958 B TW495958 B TW 495958B
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- Taiwan
- Prior art keywords
- conductive
- semiconductor device
- region
- substrate
- insulating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 75
- 239000012212 insulator Substances 0.000 claims abstract description 44
- 239000007787 solid Substances 0.000 claims abstract description 11
- 238000001020 plasma etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 58
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 239000000853 adhesive Substances 0.000 claims description 19
- 230000001070 adhesive effect Effects 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 5
- 230000002079 cooperative effect Effects 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 10
- 239000010949 copper Substances 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 238000005498 polishing Methods 0.000 abstract description 7
- 238000007689 inspection Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 238000010407 vacuum cleaning Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
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- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
495958 ^ A7 _B7___ 五、發明説明(1 ) 發明背景 本發明與具有多數基材之半導體裝置及製造該裝置之方 法相關。 近來,本發明者已經提出這種藉由下面步驟所獲得之半 導體裝置:層壓導電層和絕緣層在第一半導體基材上,藉 由化學機械研磨法(此後縮寫爲CMP)用以一平坦第一黏合表 面的形成在矽氮化物薄膜當作絕緣層和銅,其爲一貫穿孔 導體用以***矽氮化物薄膜之貫穿孔,所暴露地方之上而 4 研磨其表面,層壓一導電層和一絕緣層在一第二半導體基 材上,使其表面遭受CMP用以一平坦第二黏合表面形成在 矽氮化物薄膜和爲貫穿孔導體之銅所暴露地方之上,進一 步應用壓力鎔接裝載至第一半導體基材和第二半導體基材 用以達成第一黏合表面固態黏合至第二黏合表面且電氣地 將貫穿孔導體彼此連接。要注意該半導體裝置係爲了解釋 本發明之緣故才提及,此表示該裝置尚未公開且不是先前 技藝。 該半導體裝置具有優點其可以簡單地防止電磁輻射噪音 ,因爲提供導電層在第一和第二基材上且内連線可以造的 短且容易因爲貫穿孔導體是以固態黏合方式黏合在一起。 然而,前述的半導體裝置,其中由銅所製造之貫穿孔導 體和提供在矽氮化物薄膜之貫穿孔内具有比爲絕緣層之矽 氮化物薄膜的還要低之硬度。所以,當第一黏合表面和第 二黏合表面遭受CMP時,碟狀(一碟狀之洞)發生在貫穿孔導 體的表面上且直接地將貫穿孔彼此黏合此可能引向失敗。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 . A7 B7 五、發明説明(2 ) 即是貫穿孔導體之電氣連接沒有可靠性。 發明摘要 因此,本發明的目的係提供一半導體裝置及製造該裝置 之方法,其能夠藉由即使其黏合表面遭受CMP方法和固態 黏合,也能安全地直接將導體彼此黏合而達成可靠電氣連 爲了達成上述目的,本發明提供一半導體裝置,其包括: 一第一邵份,其具有一第一基材、一導電層和一絕緣層 層壓在第一基材和一黏合表面,其被化學機械研磨且暴露 一導電區域和一絕緣區域; 一第二邵分,具有一第二基材、一導電層和一絕緣層層 壓在第二基材和一黏合表面,其被化學機械研磨且暴露至 少一導電區域;且其中: 第一部份的黏合表面和第二部份的黏合表面固態黏合彼 此且 第一部份的黏合表面和第二部份的黏合表面之至少其中 之一具有比相對於導電區域還低之絕緣區域。 在前述建構之半導體裝置中,第一和第二部份的黏合表 面被化學機械研磨,所以,碟狀部分發生在相鄰於絕緣區 域之導電區域。然而,絕緣區域相對於在第一部份之黏合 表面和第二部分之黏合表面之至少其中之一上的導電區域 ,被降低所以導電區域突出。因此,即使碟狀部分存在, 導電區域還是安全地直接彼此黏合。所以,可以獲得導電 區域之高可靠性電氣連接。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 - A7 B7 五、發明説明(3 ) 在一具體實施例中,導電區域的碟狀部分彼此黏合。 在一具體實施例中,第一部份之導電區域和第二部份的 導電區域彼此固態黏合,且第一部份的絕緣區域和第二部 份的絕緣區域有一空隙介入而彼此面對。 在一具體實施例中,圍繞弟·一部份的導電區域之絕緣區 域和圍繞弟二部份的導電區域之絕緣區域有一 2隙介入而 彼此面對。 在一具體實施例中,第一部份的導電區域和第二部份的 導電區域彼此固態黏合且第一部份的絕緣區域和第二部份 的絕緣區域彼此接觸或是彼此固態黏合。 在一具體實施例中,圍繞第一部份的導電區域之絕緣區 域和圍繞第二部份的導電區域之絕緣區域彼此接觸或是彼 此固態黏合。 在一具體實施例中,導電區域係爲貫穿孔導體之末端表 面而絕緣區域係爲圍繞相對貫穿孔導體之貫穿絕緣體之末 端表面。 在一具體實施例中,第一基材或是第二基材係爲半導體 基材、無機基材或是有機基材其中任何一種。 根據本發明,提供一種半導體裝置製造方法,其包括下 面步驟:. 形成一第一部份,其具有一第一基材、一導電層和一絕 緣層層壓在第一基材和一黏合表面,其被化學機械研磨且 暴露一導電區域和一絕緣區域; 形成一第二部分,具有一第二基材、一導電層和一絕緣 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 495958 ^ A7 B7 五、發明説明(4 ) 層層壓在第二基材和一黏合表面,其被化學機械研磨且暴 露至少一導電區域; 選擇性地蚀刻第一邵份的黏合表面和第二部份的黏合表 面之至少其中之一的絕緣區域,藉此相對於導電區域之表 面,降低絕緣區域的表面;以及 應用壓力鎔接裝載至第一部分和第二部分用以達成第一 部份之黏合表面固態黏合至第二部份之黏合表面且用以達 成第一部份之導電區域與第二部分之導電區域之電氣連接。 根據上述建構之半導體裝置製造方法、第一和第二部份 的黏合表面被化學機械研磨,所以,碟狀部分發生在相鄰 於絕緣區域之導電區域中。然而,藉由選擇性地蝕刻在第 一部份之黏合表面和第二部分之黏合表面之至少其中之一 上的絕緣區域,絕緣區域的表面相對於導電區域的表面被 降低,所以導電區域的表面從絕緣區域的表面突出。因此 ,即使碟狀部分存在導電區域,導電區域還是安全地直接 彼此黏合。所以,可以獲得導電區域之高可靠性電氣連接。 在一具體實施例中,絕緣區域的表面藉由反應離子蝕刻 而降低。 在一具體實施例中,執行一蝕刻使得導電區域的碟狀部 份的底部之高度和絕緣區域的高度變的接近彼此相等。 圖式簡述 本發明將會從下面所給之詳細描述和僅爲説明目的所給 之隨附圖式而變的更完全地了解,因此並不限制本發明且 其中: -7- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 495958 ^ A7 B7 五、發明説明(5 ) 圖1A、1B、1C、1D和1E係爲根據本發明之一第一具體實 施例,用以解釋一半導體裝置製造方法之檢視圖; 圖2A、2B和2C係爲用以解釋第一具體實施例的蝕刻製程 之檢視圖; 圖3係爲用以解釋,立刻地在第一具體實施例的固態黏合 執行之前,的狀態之檢視圖; 圖4係爲第一具體實施例之半導體裝置的剖面圖; 圖5 A、5 B、5 C、5 D和5 E係爲用以解釋根據本發明之一第 4 二具體實施例之半導體裝置製造方法之檢視圖; 圖6A、6B和6(:係爲用以解釋第二具體實施例之蝕刻製程 之檢視圖; 圖7係爲用以解釋,立刻地在第二具體實施例的固態黏合 執行之前,的狀態之檢視圖; 圖8係爲第二具體實施例之半導體裝置之剖面圖; 較偏好具體實施例之詳細説明 在顯示在圖式中之實施例的基礎上,本發明將會在下面 詳細地描述。 圖1A到IE、2A到2 C、3和4顯示第一具體實施例的半導 體裝置製造方法。首先,如圖1A所顯示,一佈線層3提供如 當作第一基材之範例的半導體基材1上之導體層之範例。進 一步,如圖1B所顯示,一絕緣層7層壓在半導體基材1和佈 線層3上。佈線層3由,例如,銅、銘合金等等之金屬、以 不純物摻雜之多晶矽、矽化物等等所製造而絕緣層7由例如 石夕氮化物所製造。 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 - A7 B7 五、發明説明(6 ) 接下來,如圖1C所顯示,藉由顯影和乾蝕刻之技術,達 到佈線層3之貫穿孔13穿過絕緣層7而形成而一接地佈線溝8 形成在絕緣層7上。留在貫穿孔13和接地佈線溝8之間之絕 緣層7之一部份變成形成貫穿孔13之牆表面之貫穿孔絕緣體 11 〇 接下來,如圖1D所顯示,由,例如,銅所製造之導電層9 形成在絕緣層7以完全地覆蓋絕緣層7且填充貫穿孔13和接 地佈線溝8。 接下來,如圖1E所顯示,導電層9藉由根據CMP方法之研 磨而平坦化直到貫穿孔絕緣體11暴露。如上所述,藉由執 行根據CMP方法之研磨直到貫穿孔絕緣體11暴露,導電層9 隔成一由銅所製造之貫穿孔導體層5且填充貫穿孔13和一埋 藏接地佈線溝8之接地佈線層6。貫穿孔導體5的表面、貫穿 孔絕緣體11和接地佈線層6形成接近同樣高度之黏合表面12 。要注意由銅所製造之貫穿孔導體5和接地佈線層6具有比 貫穿孔絕緣體1 1的還低之硬度。所以,如圖1E和圖2A所顯 示,藉由CMP,貫穿孔導體5和接地佈線層6的表面變成碟 狀之凹面且相對於貫穿孔絕緣體11的表面被降低。即是, 以碟狀之凹面之碟狀部分17發生在貫穿孔導體5的表面。 接下來,如圖2B和2C所顯示,藉由反應離子蝕刻(RIE)方 法,貫穿孔絕緣體11選擇性地蝕刻直到貫穿孔絕緣體1 1具 有與貫穿孔導體5的碟狀部分17的底部部分1 9之高度相同之 高度。此反應離子蝕刻具有選擇性和各向異性,所以貫穿 孔絕緣體11可以細微地處理以製造具有高度接近於碟狀部 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 ^ A7 B7 五、發明説明(7 ) 分17之底部部分19之高度之貫穿孔絕緣體11。一般來説, 貫穿孔絕緣體1 1的表面高度相對於貫穿孔導體5的表面高度 被降低。即是,貫穿孔導體5從貫穿孔絕緣體11的表面突 出0 如圖3所顯示,由半導體基材1、佈線層3、絕緣層7、貫 穿孔絕緣體11、貫穿孔導體5和接地佈線層6所建構之第一 部份100因此形成。雖然沒有顯示,半導體元件例如電晶體 、電容器等等建立在第一部份100。 藉由執行十分如同第一部份100之製造‘製程之相同製程, 如圖3所顯示之第二部分200形成。該第二部分200由作爲第 二基材之半導體基材20、作爲導電層之佈線層23、絕緣層 27、作爲導電層之接地佈線層26、貫穿孔絕緣體21和貫穿 孔導體25所建構。第二部分200的黏合表面22藉由根據CMP 方法之研磨平坦化,所以,碟狀部分形成在當作導電層之 貫穿孔導體25和接地佈線層26上。然而,貫穿孔絕緣體21 藉由反應離子蝕刻選擇性地蝕刻使得貫穿孔導體25和貫穿 孔絕緣體21的碟狀部分29之底部部分具有接近相同的高度 。要注意參考號碼28表示一貫穿孔。 雖然未顯示,如電晶體、電容器等等之半導體元件建立 在第二部分2 0 0中,與第一邵份相似。 接下來,第一部份100和第二部分200之黏合表面12和22
I 遭受在眞空之潔淨製程以變成潔淨表面。換句話説,黏合 表面12和22被活化。接下來,在眞空或是惰性氣體中,製 造第一部份100之黏合表面12和第二部分200之黏合表面22 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 - A7 B7 五、發明説明(8 ) ,分別地,以貫穿孔導體5和25彼此對齊且接地佈線層6和 26彼此對齊之方式,彼此相對。之後,如圖4所顯示,藉由 應用壓力鎔接裝載F和F至第一部份100之第一半導體基材1 和第二部分200之第二半導體基材20,貫穿孔導體5和25彼 此固態黏合或在室溫下黏合(室溫黏合)而接地佈線層6和26 彼此固態黏合。之後,貫穿孔導體5和25之碟狀部分17和29 之底部部分之高度變成與貫穿孔絕緣體11和2 1之高度接近 相等。整個看來,貫穿孔導體5和25和接地佈線層6和26相 4 對於貫穿孔絕緣體11和21之表面係爲凸面的。所以,貫穿 孔導體5和接地佈線層6分別安全地固態黏合至貫穿孔導體 25和接地佈線層26。以這樣安排,貫穿孔導體5和25之電氣 連接和接地佈線層6和26之電氣連接可以在可靠性方面改 善。 空隙30發生在位於貫穿孔絕緣體11和21之間且在已經被 固態黏合(以表面啓動黏合方式)之貫穿孔導體5和25之附近 。如上所述,藉由提供空隙3 0在貫穿孔絕緣體1 1和2 1之間 ,和貫穿孔導體5和2 5和接地佈線層6和2 6之間可以分別更 安全地彼此固態黏合,使得更安全機械和電氣黏合能夠達 成。也可以接受放置貫穿孔絕緣體11和21輕微接觸或致使 其固態黏合而不需提供空隙30。如上所述,當貫穿孔絕緣 體11和21彼此固態黏合,第一部份100黏合至第二部分200 會變的更牢固。 在前面提及之具體實施例中,貫穿孔絕緣體1 1和2 1之表 面相對應於在第一部份100之黏合表面12和第二部分200之 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 - A7 B7 五、發明説明(9 ) 黏合表面22兩者上之貫穿孔導體5和25之表面被降低。然而 ,可接受執行蝕刻使得貫穿孔貫穿孔絕緣體相對應於在一 黏合表面上之貫穿孔導體之表面要低的多且使得貫穿孔導 體之碟狀部分之整個表面比貫穿孔絕緣體之表面要低而不 需執行蝕刻用以調整在另一黏合表面上之貫穿孔絕緣體之 高度。即使以此安排,藉由增加一貫穿孔絕緣體之蝕刻之 數量,貫穿孔導體可以安全電氣地連接彼此,即使碟狀部 分存在。 圖5A到5E,6A到6C,7和8係爲用以解釋第二具體實施例 之半導體裝置製造方法之檢視圖。如圖7和8清楚地顯示, 一第一部份100具有與第一具體實施例之第一部份100相同 的建構且經由相同製程製造。所以,沒有描述提供於第一 部份100且使用如用於第一具體實施例之相同參考號碼。 第二部分300經由顯示在圖5A到5E和6A到6C之製程而製 造。首先,如圖5A所顯示,佈線層33提供如作爲第二基材 之範例之半導體基材3 1上之導體層之範例。進一步,如圖 5B所顯示,一絕緣層37層壓在半導體基材31和佈線層33上 。佈線層3 3由,例如,以不純物摻雜之多晶石夕、銅、銘合 金等等所製造,而絕緣層37由例如矽氮化物、矽氧化物等 等所製造。 接下來,如圖5 C所顯示,藉由顯影和乾#刻之技術,達 到佈線層33之貫穿孔43穿過絕緣層37而形成。 接下來,如圖5D所顯示,由例如多晶矽所製造之導電層 39形成在位於貫穿孔43之底部之絕緣體37和佈線層33以填 -12- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐) 495958 A7 B7 五、發明説明(1Q ) 滿貫穿孔43。 接下來,如圖5E所顯示,導電層39和絕緣層37藉由根據 CMP方法之研磨而平坦化。藉由執行根據CMP方法之研磨 ,在貫穿孔43和絕緣層37内之貫穿孔導體35的表面形成具 有接近同樣高度之黏合表面42。要注意由多晶矽所製造之 貫穿孔導體35具有比由矽氮化物所製造之絕緣層37還低之 硬度。、所以,如圖5E和圖6A所顯示,藉由CMP,貫穿孔導 體35的表面變成碟狀之凹面且相對於絕緣層37的表面被降 4 低。即是,碟狀之凹面之碟狀部分47發生在貫穿孔導體35 的表面。 接下來,如圖6 B和6 C所顯示,藉由反應離子蚀刻方法, 絕緣層37選擇性地蝕刻直到絕緣層37具有與貫穿孔導體35 的碟狀部分47的底部部分49之高度相同之高度。一般來説 ,絕緣層37的表面高度相對於貫穿孔導體35的表面高度被 降低。即是,貫穿孔導體35從絕緣層37的表面突出。 如圖7所顯示,由半島體基材3 1、佈線層3 3、絕緣層3 7和 貫穿孔導體35所建構之第二部分300因此形成。 接下來,第一部份100和第二部分300之黏合表面12和42遭 受在眞空之潔淨製程以變成潔淨表面。換句話説,黏合表面 12和42被活化。接下來,在眞空或是惰性氣體中,製造第一 部份100之黏合表面12和第二部分300之黏合表面42,以貫 穿孔導體5和35彼此對齊之方式,彼此相對。之後,如圖8 所顯示,藉由應用壓力,即是,壓力鎔接裝載F和F至第一 部份100之第一半導體基材1和第二部分300之第二半導體基· ' -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 495958 - A7 B7 ____ 五、發明説明(11 ) 材31,貫穿孔導體5和35彼此固態黏合而接地佈線層6和絕 緣層37彼此固態黏合。之後,貫穿孔導體5之碟狀部分17之 底部部分之高度變成與貫穿孔絕緣體1 1之高度接近相等。 貫穿孔導體5和接地佈線層6相對於貫穿孔絕緣體11係爲完 全地凸面。此外,貫穿孔導體35之碟狀部分47之底部部分 之高度與絕緣層37之高度接近相等且貫穿孔導體35相對於 絕緣層3 7係爲凸面的。所以,貫穿孔導體5和貫穿孔導體3 5 安全地彼此固態黏合而接地佈線層6和絕緣層3 7彼此安全地 固態黏合。以這樣安排,貫穿孔導體5和35之機械連接和電 氣連接及接地佈線層6和絕緣層3 7之電氣連接可以在可靠性 方面獲得改善。 空隙40發生在位於貫穿孔絕緣體11和絕緣層37之間且在 已經被固態黏合之貫穿孔導體5和35之附近。如上所述,藉 由提供空隙40在貫穿孔絕緣體11和絕緣層37之間,貫穿孔 導體5至貫穿孔導體35之固態黏合及接地佈線層6至絕緣層 37之固態黏合可以因更安全的機械和電氣黏合而獲得進一 步保障。也可以接受放置貫穿孔絕緣體1 1和絕緣層3 7輕微 接觸或使其固態黏合而不需提供空隙40。如上所述,當貫 穿孔絕緣體11和絕緣層37彼此固態黏合,第一部份1〇〇至第 二部分300之黏合會變的更牢固。 在前述第一或第二具體實施例中,絕緣區域(貫穿孔絕緣 體和絕緣層)11、21和37圍繞導電區域(貫穿孔導體)5、25 和3 5在黏合表面12、22和42上。然而,絕緣層區域不需要 圍繞分別導電區域而只需要提供導電區域和絕緣區域。也 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 ^ A7 B7 五、發明説明(12 ) 可接受一黏合表面具有導電區域和絕緣區域而其他黏合區 域只具有導電區域。根據本發明之具體實施例,蚀刻絕緣 區域使得在導電區域中之碟狀部分突出在絕緣區域上在被 CMP方法研磨之黏合表面上。所以,假如至少一黏合表面 具有導電區域和絕緣區域,本發明也可應用。 根據第一或第二具體實施例,貫穿孔導體5固態黏合至貫 穿孔導體25或35而接地佈線層6固態黏合至接地佈線層26或 絕緣層3 7。然而,本發明當然並不侷限於此。例如,固態 4 黏合一絕緣層至一絕緣層或固態黏合複數個佈線層和貫穿 孔導體至一作爲導電層之電源供應層係可接受的。也可接 受固態黏合複數個佈線層至彼此。 雖然在前述具體實施例中,導電層由銅或多晶矽所製造 ,導電層也可由,例如,梦化物、銘合金等等所製造,而 絕緣層可以由除矽氮化物之外也可由矽氧化物製造。 雖然在前述具體實施例中半導體基材使用爲基材,使用 無機物之基材如玻璃基材和陶瓷基材或是由有機化合物所 製造之有機基材係可接受的。 雖然前述的具體實施例使用反應離子蝕刻作爲蝕刻,使 用其他乾蝕刻例如反應濺擊蚀刻、電漿蝕刻、離子束蝕刻 和照片蝕刻或濕蝕刻係可接受的。 從上面明顯的看到,根據本發明之半導體裝置,絕緣區 域相對於在被CMP方法所研磨之兩黏合表面至少其中之一 上之導電區域被降低且之後以固態黏合。所以,導電區域 可以安全地遭受固態黏合且安全地電氣地連接彼此。 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495958 . A7 _______B7 五、發明説明(13 ) ' 並且,根據本發明之半導體裝置製造方法,絕緣區域選 擇性地蝕刻使得絕緣區域的表面相對於在被CMp方法所研 磨之兩黏合表面至少其中之一上之導電區域之表面被降低 。所以,導電區域可以安全地遭受固態黏合且安全地電氣 地連接彼此即使碟狀部分存在導電區域上。 ' 本發明被如此描豸,其可被以許多方式變化係明顯的。 如此變化並不被視爲背離本發明之精神與範圍且對於熟習 此技藝的人士來説所有如此的修改係明顯的,其被意圖包 括在下面申請專利範圍之範圍中。 .# 參考號碼 1、2〇、3丨:半導體基材 3、23、33 :佈線層 5、 25、35 :貫穿孔導體 6、 2 6 :接地佈線層 7、 27、37 :絕緣層 1 1、2 1 :貫穿孔絕緣體 13、28、43 :貫穿孔 17、29、47 :碟狀部分 19、49 :底部部分 -16-
Claims (1)
- ι· 一種半導體裝置,其包括: 、申請專利範圍 第 =:其,:第—基材、一導電層和, 經濟部智慧財產局員工消費合作社印製 層,其層壓在第一基材和一黏合表面一 研磨且暴露一導電區域和一絕緣區域; 弟一部分,其具有一第二基材、一導電層和 二,其=壓在第:基材和黏合表面上,其被化學機械研 磨且暴露至少一導電區域; 弟一邵份的黏合表面和第二部份的黏合表面彼此 黏合,以及 , a 罘一邵份的黏合表面和第二部份的黏合表面之至少其 中之一具有相對於導電區域要低之絕緣區域。 " 2. 如申請專利範圍第巧之半導體裝置,其中導電區域 狀邵分彼此黏合。 3. 如申請專利範圍第巧之半導體裝置’其中第—部份之道 電區域和第二部分之導電區域彼此固態黏合且第一㈣ 〈絕緣區域和第二部分之絕緣區域有一空隙介入而彼此 面對。 如申請專利範圍第3項之半導體裝置,其中圍繞第一部份 的導電區域之絕緣區域和圍繞第二部份的導電區域之絕 緣區域有一空隙介入而彼此面對。 如申請專利範圍第上項之半導體裝置,其中第一部份的導 電區域和第二部份的導電區域彼此固態黏合且第一部份 的絕緣區域和第:部份的絕緣區域彼此接觸或是彼此固 態黏合。 其被化學機械 2f先閱讀背面之注意事項再本頁) 本 · -線· 4. 適时ϊϋϋΤ^Αίϋ (21〇 -17- χ 297^1Τ 495958 經濟部智慧財產局員工消費合作社印制取 A8 B8 C8 - D8六、申請專利範圍 6. 如申請專利範圍第5項之半導體裝置,其中圍繞第一部份 的導電區域之絕緣區域和圍繞第二部份的導電區域之絕 緣區域彼此接觸或是彼此固態黏合。 7. 如申請專利範圍第4項之半導體裝置,其中導電區域係爲 貫穿孔導體之末端表面,而絕緣區域係爲圍繞相對貫穿 孔導體之貫穿絕緣體之末端表面。 8. 如申請專利範圍第6項之半導體裝置,其中導電區域係爲 貫穿孔導體之末端表面,而絕緣區域係爲圍繞相對貫穿 孔導體之貫穿絕緣體之末端表面。 .· 9. 如申請專利範圍第1項之半導體裝置,其中第一基材或是 第二基材係爲半導體基材、無機基材或是有機基材其中 任何一種。 10. —種半導體裝置製造方法,其包括下面步驟: 形成一第一部份,其具有一第一基材、一導電層和一 絕緣層,其層壓在第一基材和一黏合表面上,其被化學 機械研磨且暴露一導電區域和一絕緣區域; 形成一第二部分,具有一第二基材、一導電層和一絕 緣層,其層壓在第二基材和一黏合表面上,其被化學機 械研磨且暴露至少一導電區域; 選擇性地蚀刻第一邵份的黏合表面和第二部份的黏合 表面之至少其中之一的絕緣區域,藉此降低相對於導電 區域表面之絕緣區域的表面;以及 應用壓力鎔接裝載至第一部分和第二部分用以達成第 一部份的導電區域和第二部份的導電區域之電氣連接。 (請先閱讀背面之注意事項再本頁) -裝 女 訂. .線· -18- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 495958 A8 -B8 C8 D8六、申請專利範圍 11. T申請專利範圍第10項之半導體裝置製造方法,其中絕 緣區域的表面藉由反應離子蝕刻而降低。 α經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 12. 如申請專利範圍第1〇項之半導體裝置製造方法,其中執 仃一蝕刻使得導電區域的碟狀部份的底部之高度和絕緣 區域的高度變的接近彼此相等。 V 如申請專利範圍第10項之半導體裝置製造方法,其中第 —二份之導電區域和第二部分之導電區域彼此固態黏合 且第一部份I絕緣區域和第二部‘分之絕緣區域有一空隙 介入而彼此面對。 , ' 14. 如申請專利範_第13項之半導體裝置製造方法,其中圍 =第一部份的導電區域之絕緣區域和圍繞第二部份的導 %區域之絕緣區域有一空隙介入而彼此面對。 15. 如申請專利範圍第10項之半導體裝置製造方法,其中第 4知的導電區域和第二部份的導電區域彼此固態黏合 且第一部份的絕緣區域和第二部份的絕緣區域彼此接觸 或是彼此固態黏合。 16· 1\申請專利範圍第15項之半導體裝置製造方法,其中圍 =第一邵份的導電區域之絕緣區域和圍繞第二部份的導 %區域之絕緣區域彼此接觸或是彼此固態黏合。 17· 2申請專利範圍第14項之半導體裝置製造方法,其中導 兒區域係爲男牙孔導體之末端表面而絕緣區域係爲圍繞 相對貫穿孔導體之貫穿絕緣體之末端表面。 18· 2申請專利範圍第16項之半導體裝置製造方法,其中導 包區域係爲貫穿孔導體之末端表面而絕緣區域係爲圍繞 L_____ _ 19_ 本紙張尺度適家標準(CNS)A4規格⑽χ 297公髮) 495958 A8 B8 C8 D8 、申請專利範圍 相對貫穿孔導體之貫穿絕緣體之末端表面。 19.如申請專利範圍第10項之半導體裝置製造方法,其中第 一基材或是第二基材係爲半導體基材、無機基材或是有 機基材其中任何一種。 --------;-------裝· —— (請先閱讀背面之注意事項再本頁) 訂· .線· 經濟部智慧財產局員工消費合作社印製 -20- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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TWI562280B (en) * | 2005-08-11 | 2016-12-11 | Ziptronix Inc | 3d ic method and device |
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JP3440057B2 (ja) | 2003-08-25 |
DE10132024A1 (de) | 2002-01-24 |
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US20020003307A1 (en) | 2002-01-10 |
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