TW255086B - Shared-buffer memory asynchronous transfer mode exchange - Google Patents

Shared-buffer memory asynchronous transfer mode exchange

Info

Publication number
TW255086B
TW255086B TW84100108A TW84100108A TW255086B TW 255086 B TW255086 B TW 255086B TW 84100108 A TW84100108 A TW 84100108A TW 84100108 A TW84100108 A TW 84100108A TW 255086 B TW255086 B TW 255086B
Authority
TW
Taiwan
Prior art keywords
packet
queue
buffer memory
address
shared
Prior art date
Application number
TW84100108A
Other languages
Chinese (zh)
Inventor
Yu-Sheng Lin
Chun-Shen Xiang
Shyng-Jiann Hwang
Original Assignee
Telecomm Lab Dgt Motc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecomm Lab Dgt Motc filed Critical Telecomm Lab Dgt Motc
Priority to TW84100108A priority Critical patent/TW255086B/en
Application granted granted Critical
Publication of TW255086B publication Critical patent/TW255086B/en

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

A re-circulating queue manager of shared-buffer memory asynchronous transfer mode exchange includes: (1) one back-pressure interface which receives back-pressure signal from back stage and stores in register, supplying address generator check, and based on it to decide the pause of output port packet transmittance; When the buffer memory is full, the back-pressure interface send back-pressure signal to front stage; (2) one address generator consisting of a programmable logic array, a queue selector, a queue address pointer file, a state register file and a queue memory; The address generator arranges each input packet to its output queue based on the destination port address of each packet, and the packet reading out sequence of each output queue; The generated address is used to read or write the packet in the shared-buffer memory; And controlling the input interface and output interface based on system timing signal; (3) one timing generator which generates each kind of timing signals needed by system based on system timing and packet start signal.
TW84100108A 1995-01-09 1995-01-09 Shared-buffer memory asynchronous transfer mode exchange TW255086B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW84100108A TW255086B (en) 1995-01-09 1995-01-09 Shared-buffer memory asynchronous transfer mode exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW84100108A TW255086B (en) 1995-01-09 1995-01-09 Shared-buffer memory asynchronous transfer mode exchange

Publications (1)

Publication Number Publication Date
TW255086B true TW255086B (en) 1995-08-21

Family

ID=51401585

Family Applications (1)

Application Number Title Priority Date Filing Date
TW84100108A TW255086B (en) 1995-01-09 1995-01-09 Shared-buffer memory asynchronous transfer mode exchange

Country Status (1)

Country Link
TW (1) TW255086B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6122279A (en) * 1995-10-02 2000-09-19 Virata Limited Asynchronous transfer mode switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6122279A (en) * 1995-10-02 2000-09-19 Virata Limited Asynchronous transfer mode switch

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