KR960027878A - Transmission buffer erase circuit of SSCOP sublayer - Google Patents

Transmission buffer erase circuit of SSCOP sublayer Download PDF

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Publication number
KR960027878A
KR960027878A KR1019940038187A KR19940038187A KR960027878A KR 960027878 A KR960027878 A KR 960027878A KR 1019940038187 A KR1019940038187 A KR 1019940038187A KR 19940038187 A KR19940038187 A KR 19940038187A KR 960027878 A KR960027878 A KR 960027878A
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KR
South Korea
Prior art keywords
ram
registers
pointer
transmission buffer
register
Prior art date
Application number
KR1019940038187A
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Korean (ko)
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KR0129177B1 (en
Inventor
윤성욱
Original Assignee
배순훈
대우전자 주식회사
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Priority to KR1019940038187A priority Critical patent/KR0129177B1/en
Publication of KR960027878A publication Critical patent/KR960027878A/en
Application granted granted Critical
Publication of KR0129177B1 publication Critical patent/KR0129177B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 SSCOP계층의 전송버퍼 삭제회로에 관한 것으로, 입력된 포인터 값에 의해 전송버퍼의 어느 한 램을 지시하게된 N개의 램레지스터(10)와; 소정의 램레지스터(10)의 포인터를 일시 저장하게 된 제1,2레지스터(12, 14); 외부로부터램레지스터(10)의 번호를 순차적으로 입력받아 해당 램레지스터(10)에 저장된 포인터값을 읽어 상기 제1,2레지스터(12, 14); 에 출력하게 된 디먹스(16); 상기 디먹스(16)에 입력되는 램레지스터(10)의 번호를 지연부(18)를 통해 입력받아 소정의 지연시간 후에 해당 램레지스터(10)를 기록 가능하게 제어해주는 디코더(20) 및; 상기 디코더(20)의 제어신호에 의해 상기 제1,2레지스터(12,14)에 저장된 포인터값을 교환하여 입력해 주게 된 멀티플렉서(22)로 구성되어, 전송버퍼를 구성하는 램의 데이터를 지울 필요없이 램레지스터에 저장된 해당 메시지의 포인터값만을 램레지스터의 마지막 사용된 램레지스터의 포인터값과 교환하여 주므로써 메시지의 삭제가 가능하게 되는 효과가 있는 것이다.The present invention relates to a transmission buffer erasing circuit of the SSCOP layer, comprising: N number of RAM registers 10 indicating one of the transmission buffers by an input pointer value; First and second registers 12 and 14 which temporarily store a pointer of a predetermined ram register 10; First and second registers 12 and 14 which sequentially receive the numbers of the ram registers 10 from the outside and read the pointer values stored in the ram registers 10; Demux 16 to be output to; A decoder 20 which receives the number of the ram registers 10 input to the demux 16 through the delay unit 18 and controls the ram register 10 to be recordable after a predetermined delay time; It consists of a multiplexer 22 which exchanges and inputs pointer values stored in the first and second registers 12 and 14 according to the control signal of the decoder 20 to erase data of the RAM constituting the transmission buffer. The message can be deleted by exchanging only the pointer value of the corresponding message stored in the RAM register with the pointer value of the last used RAM register.

Description

SSCOP부계층의 전송버퍼 삭제회로Transmission buffer erase circuit of SSCOP sublayer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 SSCOP부계층의 전송버퍼 삭제 회로를 도시한 구성블럭도이다.4 is a block diagram showing a transmission buffer erasing circuit of the SSCOP sublayer according to the present invention.

Claims (1)

입력된 포인터값에 의해 전송버퍼의 어느 한 램을 지시하게 된 N개의 램레지스터(10)와; 소정의 램레지스터(10)의 포인터를 일시 저장하게 된 제1,2레지스터(12,14); 외부로부터 램레지스터(10)의 번호를 순차적으로 입력받아 해당 램레지스터(10)에 저장된 포인터값을 읽어 상기 제1,2레지스터(12,14)에 출력하게 된 디먹스(16); 상기디먹스(16)에 입력되는 램레지스터(10)의 번호를 지연부(18)를 통해 입력받아 소정의 지연시간 후에 해당 램레지스터(10)를 기록 가능하게 제어해주는 디코더(20) 및; 상기 디코더(20)의 제어신호에 의해 상기 제1,2레지스터(12,14)에저장된 포인터값을 교환하여 입력해주게 된 멀티플렉서(22)로 구성된 SSCOP부계층의 전송버퍼 삭제회로.N RAM registers 10 indicating one RAM of the transmission buffer by the input pointer value; First and second registers 12 and 14 which temporarily store a pointer of a predetermined ram register 10; A demux 16 which sequentially receives the numbers of the ram registers 10 from the outside and reads the pointer values stored in the ram registers 10 and outputs them to the first and second registers 12 and 14; A decoder 20 which receives the number of the ram registers 10 input to the demux 16 through the delay unit 18 and controls the ram register 10 to be recordable after a predetermined delay time; And a multiplexer (22) configured to input and exchange pointer values stored in the first and second registers (12, 14) by a control signal of the decoder (20). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038187A 1994-12-28 1994-12-28 A circuit for deleting data from send buffer of sscop sublayer KR0129177B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038187A KR0129177B1 (en) 1994-12-28 1994-12-28 A circuit for deleting data from send buffer of sscop sublayer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038187A KR0129177B1 (en) 1994-12-28 1994-12-28 A circuit for deleting data from send buffer of sscop sublayer

Publications (2)

Publication Number Publication Date
KR960027878A true KR960027878A (en) 1996-07-22
KR0129177B1 KR0129177B1 (en) 1998-04-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038187A KR0129177B1 (en) 1994-12-28 1994-12-28 A circuit for deleting data from send buffer of sscop sublayer

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Publication number Publication date
KR0129177B1 (en) 1998-04-08

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