TW201601253A - 具緊湊型互補式金氧半場效電晶體絕緣的積體電路及其製備方法 - Google Patents
具緊湊型互補式金氧半場效電晶體絕緣的積體電路及其製備方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 17
- 238000002955 isolation Methods 0.000 title description 16
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims description 43
- 238000009413 insulation Methods 0.000 claims description 14
- 230000000295 complement effect Effects 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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Abstract
一種積體電路包括一個第一導電類型的第一阱,形成在半導體層中,第一阱罩住有源元件,並且連接到第一阱電勢;一個第二導電類型的第二阱,形成在半導體層中,包圍著第一阱,第二阱罩住有源元件,並且連接到第二阱電勢;一個第二導電類型的掩埋層,形成在第一阱下方,並且部分重疊包圍著第一阱的第二阱。在一個較佳實施例中,積體電路包括一個第二導電類型的第三阱,取代掩埋層,第三阱含有第一阱,並且部分基底包圍著第一阱的第二阱。
Description
本發明涉及一種功率積體電路,具體涉及一種緊湊CMOS元件絕緣結構的積體電路及其製備方法。
高壓應用的單片功率積體電路(PIC)有時集成在類比和數位電路上。例如,一種直流-直流轉換器類型的功率積體電路,可以在一個單獨的積體電路上集成控制器和一個或兩個電源開關。也因此,構成功率積體電路中類比電路的互補式金氧半場效電晶體(CMOS)元件,必須與雜訊基底絕緣,以避免由雜訊引起的電路故障。確切地說,類比電路通常包括頻帶間隙、放大器和傳感電路等敏感電路。數位電路通常包括振盪器、邏輯電路和PWM控制器。傳統的功率積體電路包括類比電路和數位電路各自的接地連接(類比接地和數位接地)。功率積體電路的基底(通常為P-型基底),通常連接到數位接地,數位時鐘電路的開關動作導致數位接地趨近於雜訊。功率積體電路的敏感CMOS類比電路必須與P-型基底和雜訊模擬接地絕緣。
在CMOS類比電路中,PMOS元件由於形成在N-阱中,因此與P-型基底自我絕緣。然而,NMOS元件形成在P-阱中,如果不絕緣的話,就會直接連接到P-型基底。傳統的功率積體電路利用一個N-型掩埋層(“N-掩埋層”)和漏極端N-型掩埋層的深N-阱環,使CMOS元件與P-基底絕緣。圖1和2表示在積體電路中傳統的CMOS元件絕緣結構。參見圖1和2,積體電路1通常使用一個或多個電路模組1至3製成,每個電路模組都含有類比或數位電路。在本例中,每個電路模組1至3都與CMOS元件絕緣結構絕緣,CMOS元件絕緣結構包括一個深N-阱環5和一個N-型掩埋層14,在環5限定的電路模組內的整個區域下方。如圖2所示的電路模組10示例,N-掩埋層14延伸,穿過深N-阱環5之間的電路模組下方的整個區域。PMOS和NMOS元件形成在各自的N-阱18和P-阱20中,在N-掩埋層14上方的外延層13中。因此,PMOS和NMOS元件被深N-阱環5和N-掩埋層14完全包圍,與P-型基底12絕緣,P-型基底12通常連接到數位接地。雖然使類比電路模組和雜訊P-型基底絕緣更加關鍵,但是傳統的積體電路通常使類比和數位電路模組絕緣,以保持基底的雜訊較低,導致從基底到類比模組測試較低的雜訊耦合。
雖然傳統的CMOS元件絕緣結構非常有效,但由於使用了深N-阱,使絕緣結構佔據了很大面積的矽。深N-阱通常與很大的向外擴散有關,故在鄰近的深N-阱之間必須具有很大的間距。因此,利用傳統的CMOS元件絕緣結構製成的積體電路晶片尺寸很大,增加了積體電路的成本。
本發明目的是提供一種具緊湊型互補式金氧半場效電晶體(CMOS)元件絕緣結構的積體電路及其製備方法,縮小了元件絕緣所需的矽面積,從而降低了積體電路的晶片尺寸和成本,同時有利於保持基底雜訊較低,使得從基底到類比模組的雜訊耦合較低。
為了達到上述目的,本發明通過以下技術方案實現:
一種具緊湊型CMOS絕緣的積體電路,其特點是,包括:
一第一導電類型輕摻雜的半導體層;
一第一導電類型的第一阱,形成在半導體層中,所述的第一阱罩住有源元件,並且連接到第一阱電勢;
一第二導電類型的第二阱,形成在半導體層中,包圍著第一阱,所述的第二阱罩住有源元件,並且連接到第二阱電勢;以及
一第二導電類型的掩埋層,形成在第一阱下方,至少部分重疊包圍著所述第一阱的第二阱。
所述的掩埋層與第二阱接觸。
所述的掩埋層形成在第二阱周圍,但不與第二阱接觸。
所述的掩埋層與整個第二阱重疊。
所述的半導體層包括:一第一導電類型的半導體基底;以及一第一導電類型的外延層,形成在所述的半導體基底上,所述的掩埋層形成在半導體基底上。
所述的第一阱罩住第二導電類型的MOS電晶體,作為有源元件。
所述的第二阱罩住第一導電類型的MOS電晶體,作為有源元件。
所述的第一導電類型為P-型,第二導電類型為N-型。
所述的第一阱的第一阱電勢包括第一接地電勢,半導體層電連接到第二接地電勢,通過第二阱和掩埋層,第一接地電勢與第二接地電勢絕緣。
所述的第二阱的第二阱電勢包括一個正電壓源電壓。
一種用於製備積體電路的方法,其中,包括:
製備第一導電類型的半導體層,並且輕摻雜;
在半導體層中製備第一導電類型的第一阱,第一阱罩住有源元件,並且連接到第一阱電勢;
在半導體層中製備第二導電類型的第二阱包圍著第一阱,第二阱罩住有源元件,並且連接到第二阱電勢;並且
在第一阱下方,製備第二導電類型的掩埋層,並且部分重疊包圍著第一阱的第二阱。
所述製備第二導電類型的掩埋層,包括:製備第二導電類型的掩埋層,與所述第二阱接觸。
所述製備第二導電類型的掩埋層包括:製備第二導電類型的掩埋層,在所述第二阱附近,但不與第二阱接觸。
所述製備第二導電類型的掩埋層,包括:製備第二導電類型的掩埋層,重疊整個第二阱。
所述製備第一導電類型的半導體層並且輕摻雜,包括:製備第一導電類型的半導體基底;並且在所述的半導體基底上,製備第一導電類型的外延層,其中掩埋層形成在半導體基底上。
所述的第一阱罩住第二導電類型的MOS電晶體,作為有源區。
所述的第二阱罩住第一導電類型的MOS電晶體,作為有源區。
所述的第一導電類型為P-型,所述的第二導電類型為N-型。
所述第一阱的第一阱電勢包括第一接地電勢,半導體層電連接到第二接地電勢,通過第二阱和掩埋層,第一接地電勢與第二接地電勢絕緣。
所述第二阱的第二阱電勢包括正電壓源電壓。
一種積體電路,包括:
一第一導電類型的半導體層,並且輕摻雜;
一第一導電類型的第一阱,形成在半導體層中,第一阱罩住有源元件,並且連接到第一阱電勢;
一第二導電類型的第二阱,形成在半導體層中,包圍著第一阱,第二阱罩住有源元件,並且連接到第二阱電勢;以及
一第二導電類型的第三阱,形成在半導體層中,第三阱含有第一阱,並且至少部分重疊包圍著第一阱的第二阱。
所述的第三阱包括一個第二導電類型的深阱。
本發明與現有技術相比具有以下優點:
本發明縮小了元件絕緣所需的矽面積,從而降低了積體電路的晶片尺寸和成本,同時有利於保持基底雜訊較低,使得從基底到類比模組的雜訊耦合較低。
本發明可以以各種方式實現,包括作為一個工藝;一種裝置;一個系統;和/或一種物質合成物。在本說明書中,這些實現方式或本發明可能採用的任意一種其他方式,都可以稱為技術。一般來說,可以在本發明的範圍內變換所述工藝步驟的順序。
本發明的一個或多個實施例的詳細說明以及附圖解釋了本發明的原理。雖然,本發明與這些實施例一起提出,但是本發明的範圍並不局限於任何實施例。本發明的範圍僅由申請專利範圍限定,本發明包含多種較佳方案、修正以及等效方案。在以下說明中,所提出的各種具體細節用於全面理解本發明。這些細節用於解釋說明,無需這些詳細細節中的部分細節或全部細節,依據申請專利範圍,就可以實現本發明。為了條理清晰,本發明相關技術領域中眾所周知的技術材料並沒有詳細說明,以免對本發明產生不必要的混淆。
在本發明的實施例中,互補式金氧半場效電晶體(CMOS)積體電路中的緊湊CMOS元件絕緣體系構成一個含有PMOS元件的N-阱環,包圍著電路模組中含有NMOS元件的P-阱,還在P-阱下方構成一個的掩埋層。換言之,形成NMOS元件的P-阱,被形成PMOS元件的N-阱包圍著。N-型掩埋層形成在P-阱下方,部分延伸到周圍的N-阱下方。緊湊CMOS元件絕緣體系免去了在電路模組周圍使用深N-阱環。因此,積體電路的電路模組可以具有很小的矽面積,減小用於配置積體電路的晶片尺寸。
更確切地說,本發明所述的緊湊CMOS元件絕緣體系,利用N-掩埋層和周圍的PMOS元件的N-阱,提供NMOS元件的絕緣。通過形成在N-阱中,PMOS元件自我絕緣。從而,無需使用消耗很大矽面積的深N-阱環,就可以實現有效的元件絕緣。
圖3表示依據本發明的實施例,配置緊湊CMOS元件絕緣結構的CMOS積體電路俯視圖。參見圖3,CMOS積體電路50包括電路模組1至4,每個電路模組1至4都含有類比電路和數位電路,每個電路模組都含有PMOS和NMOS元件互連,以構成各自的數位或類比電路。PMOS元件形成在N-阱52中,而NMOS元件形成在P-阱54中。在本發明的實施例中,在每個電路模組中,形成NMOS元件所在的P-阱54,被形成PMOS元件所在的N-阱52包圍著。形成在P-阱54中的NMOS元件還通過N-型掩埋層(圖中沒有表示出),與基底絕緣。按照這種方式,元件絕緣無需深N-阱環,利用較小的矽面積,可以製成積體電路的電路模組。緊湊CMOS元件絕緣體系縮小了元件絕緣所需的矽面積,從而降低了積體電路50的晶片尺寸和成本。
在本發明的實施例中,緊湊CMOS元件絕緣結構可用於類比電路模組和數位電路模組。由於形成在其中的敏感類比電路必須與經常連接到數位接地的雜訊基底絕緣。數位電路模組的絕緣有利於保持基底雜訊較低,使得從基底到類比模組的雜訊耦合較低。
圖4表示依據本發明的實施例,利用緊湊CMOS元件絕緣結構製成的積體電路的電路模組剖面圖。在以下說明中,使用的參數與積體電路中相同類型的擴散區或相同類型的層參數都相同。參見圖4,電路模組60形成在積體電路上,例如圖3所示的積體電路50,可以是類比電路模組或數位電路模組。在本示例中,假設電路模組60為類比電路模組。電路模組60形成在含有P-型基底62和P-型外延層63的半導體層中。為了配置本發明所述的緊湊CMOS元件絕緣結構,電路模組60包括一個形成在電路模組週邊的N-阱68的環,包圍著P-阱70,N-型掩埋層64形成在P-阱70下方。N-型掩埋層64沿電路模組的周邊,部分延伸到周圍的N-阱68下方。
在本實施中,N-阱68有時被稱為“N-阱環”,以表示一個封閉式迴圈阱結構。要理解,N-阱不必為圓環形,但是可以是適合包圍P-阱的任意形狀。
在電路模組60中,PMOS元件形成在N-阱68中,而NMOS元件形成在P-阱70中。例如,在本示例中,PMOS電晶體形成在N-阱68中,包括重摻雜的P+區76,作為源極和漏極區,導電柵極電極72通過柵極電介質71,與半導體層絕緣。PMOS元件可以形成在N-阱68週邊的任意位置,包圍著P-阱70。N-阱68不是一個專用絕緣結構,而是形成有源元件所在的有源區。在本說明中,有源元件是指電晶體、電阻器、電容器和電感器,或用於製作積體電路的其他電路元件,有別於單純用於非功能性的結構和元件(例如絕緣),或用於製備工藝調整。
另外,在本實施例中,NMOS電晶體形成在N-阱68中,含有重摻雜N+區74作為源極和漏極區,導電柵極電極72通過柵極電介質71,與半導體層絕緣。當電路模組60為類比電路模組時,容納NMOS元件的P-阱70連接到模擬接地接頭。同時,P-型基底62連接到數位接地接頭,電路模組形成在P-型基底62上。
這樣一來,PMOS元件通過形成在P-型外延層63中的N-阱中,實現PMOS元件的自我絕緣。N-阱68連接到正電壓源電壓Vdd,而P-基底和P-型外延層63構成的P-型半導體層連接到數位接地。因此,到P-基底結的N-阱反向偏置,從而絕緣。另一方面,通過周圍的N-阱68和N-掩埋層64,P-阱70與P-型基底62絕緣。這樣一來,類比接地接頭與雜訊數位接地接頭絕緣。數位接地接頭中的雜訊不會耦合到形成在電路模組60中的敏感類比接地和類比電路。
在本實施例中,合併N-阱68和N-型掩埋層64。也就是說,N-阱68與N-型掩埋層64接觸,因此這兩個區域直徑電連接。換言之,N-型掩埋層形成在N-阱環附近,但是不與N-阱環合併或接觸,如圖5所示。參見圖5,在電路模組80中,NMOS元件形成在P-阱70中,P-阱70被N-阱環68包圍。在本實施例中,N-型掩埋層84形成在P-阱70下方,使P-阱絕緣,但是N-型掩埋層84形成在N-阱環68附近,但不與N-阱環68合併。N-掩埋層84保持浮動。雖然,N-掩埋層84和N-阱環68沒有直接連接,但是這兩個區域是通過形成在這兩個區域之間的耗盡區弱連接。更確切地說,即使N-掩埋層84沒有偏置時,掩埋層中的內建電勢都會使耗盡區形成在N-掩埋層周圍。形成在N-掩埋層84和偏置N-阱環68周圍的耗盡區會合並,並且電連接這兩個區域。按照這種方式,即使N-掩埋層84沒有與N-阱環68合併,仍然可以通過N-掩埋層84和穿過耗盡區的N-阱環68的電連接,實現P-阱與基底的絕緣。
在一些實施例中,即使N-阱環68和N-掩埋層84沒有通過耗盡區合併,只要這兩個區域之間的間距很小,N-阱環68和N-掩埋層84都將有效夾緊P-外延層83,以至於P-阱70和P-型基底62之間的電阻增大。按照這種方式,N-阱環68和N-掩埋層84為P-阱70(連接到模擬接地)和P-型基底62(連接到數位接地)提供足夠的電絕緣。
在圖4和5所示的實施例中,N-掩埋層形成在P-阱下方,僅部分重疊N-阱環。在其他實施例中,N-掩埋層可以與N-阱環68重疊。在一些情況下,需要緊湊晶片尺寸時,因為N-掩埋層具有更多的向外擴散,因此將N-掩埋層從N-阱環邊緣往回拉十分有利,掩埋層之間需要的間距大於N-阱之間所需的間距。
圖6表示依據本發明的較佳實施例,使用緊湊型CMOS元件絕緣結構製成的積體電路的電路模組剖面圖。在一些情況下,利用非外延工藝可以製備積體電路,從而掩埋層不可用。在本發明的實施例中,使用含有絕緣P-阱並且部分重疊周圍的N-阱環的深N-阱,實現緊湊CMOS元件絕緣。
參見圖6,電路模組100形成在積體電路中,積體電路形成在P-型基底102中。在電路模組100中,PMOS元件形成在N-阱108中,而NMOS元件形成在P-阱107中。N-阱108構成一個環,包圍P-阱107以便絕緣。由於掩埋層不可用,因此P-阱107形成在深N-阱106中。在一些實施例中,利用P-型基底102表面的離子注入,以及熱驅動,製備深N-阱106。深N-阱106至少與周圍的N-阱環108部分重疊。這樣一來,P-阱107與P-型基底102絕緣。當P-阱107連接到類比接地,並且P-型基底102連接到數位接地時,N-阱環108和深N-阱106提供類比和數位接地接頭的絕緣。
圖7表示依據本發明的較佳實施例,利用緊湊CMOS元件絕緣結構的P-阱和N-阱俯視圖。參見圖7,在電路模組150中,製備有源N-阱環包圍P-阱,以使絕緣不可能。在那種情況下,在盡可能多的邊上,P-阱160可以有源N-阱158為邊界。在不是以有源N-阱158為邊界的P-阱160邊上,製備N-阱和深N-阱結構159。這樣一來,即使P-阱沒有被有源N-阱完全包圍,也可以實現P-阱160的絕緣。
在上述實施例中,積體電路形成在P-型基底上,CMOS元件絕緣用於P-阱。在其他實施例中,積體電路形成在N-型基底上,本發明所述的緊湊CMOS元件絕緣系統可用於使積體電路中的N-阱絕緣。
在上述實施例中,通過連接到模擬接地電勢的N-阱,使帶有P-阱的積體電路絕緣。在其他實施例中,通過N-阱絕緣的P-阱可以連接到其他電壓值,包括高於接地電勢的電壓,只要受保護的P-阱和周圍的N-阱、N-型掩埋層之間反向偏置即可。
雖然為了表述清楚,以上內容對實施例進行了詳細介紹,但是本發明並不局限於上述細節。實施本發明還有許多較佳方案。文中的實施例僅用於解釋說明,不用於局限。
1、2、3、4、60、80、100、150‧‧‧電路模組
106、159‧‧‧深N-阱
158‧‧‧有源N-阱
50‧‧‧積體電路
52、68、108‧‧‧N-阱
54、70、107、160‧‧‧P-阱
62、102‧‧‧P-型基底
63、83‧‧‧P-型外延層
64、84‧‧‧N-型掩埋層
71‧‧‧柵極電介質
72‧‧‧柵極電極
74‧‧‧N+區
76‧‧‧P+區
Vdd‧‧‧正電壓源電壓
106、159‧‧‧深N-阱
158‧‧‧有源N-阱
50‧‧‧積體電路
52、68、108‧‧‧N-阱
54、70、107、160‧‧‧P-阱
62、102‧‧‧P-型基底
63、83‧‧‧P-型外延層
64、84‧‧‧N-型掩埋層
71‧‧‧柵極電介質
72‧‧‧柵極電極
74‧‧‧N+區
76‧‧‧P+區
Vdd‧‧‧正電壓源電壓
圖1為含有傳統CMOS元件絕緣結構的傳統功率積體電路的俯視圖;
圖2為利用傳統的CMOS元件絕緣結構製備的電路模組的剖面圖;
圖3為依據本發明的實施例,配置緊湊CMOS元件絕緣結構的CMOS積體電路的俯視圖;
圖4為依據本發明的實施例,利用緊湊CMOS元件絕緣結構製成的積體電路剖面圖;
圖5為依據本發明的較佳實施例,利用緊湊CMOS元件絕緣結構製成的積體電路的電路模組剖面圖;
圖6為依據本發明的較佳實施例,利用緊湊CMOS元件絕緣結構製成的積體電路的電路模組剖面圖;
圖7為依據本發明的較佳實施例,使用緊湊CMOS元件絕緣結構的P-阱和N-阱佈局的俯視圖。
1、2、3、4‧‧‧電路模組
50‧‧‧積體電路
52‧‧‧N-阱
54‧‧‧P-阱
Claims (22)
- 一種具緊湊型互補式金氧半場效電晶體絕緣的積體電路,其包括: 一第一導電類型輕摻雜的半導體層; 一第一導電類型的第一阱,形成在該半導體層中,該第一阱罩住有源元件,並且連接到一第一阱電勢; 一第二導電類型的第二阱,形成在該半導體層中,包圍著該第一阱,該第二阱罩住有源元件,並且連接到一第二阱電勢;以及 一第二導電類型的掩埋層,形成在該第一阱下方,至少部分重疊包圍著該第一阱的該第二阱。
- 如申請專利範圍第1項所述的積體電路,其中,該掩埋層與該第二阱接觸。
- 如申請專利範圍第1項所述的積體電路,其中,該掩埋層形成在該第二阱周圍,但不與該第二阱接觸。
- 如申請專利範圍第1項所述的積體電路,其中,該掩埋層與整個該第二阱重疊。
- 如申請專利範圍第1項所述的積體電路,其中,該半導體層包括: 一第一導電類型的半導體基底;以及 一第一導電類型的外延層,形成在該半導體基底上,該掩埋層形成在該半導體基底上。
- 如申請專利範圍第1項所述的積體電路,其中,該第一阱罩住第二導電類型的互補式金氧半場效(MOS)電晶體,作為有源元件。
- 如申請專利範圍第1項所述的積體電路,其中,該第二阱罩住第一導電類型的互補式金氧半場效電晶體,作為有源元件。
- 如申請專利範圍第1項所述的積體電路,其中,第一導電類型為P-型,第二導電類型為N-型。
- 如申請專利範圍第8項所述的積體電路,其中,該第一阱的該第一阱電勢包括一第一接地電勢,該半導體層電連接到一第二接地電勢,通過該第二阱和該掩埋層,該第一接地電勢與該第二接地電勢絕緣。
- 如申請專利範圍第9項所述的積體電路,其中,該第二阱的該第二阱電勢包括一個正電壓源電壓。
- 一種用於製備積體電路的方法,其中,包括: 製備第一導電類型的一半導體層,並且輕摻雜; 在該半導體層中製備第一導電類型的一第一阱,該第一阱罩住有源元件,並且連接到一第一阱電勢; 在該半導體層中製備第二導電類型的一第二阱包圍著該第一阱,該第二阱罩住有源元件,並且連接到該第二阱電勢;並且 在該第一阱下方,製備第二導電類型的一掩埋層,並且部分重疊包圍著該第一阱的該第二阱。
- 如申請專利範圍第11項所述的方法,其中,所述製備第二導電類型的該掩埋層,包括: 製備第二導電類型的該掩埋層,與該第二阱接觸。
- 如申請專利範圍第11項所述的方法,其中,所述製備第二導電類型的該掩埋層包括: 製備第二導電類型的該掩埋層,在該第二阱附近,但不與該第二阱接觸。
- 如申請專利範圍第11項所述的方法,其中,所述製備第二導電類型的該掩埋層,包括: 製備第二導電類型的該掩埋層,重疊整個該第二阱。
- 如申請專利範圍第11項所述的方法,其中,所述製備第一導電類型的該半導體層並且輕摻雜,包括: 製備第一導電類型的一半導體基底;並且 在該半導體基底上,製備第一導電類型的一外延層,其中該掩埋層形成在該半導體基底上。
- 如申請專利範圍第11項所述的方法,其中,該第一阱罩住第二導電類型的互補式金氧半場效電晶體,作為有源區。
- 如申請專利範圍第11項所述的方法,其中,該第二阱罩住第一導電類型的互補式金氧半場效電晶體,作為有源區。
- 如申請專利範圍第11項所述的方法,其中,第一導電類型為P-型,第二導電類型為N-型。
- 如申請專利範圍第18項所述的方法,其中,該第一阱的該第一阱電勢包括一第一接地電勢,該半導體層電連接到一第二接地電勢,通過該第二阱和該掩埋層,該第一接地電勢與該第二接地電勢絕緣。
- 如申請專利範圍第19項所述的方法,其中,該第二阱的該第二阱電勢包括正電壓源電壓。
- 一種積體電路,其中,包括: 一第一導電類型的半導體層,並且輕摻雜; 一第一導電類型的第一阱,形成在該半導體層中,該第一阱罩住有源元件,並且連接到該第一阱電勢; 一第二導電類型的第二阱,形成在該半導體層中,包圍著該第一阱,該第二阱罩住有源元件,並且連接到該第二阱電勢;以及 一第二導電類型的第三阱,形成在該半導體層中,該第三阱含有該第一阱,並且至少部分重疊包圍著該第一阱的該第二阱。
- 如申請專利範圍第21項所述的積體電路,其中,該第三阱包括一個第二導電類型的深阱。
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