JP2006319231A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2006319231A JP2006319231A JP2005142232A JP2005142232A JP2006319231A JP 2006319231 A JP2006319231 A JP 2006319231A JP 2005142232 A JP2005142232 A JP 2005142232A JP 2005142232 A JP2005142232 A JP 2005142232A JP 2006319231 A JP2006319231 A JP 2006319231A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims description 64
- 239000012535 impurity Substances 0.000 claims description 50
- 210000000746 body region Anatomy 0.000 claims description 38
- 230000015556 catabolic process Effects 0.000 description 29
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/0873—Drain regions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
【解決手段】 半導体基板1と埋込酸化膜2と半導体層3とを備え、半導体層3は、ソース領域9、及びソース領域9の周囲に位置するドレイン領域5を持つMOSトランジスタが形成された島状半導体層3aと、ドレイン領域25、及びドレイン領域25の周囲に位置するソース領域29を持つMOSトランジスタが形成された島状半導体層3bと、島状半導体層3aを半導体層3の他の部分から絶縁分離する絶縁分離用トレンチ4と、島状半導体層3bを半導体層3の他の部分から絶縁分離する絶縁分離用トレンチ24と、電位が回路上の最低電位に固定されて各トランジスタ間の電気的干渉を防止するバッファ領域12とを有する。
【選択図】 図3
Description
2、102 埋込酸化膜
3、103 半導体層
3a、3b、103a、103b 島状半導体層
4、24、104、115、124 絶縁分離用トレンチ
5、25、105、125 ドレイン領域
6、26、106、126 ドレインコンタクト領域
6a、6b、106a、106b ドレイン電極
7、27、107、127 ゲート電極
8、28、108、128 ボディー領域
9、29、109、129 ソース領域
9a、9b、109a、109b ソース電極
10、30、110、130 ボディーコンタクト領域
11、31、111、131 LOCOS酸化膜
12、112、132 バッファ領域
13、113、133 バッファコンタクト領域
13a、113a、113b バッファ電極
114、134 接続手段
Claims (5)
- 半導体基板と、
前記半導体基板上に形成された埋込酸化膜と、
前記埋込酸化膜上に形成された半導体層とを備え、
前記半導体層は、第1ボディー領域と、前記第1ボディー領域内に位置する第1ソース領域と、前記第1ボディー領域の周囲に位置する第1ドレイン領域とを持つ第1導電型の第1MOSトランジスタが形成された第1島状半導体層と、
第2ドレイン領域と、前記第2ドレイン領域の周囲に位置する第2ボディー領域と、前記第2ボディー領域内に位置する第2ソース領域とを持つ第2導電型の第2MOSトランジスタが形成された第2島状半導体層と、
前記第1島状半導体層の周囲に位置し、前記第1島状半導体層を前記半導体層の他の部分から絶縁分離する第1絶縁分離用トレンチと、
前記第2島状半導体層の周囲に位置し、前記第2島状半導体層を前記半導体層の他の部分から絶縁分離する第2絶縁分離用トレンチと、
前記第1絶縁分離用トレンチと前記第2絶縁分離用トレンチとの間に位置し、前記第1MOSトランジスタと前記第2MOSトランジスタとの間の電気的干渉を防止するバッファ領域とを有し、
前記バッファ領域の電位は、回路上の最低電位あるいは最高電位の何れか一方に固定されることを特徴とする半導体装置。 - 前記第1MOSトランジスタは、PチャネルMOSトランジスタであり、
前記第2MOSトランジスタは、NチャネルMOSトランジスタであり、
前記バッファ領域の電位は、回路上の最低電位に固定される
ことを特徴とする請求項1に記載の半導体装置。 - 前記第1MOSトランジスタは、NチャネルMOSトランジスタであり、
前記第2MOSトランジスタは、PチャネルMOSトランジスタであり、
前記バッファ領域の電位は、回路上の最高電位に固定される
ことを特徴とする請求項1に記載の半導体装置。 - 前記半導体層は、前記第1ドレイン領域と前記第1絶縁分離用トレンチとの間に該第1ドレイン領域よりも低不純物濃度であるドレインバッファ領域をさらに有している
ことを特徴する請求項1に記載の半導体装置。 - 前記半導体層において、前記第1ドレイン領域は前記第1絶縁分離用トレンチに接している
ことを特徴する請求項1に記載の半導体装置。
Priority Applications (2)
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JP2005142232A JP4864344B2 (ja) | 2005-05-16 | 2005-05-16 | 半導体装置 |
US11/370,038 US7342283B2 (en) | 2005-05-16 | 2006-03-08 | Semiconductor device |
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JP2005142232A JP4864344B2 (ja) | 2005-05-16 | 2005-05-16 | 半導体装置 |
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Publication Number | Publication Date |
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JP2006319231A true JP2006319231A (ja) | 2006-11-24 |
JP4864344B2 JP4864344B2 (ja) | 2012-02-01 |
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JP2005142232A Active JP4864344B2 (ja) | 2005-05-16 | 2005-05-16 | 半導体装置 |
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JP (1) | JP4864344B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009260208A (ja) * | 2008-03-26 | 2009-11-05 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008131730A (ja) * | 2006-11-20 | 2008-06-05 | Matsushita Electric Ind Co Ltd | 半導体装置、モータ駆動装置、及び空調機 |
DE102007029756A1 (de) * | 2007-06-27 | 2009-01-02 | X-Fab Semiconductor Foundries Ag | Halbleiterstruktur zur Herstellung eines Trägerwaferkontaktes in grabenisolierten SOI-Scheiben |
JP5410012B2 (ja) * | 2007-09-28 | 2014-02-05 | ローム株式会社 | 半導体装置 |
US20090218627A1 (en) * | 2008-02-28 | 2009-09-03 | International Business Machines Corporation | Field effect device structure including self-aligned spacer shaped contact |
EP2951865B1 (en) * | 2013-01-30 | 2020-03-25 | Microchip Technology Incorporated | Semiconductor device with esd self-protection and lin bus driver comprising the same |
JP6740831B2 (ja) * | 2016-09-14 | 2020-08-19 | 富士電機株式会社 | 半導体装置 |
CN110024134B (zh) | 2019-02-28 | 2020-06-26 | 长江存储科技有限责任公司 | 具有增大的击穿电压的高电压半导体器件及其制造方法 |
Citations (7)
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---|---|---|---|---|
JPH05136436A (ja) * | 1991-01-31 | 1993-06-01 | Toshiba Corp | 高耐圧半導体素子 |
JPH11274501A (ja) * | 1998-03-20 | 1999-10-08 | Denso Corp | 半導体装置 |
JPH11312805A (ja) * | 1998-04-30 | 1999-11-09 | Denso Corp | 半導体装置 |
JPH11330383A (ja) * | 1998-05-20 | 1999-11-30 | Denso Corp | 半導体装置 |
JP2001308338A (ja) * | 2000-04-26 | 2001-11-02 | Hitachi Ltd | 絶縁ゲート電界効果トランジスタ及び半導体集積回路 |
JP2001345376A (ja) * | 2000-06-01 | 2001-12-14 | Unisia Jecs Corp | 半導体装置 |
JP2002124681A (ja) * | 2000-10-18 | 2002-04-26 | Mitsubishi Electric Corp | 半導体装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7224025B2 (en) * | 2004-08-03 | 2007-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolated LDMOS IC technology |
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- 2005-05-16 JP JP2005142232A patent/JP4864344B2/ja active Active
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2006
- 2006-03-08 US US11/370,038 patent/US7342283B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05136436A (ja) * | 1991-01-31 | 1993-06-01 | Toshiba Corp | 高耐圧半導体素子 |
JPH11274501A (ja) * | 1998-03-20 | 1999-10-08 | Denso Corp | 半導体装置 |
JPH11312805A (ja) * | 1998-04-30 | 1999-11-09 | Denso Corp | 半導体装置 |
JPH11330383A (ja) * | 1998-05-20 | 1999-11-30 | Denso Corp | 半導体装置 |
JP2001308338A (ja) * | 2000-04-26 | 2001-11-02 | Hitachi Ltd | 絶縁ゲート電界効果トランジスタ及び半導体集積回路 |
JP2001345376A (ja) * | 2000-06-01 | 2001-12-14 | Unisia Jecs Corp | 半導体装置 |
JP2002124681A (ja) * | 2000-10-18 | 2002-04-26 | Mitsubishi Electric Corp | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009260208A (ja) * | 2008-03-26 | 2009-11-05 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
US8502344B2 (en) | 2008-03-26 | 2013-08-06 | Fuji Electric Co., Ltd. | Semiconductor device |
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US20060255406A1 (en) | 2006-11-16 |
US7342283B2 (en) | 2008-03-11 |
JP4864344B2 (ja) | 2012-02-01 |
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