TWI570839B - 用於cmos積體電路的緊密保護環結構 - Google Patents
用於cmos積體電路的緊密保護環結構 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 description 14
- 210000001503 joint Anatomy 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000002547 anomalous effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
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Description
本發明主要關於半導體元件。具體地說,本發明是指一種用於CMOS(Complementary Metal Oxide Semiconductor,互補金屬氧化物半導體)積體電路的緊密保護環結構。
單片積體電路(IC)含有多個在半導體基材上製備的主動元件。還會形成反常的寄生元件,導致元件之間發生不必要的串擾。形成在P-基材上的CMOS積體電路通常包括一寄生NPN電晶體,由P-基材製成,一N-阱和另一N區。當寄生NPN電晶體觸發形成PNPN結構時,會發生積體電路的閉鎖。
對於引入高壓開關元件和額定電壓控制器電路的功率積體電路來說,閉鎖是一個非常嚴重的問題。功率積體電路上的功率元件開關時產生的瞬態電壓,會終止寄生NPN電晶體的發射極和基極接面的正向偏置,導致少數載流子注入基材。偏置或非偏置的保護環結構,已用於在積體電路中引入寄生電流的元件或電路絕緣。利用保護環結構,收集注入到基材中的不必要的少數載流子。例如,通常使用保護環,包圍橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor,LDMOS)電晶體,收集少數載流子,防止閉鎖。
傳統的保護環結構通常佔用很大的空間,需要配置很大的矽面積。圖1表示一種包圍著主動元件的傳統的雙保護環結構。圖2表示沿線A-A’,圖1所示的傳統雙保護環結構的剖面圖。參見圖1和圖2,積體電路10形成在P-基材12上,P-型外延層14形成在P-基材12上。傳統的保護環結構16通常包括由深N-阱20構成的N-型保護環,被P-型保護環包圍在全部邊上,P-型保護環由P-阱24構成。N-阱18可以形成在深N-阱20中。保護環結構16包圍著要保護的主動元件22。例如,主動元件可以是形成在N-型掩埋層26的N-型LDMOS電晶體。保護環結構16的N-型保護環收集藉由LDMOS電晶體元件22注入到P-基材12中的少數載流子(電子)。當注入的電子重新複合時,保護環結構16的P-型保護環還在少數載流子(空穴)被N-阱20收集之前,收集產生的少數載流子。
如圖1所示,當要保護的主動元件形成在積體電路的邊上時,保護環可以呈U形,包圍主動元件22向內的對邊。N-型保護環(N-阱18/深N-阱20)可以是浮動的或連接到任意接地電勢,或者連接到正電壓源Vdd。N+擴散區30形成在N-阱/深N-阱中,以便與重疊接頭(圖中沒有表示出)形成歐姆接觸,以降低阱的電阻。P-型保護環(P-阱24)通常接地,利用P+擴散區,與重疊接頭(圖中沒有表示出)形成歐姆接觸,重疊接頭也稱為P-接頭。在一些情況下,靠近主動元件的P-型保護環的P-阱,可以是浮動的,而在N-型保護環另一邊上的P-型保護環的P-阱可以接地。因此,寄生NPN雙極電晶體由N-型保護環構成,作為集電極,P-基材12作為基極,主動元件22中的N-型掩埋層作為發射極。
傳統的保護環結構佔用大量空間,增大了晶片尺寸和積體電路的成本。尤其是P-阱24的P-型掩埋層(PBL)28和N-型保護環的N-型掩埋層(NBL)26之間所需的最小間距,增加了配置保護環結構所
需的矽面積。
本發明的目標旨在改善習知技術中的一個或多個問題,因此提出以下有效的可選方案。
本發明提供一種積體電路,包括:第一導電類型輕摻雜的一半導體層;形成在半導體層中的一主動元件,該主動元件至少部分形成在第二導電類型的第一掩埋層上;第一導電類型的一第一保護環,形成在半導體層中,至少包圍著主動元件的一部分;第二導電類型的一第二保護環,形成在半導體層中,包圍著第一保護環,該第二保護環包括第一導電類型的第一阱區,與第二導電類型的第二阱區交替排列,第一阱區和第二阱區形成在第二導電類型的第二掩埋層上,第一阱區和第二阱區相互短接,並且電耦合到地電壓或浮動;第一導電類型的一第三保護環,形成在半導體層中,包圍著第二保護環;其中第一和第三保護環不接受直連,並且偏置到與第二保護環中的第二導電類型的第二阱區相同的電勢。
較佳地,第一保護環、第二保護環和第三保護環構成同心閉環,包圍著主動元件。
較佳地,第一保護環、第二保護環和第三保護環構成同心開環,包圍著至少一部分主動元件。
較佳地,第一保護環和第三保護環都含有第一導電類型的一阱區,形成在第一導電類型的第三掩埋層上,以及第一導電類型的一重摻雜區,形成在阱區中。
較佳地,每個第二保護環的第二阱區更包括第二導電類型的一深阱區,延伸到第二掩埋層,以及第二導電類型的一重摻雜區,形成在深阱區中。
較佳地,每個第二保護環的第二阱區更包括第二導電類型的一標準阱區,形成在深阱區中;第二導電類型的重摻雜區形成在標準阱區中。
較佳地,每個第二保護環的第一阱區都包括第一導電類型的一重摻雜區,形成在第一阱區中。
較佳地,第二保護環包括與第一阱區的重摻雜區和第二阱區重摻雜區電接觸的接頭,及電連接第二保護環中接頭的導電層。
較佳地,接頭包括對接接頭,每個對接接頭都與一對相鄰的第一阱區和第二阱區電連接。
較佳地,第一導電類型為P-型,第二導電類型為N-型。
本發明更提供一種用於製備積體電路的方法,包括下列步驟:製備第一導電類型的一半導體層,並且輕摻雜;在半導體層中製備一主動元件,該主動元件至少部分形成在第二導電類型的第一掩埋層上;在半導體層中製備第一導電類型的一第一保護環,至少包圍著主動元件的一部分;在半導體層中製備第二導電類型的一第二保護環,包圍著第一保護環,該第二保護環包括第一導電類型的第一阱區與第二導電類型的第二阱區交替排列,第一阱區和第二阱區形成在第二導電類型第二掩埋層上,第一阱區和第二阱區短接在一起,並且電耦合至地電壓或浮動;在半導體層中製備第一導電類型的一第三保護環,包圍著第二保護環;其中第一和第三保護環不接受直連,並且偏置到第二保護環中的第二導電類型的第二阱區相同的電勢。
較佳地,製備第一保護環、第二保護環和第三保護環,包括下列步驟:製備第一保護環、第二保護環和第三保護環,作為同心閉環,包圍著主動元件。
較佳地,製備第一保護環、第二保護環和第三保護環,包括下列步驟:製備第一保護環、第二保護環和第三保護環,作為同心開環,至少包圍著主動元件的一部分。
較佳地,製備第一保護環和第三保護環,包括下列步驟:在第一導電類型的第三掩埋層上,製備第一導電類型的阱區;並且在第一導電類型的阱區中製備第一導電類型的重摻雜區。
較佳地,製備第二保護環,包括下列步驟:製備第二導電類型的一深阱區,作為第二阱區,該深阱區延伸到第二掩埋層;並且在深阱區中,製備第二導電類型的一重摻雜區。
較佳地,製備第二保護環,更包括下列步驟:在深阱區中,製備第二導電類型的一標準阱區,第二導電類型的重摻雜區形成在標準阱區中。
較佳地,製備第二保護環,更包括下列步驟:在第二保護環的每個第一阱區中,製備第一導電類型的一重摻雜區。
較佳地,製備第二保護環,更包括下列步驟:製備與第一阱區和第二阱區的重摻雜區電接觸的接頭;並且製備一導電層,電連接第二保護環中的接頭。
較佳地,製備與第一阱區和第二阱區的重摻雜區電接觸的接頭,包括:製備對接接頭,每個對接接頭都與一對相鄰的第一阱區和第二阱區電連接。
較佳地,第一導電類型為P-型,第二導電類型為N-型。
閱讀以下說明並參照圖式之後,本發明的其他目標和優勢將更加顯而易見,說明及圖式並不用於侷限本發明的範圍。
10‧‧‧積體電路
110‧‧‧積體電路
116‧‧‧緊密保護環結構
12‧‧‧P-基材
120‧‧‧深N-阱
124‧‧‧P-阱
124A‧‧‧P-阱
124B‧‧‧P-阱
130‧‧‧N+區
132‧‧‧P+區
134‧‧‧對接接頭
14‧‧‧P-型外延層
156‧‧‧緊密保護環結構
16‧‧‧保護環結構
160‧‧‧深N-阱
162‧‧‧主動元件
164‧‧‧P-阱
164A‧‧‧P-阱
164B‧‧‧P-阱
18‧‧‧N-阱
20‧‧‧深N-阱
22‧‧‧主動元件
24‧‧‧P-阱
26‧‧‧N-型掩埋層
28‧‧‧P-型掩埋層
30‧‧‧N+擴散區
50‧‧‧積體電路
52‧‧‧P-基材
54‧‧‧P-型外延層
56‧‧‧緊密保護環結構
58‧‧‧N-阱
60‧‧‧深N-阱
62‧‧‧主動元件
64‧‧‧P-阱
64A‧‧‧P-阱
64B‧‧‧P-阱
66‧‧‧N-型掩埋層
68‧‧‧P-型掩埋層
70‧‧‧重摻雜N+區
72‧‧‧重摻雜P+擴散區
74‧‧‧接頭
圖1表示包圍著主動元件的傳統雙保護環結構;圖2表示圖1中沿線A-A’所示的傳統雙保護環結構的剖面圖;圖3表示在本發明的實施例中,積體電路中的緊密保護環結構的俯視圖;圖4表示圖3中沿線B-B’所示的緊密保護環結構的剖面圖;圖5表示在本發明的可選實施例中,積體電路中的緊密保護環結構的俯視圖;圖6表示在本發明的可選實施例中,積體電路中的接觸保護環結構的俯視圖。
以下結合圖式,藉由詳細說明較佳的具體實施例,對本發明做進一步闡述。
本發明可以以各種方式實現,包括作為一個製程;一種裝置;一個系統;或一種物質合成物。在本發明說明書中,這些實現方式或本發明可能採用的任意一種其他方式,都可以稱為技術。一般來說,可以在本發明的範圍內變換所述技術步驟的順序。
本發明的一個或多個實施例的詳細說明以及圖式解釋了本發明的原理。雖然,本發明與這些實施例一起提出,但是本發明的範圍並不侷限於任何實施例。本發明的範圍僅由申請專利範圍限定,本發明包含多種可選方案、修正以及等效方案。在以下說明中,所提出的各種具體細節用於全面理解本發明。這些細節用於解釋說明,無需這些詳細細節中的部分細節或全部細節,依據申請專利範圍,就可以實現本發明。為了條理清晰,本發明相關技術領域中眾所周知的技術材料並沒有詳細說明,以免對本發明產生不必要的混淆。
在本發明的實施例中,用於CMOS積體電路的緊密保護環結構含有積體P-阱接頭的N-型保護環,以減小保護環結構所需的矽面積。在部分實施例中,緊密保護環結構包括被內、外P-型保護環包圍的N-型保護環。N-型保護環由交替的深N-阱和P-阱構成,深N-阱和P-阱形成在N-型掩埋層上並且同時短路。內、外P-型保護環形成在P-阱中。N-型保護環的交替深N-阱和P-阱可以接地或保持浮動。藉由在N-型保護環中積體P-阱接頭,可以省去用於P-型保護環的P-阱接頭或P-接頭,從而減小配置保護環結構所需的矽面積。用於配置引入緊密保護環結構的積體電路的晶片尺寸,也可以減小。
在本發明的實施例中,利用緊密保護環結構,包圍主動元件,主動元件可以至少部分在N-型掩埋層上方。緊密保護環結構可以形成在一閉環中,包圍著要保護的主動元件。還可選擇,當要保護的主動元件形成在積體電路邊上時,緊密保護環結構可以作為一開環,例如呈C形或U形,以包圍主動元件的向內對邊。
圖3表示在本發明的實施例中,積體電路中的緊密保護環結構的俯視圖。圖4表示圖3中沿線B-B’所示的緊密保護環結構的剖
面圖。參閱圖3和圖4,積體電路50形成在P-基材52上,P-型外延層54形成在P-基材52上。緊密保護環結構56形成在積體電路50上,以保護積體電路上的其他敏感元件注入主動元件62。主動元件至少部分形成在N-型掩埋層上方。在本實施例中,主動元件62形成在積體電路50的邊緣。因此,如圖3所示,緊密保護環結構56作為一開環,呈U形,保護主動元件62的向內對邊。在其他實施例中,緊密保護環結構可以形成在閉環中,以包圍在所有邊上的要保護的主動元件,這將在下文詳細介紹。
緊密保護環結構56包括一N-型保護環,N-型保護環被內部P-型保護環和外部P-型保護環包圍。外部P-型保護環形成在P-型掩埋層68上的P-阱64A中。內部P-型保護環形成在P-型掩埋層上的P-阱64B中。重摻雜P+擴散區72形成在P-阱64A和P-阱64B,以降低P-阱的電阻。
在本發明的實施例中,N-型保護環由交替的深N-阱60和P-阱64形成,深N-阱60和P-阱64都形成在N-型掩埋層66上。更確切地說,N-型保護環由交替的深N-阱60和P-阱64形成,使得每個深N-阱60都鄰近P-阱64。在部分實施例中,N-阱58形成在每個深N-阱60內。在本發明說明中,深N-阱60有時稱為高壓N-阱,是指N-阱形成在半導體本體的表面以下比標準N-阱58更深的地方,並且比標準N-阱58的重摻雜程度更高。深N-阱通常延伸到阱下方的N-掩埋層。深N-阱60用於高壓元件,以維持較高的擊穿電壓。重摻雜N+區70形成在每個N-阱58中,以提供到N-阱的歐姆接觸。重摻雜P+擴散區72形成在P-阱64中,以提供到P-阱64的歐姆接觸。
在本實施例中,P-阱形成在P-型外延層中,可以與N-阱
分隔開。在其他實施例中,P-阱可以作為全面P-阱,形成在沒有N-阱的任何地方。在那種情況下,P-阱64A和P-阱64B鄰近深N-阱60或N-型保護環的P-阱64。
在本發明的實施例中,構成N-型保護環的深N-阱60和P-阱64,相互短接,並且可以電連接到接地電勢,或者保持浮動。例如,接頭74可以形成在P-阱64的重摻雜N+區70和重摻雜P+擴散區72。可以使用導電層(圖中沒有表示出),例如金屬層,電連接N-型保護環中的接頭74。在部分實施例中,N-型保護環電阻短接至接地電勢。
這樣使得藉由接頭74,只能直連到N-型保護環。內部和外部P-型保護環(P-阱64A和P-阱64B)不包括任何接頭或P-接頭,並且不會接收任何直接電聯。更確切地說,P-阱64A和P-阱64B不會直連到任意電勢,而是保持浮動。然而,P-阱64A、P-阱64B藉由其鄰近N-型保護環中的P-阱區,偏置到與P-阱64A相同的電勢。例如,P-阱64A藉由P-型外延層54,電阻短接至P-阱64。更可選擇,P-阱64A在某些位置鄰近P-阱64,並且藉由物理接頭,短接至P-阱64。
本發明所述之緊密保護環結構56的顯著特點是,緊密保護環結構56結合了在N-型保護環中的P-阱接頭,消除了在P-型保護環中提供單獨的P-接頭的必要性。藉由省去到P-型保護環的P-阱接頭或P-接頭(P-阱64A和P-阱64B),減小了用於配置緊密保護環結構56的矽面積,實現了緊密保護環結構。
緊密保護環結構56的另一個特點是,N-型保護環的深N-阱電連接到與P-阱64和P-阱64A相同的電勢。也就是說,整個緊密保護環結構56接地或保持浮動。N-型保護環的深N-阱60從不連接到正電壓源電壓Vdd,使保護環結構中的N-型區和P-型區之間的間距最小。因
此,P-基材52中的少數載流子(電子)可以由N-型保護環的深N-阱60收集,作為寄生NPN雙極電晶體的集電極。當深N-阱60接地或保持浮動時,電子將轉移至地電壓。更確切地說,由深N-阱60收集的電子,藉由電阻接地的鄰近P阱區,轉換成空穴,然後在接地處收集空穴。
在本發明的實施例中,所形成的深N-阱60和P-阱64可以相互分隔開,或者相互佈滿或鄰近。此外,在圖3所示的實施例中,每個深N-阱60和每個P-阱64都含有一接頭,形成到N和P型區的電連接。在其他實施例中,當深N-阱60和P-阱64相互佈滿或鄰近時,可以使用對接接頭,電連接交替的深N-阱和P-阱,如圖5所示。圖5表示在本發明的可選實施例中,積體電路中的緊密保護環結構的俯視圖。參閱圖5,形成在積體電路110上的緊密保護環結構116,包括由N-型掩埋層上的交替深N-阱120和P-阱124構成的N-型保護環。利用對接接頭134,將深N-阱120和P-阱124電短接在一起。更確切地說,在一對鄰近的深N-阱120和P-阱124中,形成在深N-阱120中的N+區130和形成在P-阱124中的P+區132相互鄰近並對接,製備單獨的對接接頭134,連接N+區和P+區。N-型保護環被P-型保護環包圍,P-型保護環由P-型掩埋層上的P-阱124A製成,P+區132形成在P-阱124A中。外部P-阱124A或內部P-阱124B無需阱接頭或P-接頭。P+區132形成在外部P-阱124和內部P-阱124B中,以降低由表面閾值電壓增大導致的表面洩露。
圖6表示在本發明的實施例中,積體電路中的緊密保護環結構的俯視圖。圖6表示本發明所述的緊密保護環結構156形成在一閉環結構中,以包圍整個主動元件162。本發明所述的緊密保護環結構156可以作為內部P-型保護環(P-阱164B)的同心環,包圍主動元件162、N-型保護環以及外部P-型保護環(P-阱164A)。N-型保護環由形成在
N-型掩埋層上的交替深N-阱160和P-阱164構成。深N-阱160和P-阱164電連接在一起,可以浮動或接地。N+區形成在包括N-阱的深N-阱160中。內部和外部P-型保護環形成在P-型外延層上的P-阱164A和P-阱164B中。P+區形成在P-阱164、164A、164B中。單獨的接頭(圖中沒有表示出)或對接接頭(圖中沒有表示出)還可以用於連接N-型保護環中的深N-阱和P-阱164。
因此,N-型保護環結合P-阱接頭,使得內部和外部P-型保護環(P-阱164A和P-阱164B)無需包括P-阱接頭。在這種情況下,可以利用很小的矽面積,實現緊密保護環結構156。必須注意的是,圖3所示的緊密保護環結構56和圖5所示的緊密保護環結構116,僅僅是圖6所示的緊密保護環結構156的一部分。當主動元件162形成在積體電路邊緣時,保護環結構成為緊密保護環結構156的一部分。在本實施例中,保護環假設呈圓形或多邊形(例如正方形)。使用「環」一詞不是只將保護環限定為圓形。
另外,在本發明的實施例中,可以使用多行接頭,製備N-型保護環。例如,在圖3和圖5中,表示的是單獨的一行接頭。在其他實施例中,圖3、圖5和圖6所示的保護環結構可以含有兩行或多行接頭或對接接頭,以增強深N-阱和P-阱之間的電接觸。
雖然為了表述清楚,以上內容對實施例進行了詳細介紹,但是本發明並不侷限於上述細節。實施本發明還有許多可選方案。文中的實施例僅用於解釋說明,不用於侷限。
50‧‧‧積體電路
56‧‧‧緊密保護環結構
60‧‧‧深N-阱
62‧‧‧主動元件
64‧‧‧P-阱
64A‧‧‧P-阱
64B‧‧‧P-阱
70‧‧‧重摻雜N+區
72‧‧‧重摻雜P+擴散區
74‧‧‧接頭
Claims (20)
- 一種積體電路,其包括:一第一導電類型輕摻雜的一半導體層;形成在該半導體層中的一主動元件,該主動元件至少部分形成在一第二導電類型的第一掩埋層上;該第一導電類型的一第一保護環,形成在該半導體層中,至少包圍著該主動元件的一部分;該第二導電類型的一第二保護環,形成在半導體層中,包圍著該第一保護環和該主動元件,該第二保護環包括該第一導電類型的一第一阱區,與該第二導電類型的一第二阱區交替排列,該第一阱區和該第二阱區形成在該第二導電類型的一第二掩埋層上,該第一阱區和該第二阱區相互短接,並且電耦合到地電壓或浮動;該第一導電類型的一第三保護環,形成在該半導體層中,包圍著該第二保護環;其中該第一保護環和該第三保護環不接受直連,並且偏置到與該第二保護環中的該第二導電類型的該第二阱區相同的電勢。
- 如申請專利範圍第1項所述之積體電路,其中該第一保護環、該第二保護環和該第三保護環構成同心閉環,包圍著該主動元件。
- 如申請專利範圍第1項所述之積體電路,其中該第一保護環、該第二保護環和該第三保護環構成同心開環,包圍著至少一部分該主動元件。
- 如申請專利範圍第1項所述之積體電路,其中該第一保護環和該第三保護環都含有該第一導電類型的一阱區,形成在該第一導電類型的一第三掩埋層上,以及該第一導電類型的一重摻雜區,形成在該阱區中。
- 如申請專利範圍第1項所述之積體電路,其中每個該第二保護環的該第二阱區,更包括該第二導電類型的一深阱區,延伸到該第二掩埋層,以及該第二導電類型的一重摻雜區,形成在該深阱區中。
- 如申請專利範圍第5項所述之積體電路,其中每個該第二保護環的該第二阱區,更包括該第二導電類型的一標準阱區,形成在該深阱區中;該第二導電類型的該重摻雜區形成在該標準阱區中。
- 如申請專利範圍第5項所述之積體電路,其中每個該第二保護環的該第一阱區,都包括該第一導電類型的一重摻雜區,形成在該第一阱區中。
- 如申請專利範圍第7項所述之積體電路,其中該第二保護環包括與該第一阱區的該重摻雜區和該第二阱區的該重摻雜區電接觸的一接頭,及電連接該第二保護環中該接頭的一導電層。
- 如申請專利範圍第8項所述之積體電路,其中該接頭包括一對接接頭,每個該對接接頭都與一對相鄰的該第一阱區和該第二阱區電連接。
- 如申請專利範圍第1項所述之積體電路,其中該第一導電類型為P-型,該第二導電類型為N-型。
- 一種用於製備積體電路的方法,其包括下列步驟:製備一第一導電類型的一半導體層,並且輕摻雜;在該半導體層中製備一主動元件,該主動元件至少部分形成在一第二導電類型的一第一掩埋層上;在該半導體層中製備該第一導電類型的一第一保護環,至少包圍著該主動元件的一部分;在該半導體層中製備該第二導電類型的一第二保護環,包圍著該第一保護環和該主動元件,該第二保護環包括該第一導電類型的一第一阱區與該第二導電類型的一第二阱區交替排列,該第一阱區和該第二阱區形成在該第二導電類型的一第二掩埋層上,該第一阱區和該第二阱區短接在一起,並且電耦合至地電壓或浮動;在該半導體層中製備該第一導電類型的一第三保護環,包圍著該第二保護環;其中該第一保護環和該第三保護環不接受直連,並且偏置到該第二保護環中的該第二導電類型的該第二阱區相同的電勢。
- 如申請專利範圍第11項所述之方法,其中製備該第一保護環、該第二保護環和該第三保護環之步驟,包括:製備該第一保護環、該第二保護環和該第三保護環,作為同心閉環,包圍著該主動元件。
- 如申請專利範圍第11項所述之方法,其中製備該第一保護環、該第二保護環和該第三保護環之步驟,包括:製備該第一保護環、該第二保護環和該第三保護環,作為同心開環,至少包圍著該主動元件的一部分。
- 如申請專利範圍第11項所述之方法,其中製備該第一保護環和該第三保護環之步驟,包括:在該第一導電類型的一第三掩埋層上,製備該第一導電類型的一阱區;並且在該第一導電類型的該阱區中製備該第一導電類型的一重摻雜區。
- 如申請專利範圍第11項所述之方法,其中製備該第二保護環之步驟,包括:製備該第二導電類型的一深阱區,作為該第二阱區,該深阱區延伸到該第二掩埋層;並且在該深阱區中,製備該第二導電類型的一重摻雜區。
- 如申請專利範圍第15項所述之方法,其中製備該第二保護環之步驟,更包括:在該深阱區中,製備該第二導電類型的一標準阱區,該第二導電類型的該重摻雜區形成在該標準阱區中。
- 如申請專利範圍第15項所述之方法,其中製備該第二保護環之步驟,更包括:在該第二保護環的每個該第一阱區中,製備該第一導電類型的一重摻雜區。
- 如申請專利範圍第17項所述之方法,其中製備該第二保護環之步驟,更包括:製備與該第一阱區和該第二阱區的該重摻雜區電接觸的一接頭;並且製備一導電層,電連接該第二保護環中的該接頭。
- 如申請專利範圍第18項所述之方法,其中製備與該第一阱區和該第二阱區的重摻雜區電接觸的該接頭之步驟,包括:製備一對接接頭,每個該對接接頭都與一對相鄰的該第一阱區和該第二阱區電連接。
- 如申請專利範圍第11項所述之方法,其中該第一導電類型為P-型,該第二導電類型為N-型。
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