200917921 九、發明說明 【發明所屬之技術領域】 本發明’係有關於經由電鍍而在基板上形成細微之配 線以及層間連接孔（通孔）的技術。 【先前技術】 由於電子機器之小型化，在覆晶薄膜（COF )或是半 導體封裝基板等之上’亦強烈地要求有將銅配線之配線節 距設爲20 μιη以下之細微化要求。伴隨著細微化，配線之 形成或是配線間之遷移（m i g r a t i ο η )耐性的確保亦成爲困 難。 近年來，作爲在基板上形成細微之配線以及層間連接 孔（通孔）的方法，係使用有電鍍法。電鍍法，相較於物 理氣相成長（PVD )法、或是化學氣相成長（CVD )法， 係具備有成本低，生產率高，量產性優良等之優點。在經 由電鍍而在基板上形成配線以及層間連接孔之方法，係週 知有各種之方法，而其中之一，係爲金屬鑲嵌法。在金屬 鑲嵌法中，係在基板上，經由適當之方法，而形成溝以及 凹部。溝，係被形成爲對應於配線圖案之形狀，而凹部’ 係被形成在應配置通孔之位置。接下來，經由電鍍’而在 基板之表面處使金屬析出。經由此析出金屬，溝以及凹部 係被塡埋。如此這般，經由被埋入至溝以及凹部中之析出 金屬，而形成配線以及層間連接孔。 [專利文獻1]日本特開2006-2 1 0565號公報 200917921 [專利文獻2]日本特開2006-2069 5 0號公報 [專利文獻3]日本特開2002 - 1 5 5 3 90號公報 【發明內容】 [發明所欲解決之課題] 在金屬鑲嵌法中，係經由以電鍍所析出之金屬，而在 基板上形成配線又或是通孔。然而，經由電鍍所析出之金 屬，不僅會覆蓋基板上之溝以及凹部，而亦會覆蓋溝以及 凹部以外之部分。故而，在進行了電鍍後，係有必要進行 將不必要之金屬層除去之工程。此作業，係爲繁雜。又， 將此金屬層正確地除去一事，係爲困難。 本發明之目的，係在經由電鍍而在基板上形成配線又 或是層間連接孔時，能夠減輕將不必要之金屬層除去的作 業。 [用以解決課題之手段] 若藉由本發明，則係在使用於電鍍中之電鍍液處，添 加添加劑。添加劑，係具備有抑制電鍍反應之功能，並具 備有隨著電鍍反應之進行而使抑制電鍍反應之功能減少的 特性。藉由此，能夠在被形成於基板上之溝以及凹部處來 將金屬選擇性的析出。 若藉由本發明，則在電鍍中所使用之電鍍液，其分極 曲線，係當電位爲存在於第1電位E1與第2電位E2之 間的情況時，當旋轉數爲1 OOOrpm時，若是將電位朝向更 200917921 爲負方向而橫移，則電流密度係急遽地增加。而當電位爲 存在於第1電位E1與第2電位E2之間的情況時，旋轉 數爲1000rpm時之分極曲線，係與旋轉數爲〇時之分極曲 線交叉。 若藉由本發明，則在經由金屬鑲嵌法而在基板上形成 配線又或是層間連接孔時，係在基板上形成具備有特定之 表面粗度的溝以及凹部。 [發明之效果] 本發明之目的，則在經由電鍍而在基板上形成配線又 或是通孔時，能夠減輕將不必要之金屬層除去的作業。 【實施方式】 首先，對本發明之槪要作說明。若藉由本發明，則係 在使用於電鍍中之電鍍液處，添加添加劑。在電鍍液中， 係可使用酸性硫酸銅溶液。被使用於電鍍中之酸性硫酸銅 溶液，係爲既知，故於此並不作詳細說明。另外，若是使 用酸性硫酸銅溶液，則配線以及通孔係藉由銅而形成。配 線以及通孔，係亦可藉由銅以外之金屬來形成。例如，亦 可使用鎳、鋁等。於此情況，作爲電鍍液，係使用成爲配 線以及通孔之原料的金屬之溶液。在身爲電鍍之基底的導 電層處所使用之金屬，雖然亦可爲銅，但是，係使用銅以 外之金屬，例如，使用鎳、鈷、鉻、鎢、鈀、鈦：又或是 包含有此些之金屬的至少一個之合金。 -7- 200917921 若藉由本發明，則添加劑係具備有抑制電鍍反應之功 能，但是亦具備有隨著電鍍反應之進行而使抑制電鍍反應 之功能減少的特性。添加劑，若是具備有此種功能以及特 性，則可爲任何之物質。本案之發明者，係發現了 ：花青 (Cyanine )色素以及其之衍生物，係具備有此種功能以 及特性。花青色素，係藉由下式來作表示。但是，η係爲 0、1、2、2之其中一者。 [化學式1]BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique of forming fine wiring lines and interlayer connection holes (through holes) on a substrate by electroplating. [Prior Art] Due to the miniaturization of electronic equipment, it is strongly required to have a wiring pitch of copper wiring of 20 μm or less or less on a flip chip (COF) or a semiconductor package substrate. With the miniaturization, it is also difficult to ensure the formation of wiring or the migration of wiring (m i g r a t i ο η). In recent years, as a method of forming fine wiring and interlayer connection holes (through holes) on a substrate, an electroplating method has been used. The electroplating method has advantages such as low cost, high productivity, and excellent mass productivity as compared with the physical vapor phase growth (PVD) method or the chemical vapor phase growth (CVD) method. In the method of forming wiring and interlayer connection holes on a substrate by electroplating, various methods are known, and one of them is a damascene method. In the damascene method, grooves and recesses are formed on a substrate by an appropriate method. The groove is formed to correspond to the shape of the wiring pattern, and the recessed portion is formed at a position where the through hole should be disposed. Next, metal is deposited on the surface of the substrate via electroplating'. The metal, the groove, and the recess are thus deposited. In this manner, the wiring and the interlayer connection hole are formed via the deposited metal buried in the groove and the recess. [Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-2 1 0565 No. 200917921 [Patent Document 2] JP-A-2006-2069 [Problem to be Solved by the Invention] In the damascene method, wiring or via holes are formed on a substrate via a metal deposited by electroplating. However, the metal deposited by electroplating not only covers the grooves and recesses on the substrate, but also covers the grooves and portions other than the recesses. Therefore, after electroplating, it is necessary to carry out the process of removing unnecessary metal layers. This job is complicated. Moreover, it is difficult to remove this metal layer correctly. It is an object of the present invention to reduce the work of removing unnecessary metal layers when forming wiring or interlayer connection holes on a substrate by electroplating. [Means for Solving the Problem] According to the present invention, an additive is added to a plating solution used in electroplating. The additive has a function of suppressing the plating reaction, and has a function of reducing the function of suppressing the plating reaction as the electroplating reaction proceeds. Thereby, the metal can be selectively deposited on the grooves and recesses formed on the substrate. According to the present invention, in the plating solution used for electroplating, the polarization curve is such that when the potential is between the first potential E1 and the second potential E2, when the number of rotations is 1 OOO rpm, When the potential is traversed in the negative direction of 200917921, the current density increases sharply. On the other hand, when the potential is between the first potential E1 and the second potential E2, the polarization curve at the time of the rotation number of 1000 rpm intersects with the polarization curve when the number of rotations is 〇. According to the present invention, when a wiring or an interlayer connection hole is formed on a substrate by a damascene method, a groove having a specific surface roughness and a concave portion are formed on the substrate. [Effects of the Invention] An object of the present invention is to reduce the work of removing unnecessary metal layers when wiring or via holes are formed on a substrate by electroplating. [Embodiment] First, a brief description of the present invention will be given. According to the present invention, an additive is added to a plating solution used in electroplating. In the plating solution, an acidic copper sulfate solution can be used. The acidic copper sulfate solution used in the electroplating is known, and therefore will not be described in detail. Further, if an acidic copper sulfate solution is used, the wiring and the via holes are formed by copper. Wiring and vias can also be formed by metals other than copper. For example, nickel, aluminum, or the like can also be used. In this case, as the plating solution, a solution of a metal which is a raw material of a wiring and a through hole is used. The metal used in the conductive layer as the base of the plating may be copper, but a metal other than copper, for example, nickel, cobalt, chromium, tungsten, palladium, titanium: or contains An alloy of at least one of the metals. -7-200917921 According to the present invention, the additive has a function of suppressing the plating reaction, but also has a property of reducing the function of suppressing the plating reaction as the plating reaction progresses. The additive may be any substance if it has such a function and characteristics. The inventors of the present invention discovered that Cyanine pigments and derivatives thereof have such functions and characteristics. The cyanine pigment is represented by the following formula. However, the η system is one of 0, 1, 2, and 2. [Chemical Formula 1]
作爲此種使用於銅電鍍中之添加劑，係以對電鍍反應 作抑制，並在電鍍反應之進行的同時而失去電鍍反應抑制 效果之物質爲佳。添加劑之抑制電鍍反應的效果，係可藉 由在電鍍液中添加入添加劑時會使得金屬的析出過電壓變 大一事來作確認。而添加劑之在電鍍反應之進行的同時而 失去電鍍反應抑制效果的效果，係可藉由當電鍍液之流速 變得越快則使得金屬的析出過電壓變得越大一事來作確 認。此事，係代表若是添加劑之對於第1金屬層表面的供 給速度越快，則電鍍反應之抑制效果係變得越高。當添加 劑失去電鍍反應抑制效果時，係有添加劑被分解並變化成 其他之物質、或是添加劑被還原並變化爲氧化數相異之物 質的情況。 -8- 200917921 於以下，對於藉由以包含有此種添加劑 行電鍍，可大略選擇性地使電鍍在凹部內析 作敘述。若是使用此種添加劑來進行電鍍， 之進行的同時，在第1金屬層表面處，添加 效果。其結果，在第1金屬層表面處，對於 寄予之實效的添加劑濃度係減少。若是添 少，則添加劑係經由從溶液中之擴散而被作 在凹部內與在基板表面處之添加劑濃度的減 異。在凹部內，由於係在第1金屬層處形 此，相較於基板表面，相對上其表面積係爲 凹部內，添加劑濃度的減少速度係爲快。又 距離電鍍液的液面處之距離，相較於基板表 故而，在凹部內，添加劑之供給係變慢，而 加劑濃度的增加速度係爲慢。因此，相較於 凹部內係被維持爲添加劑濃度低的狀態。此 係具備有抑制電鍍反應之效果，因此，在添 之凹部內，電鍍反應係並不被抑制，而能夠 部內選擇性的成長。 作爲具備有此種特性之電鍍液，係以具 性爲理想：具備有在於旋轉盤狀電極處所測 中，相對於電極爲靜止時之情況，在電極以 轉時之電流値係成爲1 / 1 0 0以下之電位區 鍍液中，如圖7所示一般，當在某一電位 靜止時（〇rpm)之電流密度A，在lOOOrpm 之電鍍液來進 出一事的理由 則在電鍍反應 劑係失去其之 電鍍反應有所 加劑之濃度減 供給。此時， 少速度係爲相 成有凹凸，因 大。故而，在 ，在凹部內之 面亦爲較長。 擴散所致之添 基板表面，在 添加劑，由於 加劑濃度爲低 使電鍍膜在凹 備有以下之特 定之分極曲線 lOOOrpm 來旋 域。在此種電 E’下，相對於 時之電流密度 200917921 B係成爲1/ 100以下。 具備有此種分極曲線之電鍍液’係如同上述一般，能 夠在基板上之溝以及凹部內選擇性地使金屬析出。 若藉由本發明，則係經由金屬鑲嵌法，而在基板上形 成配線以及層間連接通孔。於此，一面對金屬鑲嵌法作說 明，一面對於在基板上所形成之溝以及凹部內的表面粗度 作說明。作爲粗度之指標，係週知有：藉由JISB060 1所 規定之算數平均粗度Ra、以及藉由JI SB 060 1所規定之粗 度曲線要素的平均長度RSm。若是藉由金屬鑲嵌法，則係 在基板上，經由適當之方法，而形成溝以及凹部。溝，係 被形成爲對應於配線圖案之形狀，而凹部，係被形成在應 配置通孔之位置。若藉由本發明，則係以使溝以及凹部內 具備有特定之表面粗度的方式，來形成溝以及R部。接下 來，在被形成有溝以及凹部之基板上，形成身爲電鍍之基 底的第1金屬層。接下來，經由電鍍，而在基板之表面處 形成第2金屬層。 在實行電鍍前，測定了形成有第1金屬層之基板的表 面粗度。其結果，在溝以及凹部內的算數平均粗度Ra， 係爲〇 _ 0 1〜4 μ m，較理想，係爲〇 _ 〇 1〜1 · 〇 μ m。粗度曲線 要素之平均長度RSm，係爲0.00 5〜8μπι，較理想，係爲 0.0 1〜2·0μιη。在溝以及凹部以外之區域、亦即是在基板 之表面處，算數平均粗度 Ra，較理想係爲o.ooi〜 0·0〇2μιη。粗度曲線要素之平均長度RSm，係爲10〜 50μηα，較理想，係爲20〜40μηι。 -10- 200917921 依據以上，在溝以及凹部內之算數平均粗度Ra，係 爲較溝以及凹部以外之區域、亦即是較基板之表面處的算 數平均粗度Ra更大。在溝以及凹部內之算數平均粗度 Ra ’係爲溝以及凹部以外之區域的算數平均粗度Ra之1 〇 倍以上。在溝以及凹部內之粗度曲線要素平均長度RSm， 係爲較溝以及凹部以外之區域、亦即是較基板之表面處的 粗度曲線要素平均長度RS m更小。在溝以及凹部內之粗 度曲線要素平均長度RSm，係爲溝以及凹部以外之區域的 粗度曲線要素平均長度RSm之1/10以下。 基板上之溝以及凹部內的表面粗度，在第1金屬層之 形成前與形成後，係幾乎沒有改變。故而，藉由在基板上 形成具備有所期望之表面粗度的溝以及凹部，在形成了第 1金屬層之後，可以得到具備有所期望之表面相度的溝以 及凹部。 如此這般，藉由在基板上形成具備有所期望之表面粗 度的溝以及凹部，並於其上形成第1金屬層，再更進而使 用添加有本發明所致之添加劑的電鍍液來進行電鍍，可以 在基板上之溝以及凹部內選擇性地使金屬析出。在基板上 之溝以及凹部以外之區域處、亦即是在基板之表面處，金 屬係並不被析出。故而，能夠減輕將在基板之表面上析出 的金屬除去之作業。本發明，係可適用於L S I內之銅配線 或是Si貫通電極之形成。 以下，對於本案之發明者所實施的電鍍之實施例作說 明。本案之發明者，係實施了實施例1〜8與比較例1之 -11 - 200917921 電鍍實驗。實施例1〜8，係爲使用有被添加了本發明所 致之添加劑的電鍍液所進行之電鍍實驗，比較例1，係爲 使用有先前技術之電鍍液的電鍍實驗。電鍍液，係在濃度 爲150g/dm3之硫酸銅5水化合物中添加濃度爲i80g/ dm3之硫酸所作成者。藉由於此電鍍液中添加本發明所致 之添加劑，而作成了本發明所致之電鍍液。 圖8，係展示實施例1〜8以及比較例1之實驗條件 與實驗結果。在添加劑的種類欄中所記載之記號，係代表 下述之化學物質。 A-l:2-[(l，3-Dihydro-l，3,3-trimethyl-2H_indol，2-ylidene)-methyl]-l?3,3-trimethyl-3H-indolium perchlorate A-2:2-[3-(l,3-Dihydro-l,3,3-trimethyl-2H-indol-2-ylidene)-l - propenyl]-l .3.3-trimethyl -3 H-indolium chloride A-3:2-[5-(l,3-Dihydro-l?3,3-trimethyl-2H-indol-2-ylidene)-l ,3-pentadienyl]-l ,3,3-trimethyl-3H-indolium iodide A-4:2-[7-(l,3-Dihydro-l,3,3-trimethyl-2H-indol-2- ylidene)-l，3,5-heptatrienyl]-l，3,3-trimethyl-3H-indolium iodide B : 3-Ethyl-2-[5-(3-ethyl-2(3H)-benzothiazolylidene) -1 ,3-pentadienyl]benzothiazolium iodideAs such an additive used in the copper plating, it is preferable to suppress the plating reaction and to lose the effect of suppressing the plating reaction while the electroplating reaction proceeds. The effect of suppressing the plating reaction of the additive can be confirmed by increasing the precipitation overvoltage of the metal when the additive is added to the plating solution. On the other hand, the effect of suppressing the effect of suppressing the plating reaction while the electroplating reaction is being carried out can be confirmed by making the precipitation overvoltage of the metal larger as the flow rate of the plating solution becomes faster. In this case, the higher the supply rate of the additive to the surface of the first metal layer, the higher the suppression effect of the plating reaction. When the additive loses the effect of suppressing the plating reaction, there are cases where the additive is decomposed and changed into other substances, or the additive is reduced and changed to a substance having a different oxidation number. -8- 200917921 In the following, by electroplating with such an additive, electroplating can be roughly and selectively described in the concave portion. When such an additive is used for electroplating, the effect is added to the surface of the first metal layer. As a result, the concentration of the additive effective for the deposition on the surface of the first metal layer is reduced. If it is less, the additive is reduced in the concentration of the additive in the recess and at the surface of the substrate by diffusion from the solution. In the concave portion, since it is formed at the first metal layer, the surface area is relatively small in the concave portion as compared with the surface of the substrate, and the rate of decrease in the additive concentration is fast. Further, the distance from the liquid surface of the plating solution is slower than that of the substrate, and the supply of the additive is slow in the concave portion, and the increase rate of the additive concentration is slow. Therefore, it is maintained in a state where the concentration of the additive is low as compared with the inside of the recess. Since this has an effect of suppressing the plating reaction, the plating reaction is not suppressed in the added concave portion, and the inside can be selectively grown. It is preferable that the plating liquid having such characteristics is provided with a property in which the current is reversed when the electrode is turned while the electrode is stationary while being measured at the rotating disk electrode. In the plating solution of the potential region below 0 0, as shown in Fig. 7, when the current density A at a certain potential is at rest (〇 rpm), the reason why the plating solution at 1000 rpm comes in and out is lost in the plating reaction system. The electroplating reaction of the electroplating reaction is reduced by the concentration of the additive. At this time, the low speed is uneven, and the difference is large. Therefore, the surface inside the recess is also long. Diffusion caused by the addition of the substrate surface, in the additive, due to the low concentration of the additive, the plating film has the following specific polarization curve lOOOOrpm to rotate the domain. Under this electric E', the current density 200917921 B is 1/100 or less. The plating solution having such a polarization curve is as described above, and it is possible to selectively deposit metal in the groove and the recess in the substrate. According to the present invention, wiring and interlayer connection via holes are formed on the substrate via the damascene method. Here, the surface roughness of the groove formed in the substrate and the concave portion will be described with reference to the metal damascene method. As an index of the roughness, the arithmetic mean roughness Ra as defined by JIS B060 1 and the average length RSm of the thickness curve elements defined by JIS B 060 1 are known. In the case of the damascene method, grooves and recesses are formed on the substrate by an appropriate method. The groove is formed to correspond to the shape of the wiring pattern, and the concave portion is formed at a position where the through hole should be disposed. According to the present invention, the groove and the R portion are formed such that the groove and the recess have a specific surface roughness. Next, a first metal layer which is a substrate for electroplating is formed on the substrate on which the grooves and the recesses are formed. Next, a second metal layer is formed on the surface of the substrate by electroplating. Before the plating was performed, the surface roughness of the substrate on which the first metal layer was formed was measured. As a result, the arithmetic mean roughness Ra in the groove and the concave portion is 〇 _ 0 1 to 4 μ m, and preferably 〇 _ 〇 1 to 1 · 〇 μ m. The average length RSm of the roughness curve element is 0.00 5 to 8 μm, which is preferably 0.0 1 to 2·0 μιη. In the region other than the groove and the recess, that is, at the surface of the substrate, the arithmetic mean roughness Ra is preferably o.ooi~0·0〇2μιη. The average length RSm of the thickness curve elements is 10 to 50 μηα, and preferably 20 to 40 μm. -10-200917921 According to the above, the arithmetic mean roughness Ra in the groove and the concave portion is larger than the groove and the concave portion, that is, the arithmetic mean roughness Ra at the surface of the substrate. The arithmetic mean roughness Ra ′ in the groove and the recess is 1 〇 or more of the arithmetic mean roughness Ra of the region other than the groove and the recess. The average length RSm of the roughness curve elements in the grooves and the recesses is smaller than the groove and the recesses, that is, the average length RSm of the thickness curve elements at the surface of the substrate. The average length RSm of the roughness curve elements in the grooves and the recesses is 1/10 or less of the average length RSm of the roughness curve elements in the regions other than the grooves and the recesses. The surface roughness of the groove and the recess in the substrate is hardly changed before and after the formation of the first metal layer. Therefore, by forming the groove and the recess having the desired surface roughness on the substrate, after the first metal layer is formed, the groove and the recess having the desired surface phase can be obtained. In this manner, a groove having a desired surface roughness and a concave portion are formed on the substrate, and a first metal layer is formed thereon, and further, a plating solution to which the additive of the present invention is added is further used. Electroplating selectively deposits metal in the grooves and recesses on the substrate. The metal system is not deposited at the regions other than the grooves and the recesses on the substrate, that is, at the surface of the substrate. Therefore, it is possible to reduce the work of removing the metal deposited on the surface of the substrate. The present invention can be applied to the formation of a copper wiring or a Si through electrode in L S I . Hereinafter, an embodiment of electroplating performed by the inventors of the present invention will be described. The inventors of the present invention carried out electroplating experiments of Examples 1 to 8 and Comparative Example 1 -11 - 200917921. Examples 1 to 8 were electroplating experiments using a plating solution to which an additive of the present invention was added, and Comparative Example 1 was an electroplating experiment using a plating solution of the prior art. The plating solution was prepared by adding sulfuric acid having a concentration of i80 g/dm3 to a copper sulfate 5 aqueous compound having a concentration of 150 g/dm3. The plating solution resulting from the present invention was prepared by adding the additive of the present invention to the plating solution. Fig. 8 shows the experimental conditions and experimental results of Examples 1 to 8 and Comparative Example 1. The symbols described in the column of the types of additives represent the following chemical substances. Al:2-[(l,3-Dihydro-l,3,3-trimethyl-2H_indol,2-ylidene)-methyl]-l?3,3-trimethyl-3H-indolium perchlorate A-2:2-[3 -(l,3-Dihydro-l,3,3-trimethyl-2H-indol-2-ylidene)-l - propenyl]-l .3.3-trimethyl -3 H-indolium chloride A-3:2-[5- (l,3-Dihydro-l?3,3-trimethyl-2H-indol-2-ylidene)-l,3-pentadienyl]-l ,3,3-trimethyl-3H-indolium iodide A-4:2-[ 7-(l,3-Dihydro-l,3,3-trimethyl-2H-indol-2- ylidene)-l,3,5-heptatrienyl]-l,3,3-trimethyl-3H-indolium iodide B : 3 -Ethyl-2-[5-(3-ethyl-2(3H)-benzothiazolylidene) -1 ,3-pentadienyl]benzothiazolium iodide
C ·_ Janus Green B 藉由JISB030 1所規定之算數平均粗度Ra、以及藉由 -12- 200917921 JISB 060 1所規定之粗度曲線要素的平均長度RSm，係爲 在形成了第1金屬層後所測定之基板上的溝以及凹部處之 表面粗度的測定値。 [實施例1 ] 參考圖1，對本發明所致之配線的形成方法作說明。 於此，係對本案之發明者所致的實施例1作說明。如圖1 (a)中所示一般，作爲基板1，準備了厚度25 μηι之聚醯 亞胺薄膜（TORAY · DUPONT股份有限公司製ΚΑΡΤΟΝ ΕΝ )。 如圖1 ( b )中所示一般，對基板1之表面進行了粗 面化處理。在粗面化處理中，係使用有將鋁微粒子噴吹附 著於基板1之表面處的噴砂處理。在粗面化處理中，係可 使用化學性之粗面化處理、電性之粗面化處理、又或機械 性之粗面化處理的任一者，又或是，亦可使用此些之組 合。化學性粗面化處理，係有使用N a ◦ Η水溶液等之鹼性 液的鹼性蝕刻處理、使用過錳酸鹽、重鉻酸鹽、過硫酸 鹽、次亞氯酸鹽、亞氯酸鹽、氯酸鹽等之酸性鹽的氧化處 理、使用聯胺（hydrazine )等之蝕刻等。電性之粗面化處 理，係有真空中電漿處理、大氣中電暈處理等。機械性粗 面化處理，係有使用鋼絲刷之刷洗處理等。 在粗面化處理後，經由表面粗度測定裝置，對基板1 之表面的表面粗度.作了測定。如圖8中所示一般，藉由 JISB0 60 1所規定之算數平均粗度Ra，係爲〇.4μιη，藉由 -13- 200917921 JISB0601所規定之粗度曲線要素的平均長度RSm，係爲 1 · 1 μ m 〇 如圖1 ( c )中所示一般’在粗面化後之基板1之表 面’形成了光阻膜2。在光阻劑中，係使用有新日鐵化學 公司製之V-25 9PA。作爲光阻劑，亦可使用日立化成公司 製之RY-3219、旭化成電子公司製之SPG-202等。光阻膜 之厚度，係爲ΙΟμηι。 如圖1 ( d )中所示一般，經由光微影法，而在光阻 膜2處，沿著配線圖案而形成了寬幅7〜1 0 0 μ m之溝2 a。 如圖1(e)中所示一般，形成了身爲電鍍之基底的 第1金屬層3。金屬層3，係形成於基板之表面，亦即是 形成於溝3 a內以及溝3 a以外之區域3 c處。於本例中， 第1金屬層3，係爲經由無電解鎳電鍍所形成之鎳膜。在 無電解鎳電鍍液中，係使用有奧野製藥公司製之 TOPCHEMIALLOY 66。鎳之膜厚，係爲 200nm。在基底 之形成方法中，除了無電解鎳電鍍法之外，亦可使用蒸鍍 法、濺鍍法、化學氣相成長（CVD )法等。又，作爲第1 金屬層，除了鎳膜之外，亦可使用鉻、鎢、鈀、鈦以及此 些之合金的膜。 在形成了第1金屬層3之後，經由表面粗度測定裝 置，來對溝3 a內之表面粗度，以及溝3 a以外之區域3 c 的表面粗度作了測定。溝3 a內之表面粗度，係與在粗面 化處理後所測定之基板1之表面的表面粗度爲相同。又， 在溝3a以外之區域3c處，藉由JISB0601所規定之算數 -14- 200917921 平均粗度Ra，係爲Ο.ΟΟΙμηι，藉由JISB060 1所規定之粗 度曲線要素的平均長度RSm，係爲34μιη。 如圖1 ( f)中所示一般，經由銅電鍍，而形成了第2 金屬層4。第2金屬層4，係爲銅電鍍膜。電鍍條件，係 如同圖8所示一般。又，電鍍時間係爲1 0分鐘，電流密 度係爲l.OA/dm2，電鍍液之溫度係爲25°C。 在銅電鍍後，進行了配線剖面觀察。如圖6中所示一 般，將在溝3a內之銅電鍍膜厚設爲T1，將在溝3a以外 之區域3 c處的銅電鍍膜厚設爲T3。於實施例1中，在溝 3a內之銅電鍍膜厚T1，係爲ΙΟμπι。又，在溝3a以外之 區域3c處的銅電鍍膜厚T3，係爲0.001 μιη以下。故而， 在實施例1中，可以得知，銅電鍍膜，係在基板上之溝 3 a內選擇性地成長，而在溝3 a以外之區域3 c、亦即是在 基板之表面，銅係幾乎不會析出。 如圖1 ( g )中所示一般，將光阻膜2之表面的第1 金屬層3，亦即是將鎳膜除去。在鎳膜之除去中，係使用 有MEC公司製之CH-1935。在鎳膜之除去中，亦可使用 Meltex 公司製之 Melstrip、EBARA-UDYLITE 公司製之 SEEDLON PROCESS等。在光阻膜2之表面處所形成之些 許的銅電鍍膜，係可與鎳膜而同時地除去。 如此這般’在實施例1中，光阻膜2之表面、亦即是 在溝3 a以外之區域3 c處的銅電鍍膜之除去係成爲不必 要’而具備有深度1 Ομιη、寬幅7〜1 ΟΟμιη之銅配線的配 線板之製造，係成爲容易。 -15- 200917921 [實施例2] 參考圖2，對本發明所致之層間連接通孔的形成方法 作說明。於此，係對本案之發明者所致的實施例2作說 明。如圖2(a)中所示一般，作爲基板1，準備了厚度 25μηι之聚醯亞胺薄膜（TORAY . DUPONT股份有限公司 製KAPTON EN)，並於其表面上，貼附了厚度12μηι之 銅箔5。 如圖2(b)中所示一般，對銅箔5之表面進行了粗 面化處理。粗面化處理，係與實施例1相同。 在粗面化處理後，經由表面粗度測定裝置，對銅箔5 之表面的表面粗度作了測定。如圖8中所示一般，藉由 JISB0601所規定之算數平均粗度Ra，係爲〇·4μιη，藉由 JISB0601所規定之粗度曲線要素的平均長度RSm，係爲 0.8 μ m 〇 如圖2(c)中所示一般，在粗面化後之銅箔5之表 面’形成了光阻膜2。在光阻劑中，係使用有新日鐵化學 公司製之V-259PA。光阻膜之厚度，係爲ΐ〇μπ1。 如圖2 ( d )中所示一般，經由光微影法，而在光阻 膜2處，於應配置層間連接通孔的位置處而形成了直徑 20〜200μηι之凹部2a。 如圖2(e)中所示一般，形成了身爲電鍍之基底的 第1金屬層3。金屬層3 ’係形成於基板之表面，亦即是 形成於凹部3 b內以及凹部3 b以外之區域3 c處。於本例 -16- 200917921 中，第1金屬層3，係爲經由無電解鎳電鍍所形成之鎳 膜。在無電解鎳電鍍液中，係使用有奧野製藥公司製之 TOPCHEMIALLOY 66。鎳之膜厚，係爲 200nm。 在形成了第1金屬層3之後，經由表面粗度測定裝 置，來對凹部3b內之表面粗度，以及凹部3b以外之區域 3c的表面粗度作了測定。凹部3b內之表面粗度，係與在 粗面化處理後所測定之基板1之表面的表面粗度爲相同。 又，在凹部3b以外之區域3c處，藉由JISB0601所規定 之算數平均粗度Ra，係爲0.002 μιη，藉由JISB0 60 1所規 定之粗度曲線要素的平均長度RSm，係爲27μηι。 如圖2(f)中所示一般，經由銅電鑛，而形成了第2 金屬層4。第2金屬層4，係爲銅電鍍膜。電鍍條件，係 如同圖8所示一般。又，電鍍時間係爲1 0分鐘，電流密 度係爲1 ·0Α/ dm2，電鍍液之溫度係爲25°C。 如圖2(g)中所示一般，將光阻膜2之表面的第1 金屬層3，亦即是將鎳膜除去。鎳膜之除去，係藉由與實 施例1相同之方法。 如此這般，在實施例2中，光阻膜2之表面、亦即是 在凹部3 b以外之區域3 c處的銅電鍍膜之除去係成爲不必 要，而具備有直徑2 0〜2 0 0 μ m之層間連接通孔的配線板 之製造，係成爲容易。 [實施例3] 參考圖3，對本發明所致之層間連接通孔的形成方法 -17- 200917921 作說明。於此，係對本案之發明者所致的實施例3作說 明。實施例3，除了將銅箱之粗化處理工程在光阻凹部形 成後再進行一事以外，係與實施例2相同。如圖3 ( a ) 中所示一般，作爲基板丨，準備了厚度之聚醯亞胺 薄膜(TORAY . DUPONT股份有限公司製 KAPTON EN)，並於其表面上，貼附了厚度12μπι之銅箔5。 如圖3(b)中所示一般，在銅箔5之表面’形成了 光阻膜2。在光阻劑中，係使用有新日鐵化學公司製之V-259ΡΑ。光阻膜之厚度，係爲ΙΟμιη。 如圖3 ( c )中所示一般，經由光微影法，而在光阻 膜2處，於應配置層間連接通孔的位置處而形成了直徑 20〜200μιη之凹部2a。 如圖3 ( d )中所示一般，對銅箔 5之表面進行了粗 面化處理。亦即是，對露出於光阻膜2之凹部2a處的銅 箔5進行了粗面化處理。粗面化處理，係與實施例1相 同。從圖3(e)起直到圖3(g)爲止，係和從圖2(e) 起直到圖2 ( g )爲止爲相同。亦即是，如圖3 ( e )中所 示一般，形成了身爲電鍍之基底的第1金屬層3。如圖3 (f)中所示一般，經由銅電鍍，而形成了第2金屬層 4。第2金屬層4，係爲銅電鍍膜。電鍍條件，係如同圖8 所示一般。 在銅電鍍後，進行了配線剖面觀察。如圖6中所示— 般’將在凹部3b內之銅電鍍膜厚設爲T2。於實施例3 中’在凹部3b內之銅電鍍膜厚T2，係爲1〇μιη。又，在 -18- 200917921 凹部3b以外之區域3c處的銅電鍍膜厚T3，係爲Ο.ΟΟΙμηι 以下。故而，在實施例3中，可以得知，銅電鍍膜，係在 基板上之凹部3b內選擇性地成長’而在凹部3b以外之區 域3c、亦即是在基板之表面，銅係幾乎不會析出。 如圖3(g)中所示一般’將光阻膜2之表面的第1 孟：屬層3 ’亦即是將鎳膜除去。如此這般，在實施例3 中’光阻膜2之表面、亦即是在凹部3b以外之區域3c處 的銅電鍍膜之除去係成爲不必要，而具備有直徑2〇〜 2 00 μπι之層間連接通孔的配線板之製造，係成爲容易。 [實施例4] 參考圖4，對本發明所致之配線的形成方法作說明。 於此，係對本案之發明者所致的實施例4作說明。如圖4 (a)中所示一般，作爲基板1，準備了厚度5〇μιη之聚醯 亞胺薄膜（宇部興業公司製UP ILEX)。 如圖4(b)中所示一般’在基板1之表面處，使用 準分子雷射，而沿著配線圖案形成了深度7 μ m、寬幅7〜 1 0 0 μ m 之溝 1 a。 經由表面粗度測定裝置，對基板1之溝1 a內的表面 粗度作了測定。如圖8中所示一般，藉由JISB060 1所規 定之算數平均粗度Ra，係爲〇_〇5μηι，藉由jlSB〇6〇l所規 定之粗度曲線要素的平均長度RSm，係爲0.2μιη。 如圖4(c)中所示一般，使用濺鍍法，而形成了第1 金屬層3。金屬層3，係形成於基板之表面，亦即是形成 -19- 200917921 於溝3 a內以及溝3 a以外之區域3 c處。第1金屬層，係 爲包含有25%之鉻的鎳膜。膜厚，係爲1〇〇nm° 在形成了第1金屬層3之後，經由表面粗度測定裝 置，來對溝3 a內之表面粗度，以及溝3 a以外之區域3 c 的表面粗度作了測定。溝3 a內之表面粗度，係與第1金 屬層3形成前的表面粗度爲相同。又，在溝3 a以外之區 域3c處，藉由JISB060 1所規定之算數平均粗度Ra’係 爲Ο.ΟΟΙμιη，藉由JISB0601所規定之粗度曲線要素的平 均長度R S m ’係爲3 4 μ m。 如圖4 ( d )中所示一般，經由銅電鍍，而形成了第2 金屬層4。第2金屬層4，係爲銅電鍍膜。電鍍條件，係 如同圖8所示一般。又，電鍍時間係爲5分鐘，電流密度 係爲2.0 A/ dm2，電鍍液之溫度係爲25 °C。 在銅電鍍後，進行了配線剖面觀察。於實施例4中， 在溝3a內之銅電鍍膜厚T1，係爲7μπι。又，在溝3a以 外之區域3c處的銅電鍍膜厚T3，係爲0.001 μηι以下。故 而’在實施例4中，可以得知，銅電鍍膜，係在基板上之 溝3 a內選擇性地成長，而在溝3 a以外之區域3 c、亦即 是在基板之表面，銅係幾乎不會析出。 如圖4(e)中所示一般，將基板1之表面的第1金 屬層3 ’亦即是將鎳膜除去。在鎳膜之除去中，係使用有 MEC公司製之CH-1935。在光阻表面所形成之些許的銅電 鍍膜，係可與鎳膜而同時地除去。 如此這般’在實施例4中，基板1之表面、亦即是在 -20- 200917921 溝3 a以外之區域3 c處的銅電鍍膜之除去係成爲不必要， 而具備有深度7μηι、寬幅7〜iOO^m之銅配線的配線板之 製造，係成爲容易。 [實施例5] 參考圖5，對本發明所致之配線層間連接通孔的形成 方法作說明。於此，係對本案之發明者所致的實施例5作 說明。如圖5(a)中所示一般，作爲基板1，使用了厚度 ΙΟΟμιη之聚對苯二甲酸乙二酯薄膜（Teijin Dupont Films 公司製TEFLEX)。此薄膜，係包含有銅箔5。 如圖5 ( b )中所示一般，經由使用有鎳製模具6之 奈米壓印處理，而在基板1之表面處，形成深度5μιη、寬 幅5〜ΙΟΟμιη之溝7，同時，在溝7之底面處，形成了深 度5 μπι、直徑5 μηι之凹部8。溝7，係沿著配線圖案而形 成，而凹部8，係被形成在應配置層間連接通孔之位置 處。 在奈米壓印處理後，經由表面粗度測定裝置，對溝7 以及凹部8之表面粗度作了測定。如圖8中所示一般，藉 由JISB060 1所規定之算數平均粗度Ra，係爲0.4μηι，藉 由JISB0 60 1所規定之粗度曲線要素的平均長度RSm，係 爲 1 . 1 μπι。 如圖5 ( c )中所示一般，將凹部8之底部的樹脂藉 由蝕刻而除去，並使銅箔5露出。如圖5(d)中所示一 般，對露出了的銅箔5之表面進行了粗面化處理。粗面化 -21 - 200917921 處理，係與實施例1相同 在粗面化處理後，經由表面粗度測定裝置，對露出之 銅箔5的表面粗度作了測定。如圖8中所示一般，藉由 JISB 060 1所規定之算數平均粗度Ra，係爲〇·4μιη，藉由 JISB060 1所規定之粗度曲線要素的平均長度RSm，係爲 1 · 1 μιη 〇 如圖5(e)中所示一般，使用濺鍍法，而形成了第i 金屬層3。金屬層3，係形成於基板之表面，亦即是形成 於溝3 b以及凹部3 a內和其以外之區域3 c處。實施例5 之第1金屬層3，係爲鈦膜，膜厚係爲50nm。 在形成了第1金屬層3之後，經由表面粗度測定裝 置，來對凹部3 a、溝3 b以及其之外的區域3 c處之表面 粗度作了測定。溝3b以及凹部3a之銅箔的表面耜度，係 與在第1金屬層3形成前所測定的表面粗度爲相同。又， 在溝部以及凹部以外之區域3c處、亦即是於基板之表 面，藉由JISB0601所規定之算數平均粗度Ra，係爲 Ο.ΟΟΙμιη，藉由JISB0601所規定之粗度曲線要素的平均長 度 RSm，係爲 30μπι。 如圖5 ( f)中所示一般，經由銅電鑛，而形成了第2 金屬層4。第2金屬層4，係爲銅電鍍膜。電鍍條件’係 如同圖8所示一般。又，電鍍時間係爲20分鐘，電流密 度係爲0.5A/ dm2，電鍍液之溫度係爲25°C。 在銅電鍍後，進行了配線剖面觀察。於實施例5中’ 在溝3a內之銅電鍍膜厚T1，係爲5μηι，在凹部內之銅電 -22- 200917921 鍍膜厚Τ2，係爲1 0 μηι。在奈米壓印加工部以外 亦即是在基板之表面處的銅電鍍膜厚Τ3，係爲 以下。故而，在實施例5中，可以得知，銅電鍍 基板上之溝3 a內選擇性地成長，而在溝3 a以 3c、亦即是在基板之表面，銅係幾乎不會析出。 如圖5 ( g )中所示一般，將基板1之表面丨 屬層3，亦即是將鎳膜除去。在鎳膜之除去中， MEC公司製之CH- 1 93 5。在光阻表面所形成之些 鍍膜，係可與鎳膜而同時地除去。 如此這般，在實施例5中，基板1之表面、 溝3 a以外之區域3 c處的銅電鍍膜之除去係成爲 而一括具備有深度5μιη、寬幅5〜ΙΟΟμιη之銅配 徑5 μιη之層間連接通孔的配線板之製造，係成爲 [實施例6] 再度參考圖1，對本發明所致之配線的形成 明。於此，係對本案之發明者所致的實施例6作 圖1(a)中所示一般，作爲基板1，準備了厚度 液晶聚合物薄膜〇&?&11〇〇^-丁6\公司製81八(：） 如圖1(b)中所不一般’對基板1之表面 面化處理。在粗面化處理中，係使用有將鋁微粒 著於基板1之表面處的噴砂處理。 在粗面化處理後，經由表面粗度測定裝置， 之表面的表面粗度作了測定。如圖8中所示一 之區域、 0.00 1 μηι 膜，係在 外之區域 β第1金 係使用有 許的銅電 亦即是在 不必要， 線以及直 容易。 方法作說 說明。如 5 0 μ m 之 〇 進行了粗 子噴吹附 對基板1 般，藉由 -23- 200917921 JISB060 1所規定之算數平均粗度Ra，係爲0.6μηι，藉由 JISB060 1所規定之粗度曲線要素的平均長度RSm，係爲 1 · 5 μ m 〇 如圖1 ( c)中所示一般，在粗面化後之基板1之表 面，形成了光阻膜2。在光阻劑中，係使用有日立化成公 司製之RY-3219。光阻膜之厚度，係爲5μιη。 如圖1 ( d )中所示一般，經由光微影法，而在光阻 膜2處，形成了寬幅5〜ΙΟΟμηι之溝2a。 如圖1(e)中所示一般，形成了身爲電鍍之基底的 第1金屬層3。第1金屬層3，係爲經由無電解電鍍所形 成之銅膜。在無電解電鍍液中，係使用有日立化成公司製 之CUST-201。銅之膜厚，係爲100nm。 在形成了第1金屬層3之後，經由表面粗度測定裝 置，來對溝3 a內之表面粗度，以及溝3 a以外之區域3 c 的表面粗度作了測定。溝3 a內之表面粗度，係與在粗面 化處理後所測定之基板1之表面的表面粗度爲相同。又， 在溝3a以外之區域3c處，藉由JISB0601所規定之算數 平均粗度Ra，係爲Ο.ΟΟΙμιη，藉由JISB0 60 1所規定之粗 度曲線要素的平均長度RSm，係爲3 1 μιη。 如圖1 (f)中所示一般，經由銅電鍍，而形成了第2 金屬層4。第2金屬層4，係爲銅電鍍膜。電鍍條件，係 如同圖8所示一般。又，電鍍時間係爲10分鐘，電流密 度係爲1 ·0Α/ dm2，電鍍液之溫度係爲25°C。 在銅電鍍後，進行了配線剖面觀察。於實施例6中， -24- 200917921 在溝3a內之銅電鍍膜厚T1，係爲ΙΟμιη。又，在溝33以 外之區域3c處的銅電鑛膜厚Τ3’係爲Ο.ΟΟίμιη以下。故 而，在實施例6中，可以得知’銅電鍍膜，係在基板上之 溝3 a內選擇性地成長，而在溝3 a以外之區域3 c、亦即 是在基板之表面，銅係幾乎不會析出。 如圖1(g)中所示一般，將光阻膜2之表面的第1 金屬層3、亦即是將銅膜除去。在銅膜之除去中，係使用 有MEC公司製之CH-1935。在鎳膜之除去中，係使用有 MEC公司製之MECBRITE VE-7100系列。在光阻表面所 形成之些許的銅電鍍膜，係可與鎳膜而同時地除去。 如此這般，在實施例6中，光阻膜2之表面、亦即是 在溝3 a以外之區域3 c處的銅電鍍膜之除去係成爲不必 要，而具備有深度1Ομιη、寬幅5〜ΙΟΟμηι之銅配線的配 線板之製造，係成爲容易。 [實施例7] 再度參考圖1，對本發明所致之配線的形成方法作說 明。於此，係對本案之發明者所致的實施例7、8作說 明。實施例7〜8，在添加劑之種類、添加劑之濃度、以 及電鑛電流密度上，係與實施例1相異，但是’除此之 外，係和實施例1爲相同。電鍍條件，係如同圖8所示一 般。 在銅電鍍後，進行了配線剖面觀察。於實施例7以及 8中，在溝3a內之銅電鍍膜厚Τ1，係爲ΙΟμιη。又’在溝 -25- 200917921 3 a以外之區域3 c處的銅電鍍膜厚Τ 3，係爲0.0 0 1 μιη以 下。故而，在實施例7以及8中，可以得知，銅電鍍膜， 係在基板上之溝3 a內選擇性地成長，而在溝3 a以外之區 域3c、亦即是在基板之表面，銅係幾乎不會析出。 如此這般，在實施例7以及8中，光阻膜2之表面、 亦即是在溝3 a以外之區域3 c處的銅電鍍膜之除去係成爲 不必要，而具備有深度ΙΟμηι、寬幅7〜ΙΟΟμπι之銅配線 的配線板之製造，係成爲容易。 [比較例1 ] 比較例1’除了在電鍍液中並不包含有添加劑一事以 外，係與實施例1相同。電鍍條件，係如同圖8所示一 般。在銅電鍍後’進行了配線剖面觀察。於比較例中，在 溝3 a內之銅電鍍膜厚Τ 1，係爲2 · 1 μ m。又，在溝3 a以外 之區域3c處的銅電鍍膜厚T3，係爲2·2μιη。在比較例 中’銅電鑛膜，於基板上之溝3a以及溝3a以外之區域 3 c處’係幾乎均勻地成長。亦即是，可以得知，在基板 之表面處，係析出有與溝3a幾乎相同厚度之銅。 在比較例中，光阻膜2之表面、亦即是在溝3 a以外 之區域3 c處的銅電鍍膜之除去係成爲必要，而具備有深 度1 0 μ m、寬幅7〜1 0 0 μ m之銅配線的配線板之製造，係 成爲困難。 以上，雖係對本發明之例子作了說明，但是，本發明 係並不被上述之例子所限定，若是同業者，則應可容易地 -26- 200917921 理解’在申請專利範圍所記載之發明範圍內，可作各種之 變更。 【圖式簡單說明】 [圖1 ]對本發明所致之配線的形成方法作說明之圖。 [圖2]對本發明所致之層間連接通孔的形成方法作說 明之圖。 [圖3]對本發明所致之層間連接通孔的形成方法作說 明之圖。 [圖4]對本發明所致之配線的形成方法作說明之圖。 [圖5 ]對本發明所致之配線以及層間連接通孔的形成 方法作說明之圖。 [圖6]展示本發明所致之配線以及層間連接通孔板的 銅電鑛膜厚之評價位置的剖面圖。 [圖7]對本發明所致之電鍍液的特性作說明之圖。 [圖8]對本發明所致之配線以及層間連接通孔的形成 方法之實施例的電鍍條件作展示之圖。 【主要元件符號說明】 1 :基板 2 :光阻 3 :第1金屬層（基底） 4:第2金屬層（銅電鍍膜） 5 :銅箔 -27- 200917921 6 :模具 7 :溝 8 :凹部 -28C · _ Janus Green B is the first metal layer formed by the arithmetic mean roughness Ra specified in JIS B030 1 and the average length RSm of the thickness curve elements specified by -12-200917921 JISB 060 1 The measurement of the surface roughness of the groove and the concave portion on the substrate measured later. [Embodiment 1] A method of forming a wiring according to the present invention will be described with reference to Fig. 1. Here, Embodiment 1 of the inventor of the present invention will be described. As shown in Fig. 1 (a), as a substrate 1, a polyimide film having a thickness of 25 μm (TORAY, manufactured by DUPONT Co., Ltd.) was prepared. As shown in Fig. 1 (b), the surface of the substrate 1 is roughened. In the roughening treatment, a sandblasting treatment in which aluminum fine particles are sprayed and attached to the surface of the substrate 1 is used. In the roughening treatment, any of chemical roughening treatment, electrical roughening treatment, or mechanical roughening treatment may be used, or such a use may be used. combination. The chemical roughening treatment is an alkaline etching treatment using an alkaline liquid such as a Na ◦ Η aqueous solution, using permanganate, dichromate, persulfate, hypochlorite, chlorite Oxidation treatment of an acid salt such as a salt or a chlorate, etching using a hydrazine or the like. Electrical roughening treatment, such as vacuum plasma treatment, atmospheric corona treatment. The mechanical roughening treatment is a brushing treatment using a wire brush. After the roughening treatment, the surface roughness of the surface of the substrate 1 was measured by a surface roughness measuring device. As shown in Fig. 8, in general, the arithmetic mean roughness Ra specified by JIS B0 60 1 is 〇.4μιη, and the average length RSm of the thickness curve element specified by-13-200917921 JISB0601 is 1 · 1 μ m 〇 As shown in Fig. 1 (c), the photoresist film 2 is generally formed on the surface of the substrate 1 after roughening. Among the photoresists, V-25 9PA manufactured by Nippon Steel Chemical Co., Ltd. was used. As the photoresist, RY-3219 manufactured by Hitachi Chemical Co., Ltd., SPG-202 manufactured by Asahi Kasei Electronics Co., Ltd., or the like can be used. The thickness of the photoresist film is ΙΟμηι. As shown in Fig. 1 (d), a groove 2a having a width of 7 to 1 0 0 μm is formed along the wiring pattern via the photolithography method. As shown in Fig. 1(e), a first metal layer 3 which is a substrate for electroplating is formed. The metal layer 3 is formed on the surface of the substrate, that is, in the region 3c outside the trench 3a and outside the trench 3a. In this example, the first metal layer 3 is a nickel film formed by electroless nickel plating. In the electroless nickel plating solution, TOPCHEMIALLOY 66 manufactured by Okuno Pharmaceutical Co., Ltd. is used. The film thickness of nickel is 200 nm. In the method of forming the substrate, in addition to the electroless nickel plating method, a vapor deposition method, a sputtering method, a chemical vapor deposition (CVD) method, or the like can be used. Further, as the first metal layer, in addition to the nickel film, a film of chromium, tungsten, palladium, titanium, or an alloy of these may be used. After the first metal layer 3 was formed, the surface roughness of the groove 3a and the surface roughness of the region 3c other than the groove 3a were measured by the surface roughness measuring device. The surface roughness in the groove 3a is the same as the surface roughness of the surface of the substrate 1 measured after the roughening treatment. Further, in the region 3c other than the groove 3a, the average thickness Ra of the calculation -14-17917921 prescribed by JIS B0601 is Ο.ΟΟΙμηι, and the average length RSm of the thickness curve element specified by JIS B060 1 is It is 34μηη. As shown in Fig. 1 (f), the second metal layer 4 is formed by copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in Fig. 8. Further, the plating time was 10 minutes, the current density was 1.0 OA/dm 2 , and the temperature of the plating solution was 25 °C. After the copper plating, the wiring profile was observed. As shown in Fig. 6, the thickness of the copper plating film in the groove 3a is set to T1, and the thickness of the copper plating film in the region 3c other than the groove 3a is set to T3. In the first embodiment, the thickness T1 of the copper plating film in the groove 3a is ΙΟμπι. Further, the thickness of the copper plating film T3 in the region 3c other than the groove 3a is 0.001 μm or less. Therefore, in the first embodiment, it is understood that the copper plating film is selectively grown in the groove 3 a on the substrate, and the region 3 c other than the groove 3 a, that is, on the surface of the substrate, copper The system will hardly precipitate. As shown in Fig. 1 (g), the first metal layer 3 on the surface of the photoresist film 2, that is, the nickel film is removed. In the removal of the nickel film, CH-1935 manufactured by MEC Corporation was used. In the removal of the nickel film, Melstrip manufactured by Meltex, SEEDLON PROCESS manufactured by EBARA-UDYLITE, or the like can also be used. A portion of the copper plating film formed at the surface of the photoresist film 2 can be simultaneously removed from the nickel film. Thus, in the first embodiment, the surface of the photoresist film 2, that is, the removal of the copper plating film at the region 3c other than the groove 3a is unnecessary, and has a depth of 1 Ο μηη, a wide width. It is easy to manufacture the wiring board of the 7~1 ΟΟμιη copper wiring. -15-200917921 [Embodiment 2] A method of forming the interlayer connection via hole by the present invention will be described with reference to Fig. 2 . Here, Embodiment 2 of the inventor of the present invention will be described. As shown in Fig. 2(a), as a substrate 1, a polyimide film (KapTON EN manufactured by TORAY. DUPONT Co., Ltd.) having a thickness of 25 μm was prepared, and a copper having a thickness of 12 μm was attached to the surface thereof. Foil 5. As shown in Fig. 2(b), the surface of the copper foil 5 is roughened. The roughening treatment is the same as in the first embodiment. After the roughening treatment, the surface roughness of the surface of the copper foil 5 was measured by a surface roughness measuring device. As shown in Fig. 8, in general, the arithmetic mean roughness Ra specified by JIS B0601 is 〇·4μιη, and the average length RSm of the thickness curve element specified by JIS B0601 is 0.8 μm. As shown in (c), in general, the photoresist film 2 is formed on the surface of the roughened copper foil 5. Among the photoresists, V-259PA manufactured by Nippon Steel Chemical Co., Ltd. was used. The thickness of the photoresist film is ΐ〇μπ1. As shown in Fig. 2 (d), a recess 2a having a diameter of 20 to 200 μm is formed at the photoresist film 2 at a position where the interlayer connection via holes are to be arranged, as shown in Fig. 2 (d). As shown generally in Fig. 2(e), a first metal layer 3 which is a substrate for electroplating is formed. The metal layer 3' is formed on the surface of the substrate, that is, in the recess 3b and in the region 3c other than the recess 3b. In the present example -16-200917921, the first metal layer 3 is a nickel film formed by electroless nickel plating. In the electroless nickel plating solution, TOPCHEMIALLOY 66 manufactured by Okuno Pharmaceutical Co., Ltd. is used. The film thickness of nickel is 200 nm. After the first metal layer 3 was formed, the surface roughness of the concave portion 3b and the surface roughness of the region 3c other than the concave portion 3b were measured via the surface roughness measuring device. The surface roughness in the concave portion 3b is the same as the surface roughness of the surface of the substrate 1 measured after the roughening treatment. Further, in the region 3c other than the concave portion 3b, the arithmetic mean roughness Ra defined by JIS B0601 is 0.002 μm, and the average length RSm of the thickness curve element specified by JIS B0 60 1 is 27 μm. As shown in Fig. 2(f), the second metal layer 4 is formed via copper ore. The second metal layer 4 is a copper plating film. The plating conditions are as shown in Fig. 8. Further, the plating time was 10 minutes, the current density was 1 · 0 Α / dm 2 , and the temperature of the plating solution was 25 ° C. As shown in Fig. 2(g), the first metal layer 3 on the surface of the photoresist film 2, that is, the nickel film is removed. The removal of the nickel film was carried out in the same manner as in Example 1. In this way, in the second embodiment, the surface of the photoresist film 2, that is, the removal of the copper plating film at the region 3c other than the recess 3b is unnecessary, and has a diameter of 20 to 2 0. It is easy to manufacture a wiring board in which a via of 0 μm is connected to a via. [Embodiment 3] With reference to Fig. 3, a method of forming an interlayer connection via hole by the present invention will be described -17-200917921. Here, Embodiment 3 of the inventor of the present invention will be described. In the third embodiment, the same procedure as in the second embodiment is carried out except that the roughening process of the copper box is performed after the formation of the resist recess. As shown in Fig. 3 (a), as a substrate, a polyimide film of a thickness (KAPTON EN manufactured by TORAY. DUPONT Co., Ltd.) was prepared, and a copper foil having a thickness of 12 μm was attached to the surface thereof. 5. As shown generally in Fig. 3(b), a photoresist film 2 is formed on the surface of the copper foil 5. Among the photoresists, V-259® manufactured by Nippon Steel Chemical Co., Ltd. was used. The thickness of the photoresist film is ΙΟμιη. As shown in Fig. 3 (c), a concave portion 2a having a diameter of 20 to 200 μm is formed at the photoresist film 2 at a position where the interlayer connection via holes are to be arranged, as shown in Fig. 3 (c). As shown in Fig. 3 (d), the surface of the copper foil 5 is roughened. That is, the copper foil 5 exposed at the concave portion 2a of the photoresist film 2 is roughened. The roughening treatment was the same as in Example 1. From Fig. 3(e) to Fig. 3(g), the same as from Fig. 2(e) to Fig. 2(g). That is, as shown in Fig. 3 (e), the first metal layer 3 which is the base of electroplating is formed. As shown in Fig. 3 (f), the second metal layer 4 is formed by copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in Figure 8. After the copper plating, the wiring profile was observed. As shown in Fig. 6, the thickness of the copper plating film in the recess 3b is set to T2. In the third embodiment, the copper plating film thickness T2 in the concave portion 3b is 1 μm. Further, the thickness of the copper plating film T3 in the region 3c other than the recess 3b in -18-200917921 is Ο.ΟΟΙμηι or less. Therefore, in the third embodiment, it is understood that the copper plating film is selectively grown in the concave portion 3b on the substrate, and the region 3c other than the concave portion 3b, that is, on the surface of the substrate, the copper system is hardly Will precipitate. As shown in Fig. 3(g), the first film of the first layer of the photoresist film 2 is removed, that is, the nickel film is removed. As described above, in the third embodiment, the removal of the copper plating film on the surface of the photoresist film 2, that is, the region 3c other than the concave portion 3b is unnecessary, and has a diameter of 2 〇 to 2 00 μπι. It is easy to manufacture a wiring board in which vias are connected between layers. [Embodiment 4] A method of forming a wiring according to the present invention will be described with reference to Fig. 4 . Here, Embodiment 4 of the inventor of the present invention will be described. As shown in Fig. 4 (a), a polyimide film (UP ILEX manufactured by Ube Industries, Ltd.) having a thickness of 5 μm was prepared as the substrate 1. As shown in Fig. 4 (b), at the surface of the substrate 1, a pseudo-molecular laser is used, and a groove 1 a having a depth of 7 μm and a width of 7 to 100 μm is formed along the wiring pattern. The surface roughness in the groove 1 a of the substrate 1 was measured by a surface roughness measuring device. As shown in Fig. 8, in general, the arithmetic mean roughness Ra specified by JIS B060 1 is 〇_〇5μηι, and the average length RSm of the thickness curve element specified by jlSB〇6〇l is 0.2. Ιιη. As shown in Fig. 4(c), the first metal layer 3 is formed by sputtering. The metal layer 3 is formed on the surface of the substrate, that is, it is formed in the region 3 c outside the groove 3 a and the groove 3 a from -19 to 200917921. The first metal layer is a nickel film containing 25% chromium. The thickness of the film is 1 〇〇 nm. After the first metal layer 3 is formed, the surface roughness in the groove 3 a and the surface of the region 3 c other than the groove 3 a are thickened by the surface roughness measuring device. The degree was measured. The surface roughness in the groove 3a is the same as the surface roughness before the formation of the first metal layer 3. Further, in the region 3c other than the groove 3a, the arithmetic mean roughness Ra' defined by JIS B060 1 is Ο.ΟΟΙμιη, and the average length RS m ' of the thickness curve element defined by JIS B0601 is 3 4 μ m. As shown in Fig. 4 (d), the second metal layer 4 is formed by copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in Fig. 8. Further, the plating time was 5 minutes, the current density was 2.0 A/dm2, and the temperature of the plating solution was 25 °C. After the copper plating, the wiring profile was observed. In the fourth embodiment, the copper plating film thickness T1 in the groove 3a is 7 μm. Further, the thickness of the copper plating film T3 in the region 3c other than the groove 3a is 0.001 μm or less. Therefore, in Example 4, it can be known that the copper plating film is selectively grown in the groove 3a on the substrate, and the region 3c other than the groove 3a, that is, on the surface of the substrate, copper The system will hardly precipitate. As shown in Fig. 4(e), the first metal layer 3' on the surface of the substrate 1 is removed, that is, the nickel film is removed. In the removal of the nickel film, CH-1935 manufactured by MEC Corporation was used. A small amount of the copper plating film formed on the surface of the photoresist can be removed simultaneously with the nickel film. Thus, in the fourth embodiment, the surface of the substrate 1, that is, the removal of the copper plating film at the region 3c other than the groove 3a of -20-200917921 is unnecessary, and has a depth of 7 μm and a width. The manufacture of a wiring board having a copper wiring of 7 to 100 mm is easy. [Embodiment 5] With reference to Fig. 5, a method of forming a via hole between wiring layers according to the present invention will be described. Here, Embodiment 5 of the inventor of the present invention will be described. As shown in Fig. 5 (a), as the substrate 1, a polyethylene terephthalate film (TEFLEX manufactured by Teijin Dupont Films Co., Ltd.) having a thickness of ΙΟΟμηη was used. This film contains a copper foil 5. As shown in FIG. 5(b), a groove 5 having a depth of 5 μm and a width of 5 to ΙΟΟμηη is formed at the surface of the substrate 1 by using a nanoimprint process using a nickel mold 6 while being in the groove. At the bottom of the 7th, a recess 8 having a depth of 5 μm and a diameter of 5 μm is formed. The groove 7 is formed along the wiring pattern, and the concave portion 8 is formed at a position where the interlayer connection via hole is to be disposed. After the nanoimprinting treatment, the surface roughness of the grooves 7 and the recesses 8 was measured by a surface roughness measuring device. As shown in Fig. 8, in general, the arithmetic mean roughness Ra specified by JIS B060 1 is 0.4 μm, and the average length RSm of the thickness curve elements specified by JIS B 0 60 1 is 1.1 μm. As shown in Fig. 5 (c), the resin at the bottom of the concave portion 8 is removed by etching and the copper foil 5 is exposed. As shown in Fig. 5 (d), the surface of the exposed copper foil 5 was roughened. The roughening -21 - 200917921 was the same as in the first embodiment. After the roughening treatment, the surface roughness of the exposed copper foil 5 was measured by a surface roughness measuring apparatus. As shown in Fig. 8, in general, the arithmetic mean roughness Ra specified by JIS B 060 1 is 〇·4μιη, and the average length RSm of the thickness curve elements specified by JIS B060 1 is 1 · 1 μm As shown in Fig. 5(e), the i-th metal layer 3 is formed by sputtering. The metal layer 3 is formed on the surface of the substrate, that is, in the groove 3b and the region 3c in the recess 3a and beyond. The first metal layer 3 of Example 5 was a titanium film having a film thickness of 50 nm. After the first metal layer 3 was formed, the surface roughness of the recess 3a, the groove 3b, and the region 3c other than the groove 3a was measured via the surface roughness measuring device. The surface roughness of the copper foil of the groove 3b and the recess 3a is the same as the surface roughness measured before the formation of the first metal layer 3. Further, in the region 3c other than the groove portion and the concave portion, that is, on the surface of the substrate, the arithmetic mean roughness Ra defined by JIS B0601 is Ο.ΟΟΙμιη, and the average of the roughness curve elements specified by JIS B0601 The length RSm is 30 μm. As shown in Fig. 5 (f), the second metal layer 4 is formed via copper ore. The second metal layer 4 is a copper plating film. The plating conditions are as shown in Fig. 8. Further, the plating time was 20 minutes, the current density was 0.5 A/dm 2 , and the temperature of the plating solution was 25 °C. After the copper plating, the wiring profile was observed. In the fifth embodiment, the thickness of the copper plating film T1 in the groove 3a is 5 μm, and the thickness of the copper plating in the recess -22-200917921 is 12, which is 10 μm. The copper plating film thickness Τ3 at the surface of the substrate other than the nanoimprint processing portion is as follows. Therefore, in the fifth embodiment, it can be seen that the groove 3a on the copper plating substrate is selectively grown, and in the groove 3a at 3c, that is, on the surface of the substrate, the copper system hardly precipitates. As shown in Fig. 5 (g), the surface of the substrate 1 is submerged, that is, the nickel film is removed. In the removal of the nickel film, CH- 1 93 5 manufactured by MEC Corporation. Some of the plating film formed on the resistive surface can be removed simultaneously with the nickel film. As described above, in the fifth embodiment, the surface of the substrate 1 and the copper plating film at the region 3 c other than the groove 3 a are removed, and the copper having a depth of 5 μm and a width of 5 to 5 μm is provided. The manufacture of the wiring board which connects the vias between the layers is [Example 6] Referring again to Fig. 1, the formation of the wiring by the present invention will be apparent. Here, the embodiment 6 of the inventor of the present invention is shown in Fig. 1 (a). Generally, as the substrate 1, a liquid crystal polymer film of thickness 〇 && \Company system 81 (:) As shown in Fig. 1 (b), the surface of the substrate 1 is surface-treated. In the roughening treatment, a sandblasting treatment in which aluminum fine particles are placed on the surface of the substrate 1 is used. After the roughening treatment, the surface roughness of the surface was measured by the surface roughness measuring device. As shown in Fig. 8, a region of 0.00 1 μm film is used in the outer region. The first gold system uses copper electricity, which is unnecessary, and the wire is straight and easy. The method is explained. For example, after 50 μm, the rough sample is attached to the substrate 1, and the arithmetic mean roughness Ra specified by -23-200917921 JISB060 1 is 0.6 μm, which is the thickness specified by JIS B060 1 The average length RSm of the curved elements is 1 · 5 μ m. As shown in Fig. 1 (c), the photoresist film 2 is formed on the surface of the substrate 1 after roughening. Among the photoresists, RY-3219 manufactured by Hitachi Chemical Co., Ltd. is used. The thickness of the photoresist film is 5 μm. As shown in Fig. 1 (d), a wide 5~ΙΟΟμηι groove 2a is formed at the photoresist film 2 by photolithography. As shown in Fig. 1(e), a first metal layer 3 which is a substrate for electroplating is formed. The first metal layer 3 is a copper film formed by electroless plating. In the electroless plating solution, CUST-201 manufactured by Hitachi Chemical Co., Ltd. is used. The film thickness of copper is 100 nm. After the first metal layer 3 was formed, the surface roughness of the groove 3a and the surface roughness of the region 3c other than the groove 3a were measured by the surface roughness measuring device. The surface roughness in the groove 3a is the same as the surface roughness of the surface of the substrate 1 measured after the roughening treatment. Further, in the region 3c other than the groove 3a, the arithmetic mean roughness Ra defined by JIS B0601 is Ο.ΟΟΙμιη, and the average length RSm of the thickness curve element specified by JIS B0 60 1 is 3 1 Ιιη. As shown in Fig. 1 (f), the second metal layer 4 is formed by copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in Fig. 8. Further, the plating time was 10 minutes, the current density was 1 · 0 Α / dm 2 , and the temperature of the plating solution was 25 ° C. After the copper plating, the wiring profile was observed. In the sixth embodiment, -24-200917921, the copper plating film thickness T1 in the groove 3a is ΙΟμιη. Further, the thickness of the copper ore film Τ3' in the region 3c outside the groove 33 is Ο.ΟΟίμιη or less. Therefore, in the sixth embodiment, it can be known that the 'copper plating film is selectively grown in the groove 3a on the substrate, and the region 3c other than the groove 3a, that is, on the surface of the substrate, copper The system will hardly precipitate. As shown in Fig. 1(g), the first metal layer 3 on the surface of the photoresist film 2, that is, the copper film is removed. In the removal of the copper film, CH-1935 manufactured by MEC Corporation was used. In the removal of the nickel film, the MECBRITE VE-7100 series manufactured by MEC Corporation was used. A small amount of the copper plating film formed on the photoresist surface can be removed simultaneously with the nickel film. As described above, in the sixth embodiment, the surface of the photoresist film 2, that is, the removal of the copper plating film at the region 3c other than the groove 3a is unnecessary, and has a depth of 1 μm and a width of 5 It is easy to manufacture the wiring board of the copper wiring of ~ΙΟΟηηι. [Embodiment 7] Referring again to Fig. 1, a method of forming a wiring by the present invention will be described. Here, Embodiments 7 and 8 of the inventors of the present invention will be described. In Examples 7 to 8, the types of the additives, the concentration of the additives, and the current density of the electric ore were different from those of Example 1, but the same as Example 1 except for the above. The plating conditions are as shown in Fig. 8. After the copper plating, the wiring profile was observed. In Examples 7 and 8, the copper plating film thickness Τ1 in the groove 3a was ΙΟμηη. Further, the thickness of the copper plating film 3 at the region 3c other than the groove -25-200917921 3 a is 0.00 1 μm or less. Therefore, in Examples 7 and 8, it can be seen that the copper plating film is selectively grown in the groove 3a on the substrate, and the region 3c other than the groove 3a, that is, on the surface of the substrate, The copper system hardly precipitates. As described above, in the seventh and eighth embodiments, the surface of the resist film 2, that is, the removal of the copper plating film at the region 3c other than the groove 3a is unnecessary, and has a depth of ΙΟμηι and a width. The manufacture of a wiring board having a copper wiring of 7 to ΙΟΟμπι is easy. [Comparative Example 1] Comparative Example 1' was the same as Example 1 except that the plating solution did not contain an additive. The plating conditions are as shown in Fig. 8. After the copper plating, the wiring cross section was observed. In the comparative example, the copper plating film thickness Τ 1 in the groove 3 a was 2 · 1 μ m. Further, the thickness of the copper plating film T3 in the region 3c other than the groove 3a is 2·2 μm. In the comparative example, the copper electro-mineral film grows almost uniformly in the region 3c other than the groove 3a on the substrate and the groove 3a. That is, it can be seen that copper having almost the same thickness as the groove 3a is deposited on the surface of the substrate. In the comparative example, the surface of the photoresist film 2, that is, the removal of the copper plating film at the region 3c other than the groove 3a is necessary, and has a depth of 10 μm and a width of 7 to 1 0. The manufacture of a wiring board of 0 μm copper wiring is difficult. Although the examples of the present invention have been described above, the present invention is not limited to the above examples, and if it is a practitioner, it should be easy to understand the scope of the invention described in the scope of the patent application -26-200917921. Various changes can be made. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] A diagram for explaining a method of forming wirings according to the present invention. Fig. 2 is a view showing a method of forming a via hole for interlayer connection by the present invention. Fig. 3 is a view showing a method of forming a via hole for interlayer connection by the present invention. Fig. 4 is a view for explaining a method of forming a wiring by the present invention. Fig. 5 is a view for explaining the wiring of the present invention and the method of forming the interlayer connection via. Fig. 6 is a cross-sectional view showing the evaluation position of the copper ore film thickness of the wiring and the interlayer connection via plate of the present invention. Fig. 7 is a view for explaining characteristics of a plating solution caused by the present invention. Fig. 8 is a view showing the plating conditions of the embodiment of the wiring of the present invention and the method of forming the interlayer connection via. [Description of main component symbols] 1 : Substrate 2 : Photoresist 3 : First metal layer (base) 4 : Second metal layer (copper plating film) 5 : Copper foil -27 - 200917921 6 : Mold 7 : Groove 8 : Concave -28