US20090057156A1

US20090057156A1 - Production method for wiring and vias

Info

Publication number: US20090057156A1
Application number: US12/190,610
Authority: US
Inventors: Toshio Haba; Haruo Akahoshi; Hitoshi Suzuki; Akira Chinda
Original assignee: Hitachi Cable Ltd
Current assignee: Hitachi Cable Ltd
Priority date: 2007-08-30
Filing date: 2008-08-13
Publication date: 2009-03-05
Also published as: CN101378632B; CN101378632A; TW200917921A; TWI358980B; JP2009057582A; JP4682285B2; KR101030688B1; KR20090023126A

Abstract

It is an object of the present invention to alleviate a work for removing an unnecessary metal layer when wiring and vias are formed on a substrate by electroplating.

An additive is added to a plating solution to be used for electroplating. The additive has a plating reaction suppressing capability, but has a characteristic that the plating reaction suppressing capability is reduced as the plating reaction progresses. The additive has a capability for increasing a metal deposition overpotential and has a characteristic that the metal deposition overpotential is reduced as the reaction progresses. As a result, the metal can be deposited selectively in a trench and a via formed on the substrate. When a wiring and a via are formed on the substrate, the trench and the via having a predetermined surface roughness are formed on the substrate.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a technique which produces fine wiring and vias on a substrate by means of electroplating.
2. Description of the Related Art
A demand for miniaturization of a wiring pitch of copper wiring to 20 or less μm has strongly increased also in chip-on-films (COF) and semiconductor package substrates due to downsizing of electronic devices. It has been difficult to keep good ion migration resistance according to the progress in the miniaturization of the wiring pitch.
In recent years, as a method for producing fine wiring and via holes (vias) on a substrate, an electroplating method has been used. The electroplating method has advantages such as lower cost, higher throughput and more excellent mass productivity than a physical vapor deposition (PVD) method and a chemical vapor deposition (CVD) method. Various known methods for producing wiring and vias on a substrate using the electroplating include a Damascene method. In the Damascene method, first of all trenches and vias are formed on a substrate using a suitable method. The trenches and vias, which are concave section, are produced in a shape corresponding to a wiring pattern and via holes, and are formed on a position where a wirings and via holes should be arranged. Next, metal is deposited on the surface of the substrate by electroplating. The deposited metal fills the trenches and the vias. The deposited metal which fills the trench and the vias forms wirings and via holes.
Japanese Patent Application Laid-Open No. 2006-210565
Japanese Patent Application Laid-Open No. 2006-206950
Japanese Patent Application Laid-Open No. 2002-155390
The metal deposited by electroplating, however, covers not only the trenches and the vias on the substrate but also portions other than the trench and the vias After the electroplating is carried out, therefore, a process of removing an unnecessary metal layer is necessary. This metal removing process called chemical mechanical polishing (CMP). CMP process is complicated and high cost because it is difficult to accurately remove this unnecessary metal layer.

SUMMARY OF THE INVENTION

It is an object of the present invention to alleviate a work for removing an unnecessary metal layer when wiring and vias are produced on a substrate by electroplating.
According to the present invention, an additive is added to a plating solution to be used for electroplating. The additive has a plating reaction suppressing capability and has a characteristic that the plating reaction suppressing capability is reduced as the plating reaction progresses. As a result, metal can be deposited selectively in a trench and a via formed on the substrate.
According to the present invention, in a polarization curve of the plating solution to be used for the electroplating, when an electric potential shifts a first electric potential E1 to a more negative second electric potential E2 at 1000 rpm of rotational speed, a current density abruptly increases. In a potential region between the first electric potential E1 and the second electric potential E2, the polarization curve at 1000 rpm crosses the polarization curve at the 0 rpm.
According to the present invention, when a wiring and a via are formed on the substrate by a Damascene method, a trench and a via having a predetermined surface roughness are formed on the substrate.
According to the present invention, when the wiring and the via hole are formed on the substrate by electroplating, a work for removing an unnecessary metal layer can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1G are diagrams explaining a production method for wiring according to the present invention;

FIGS. 2A to 2G are diagrams explaining a production method for vias according to the present invention;

FIGS. 3A to 3G are diagrams explaining the production method for the vias according to the present invention;

FIGS. 4A to 4E are diagrams explaining the production method for wiring according to the present invention;

FIGS. 5A to 5G are diagrams explaining the production method for the wiring and the vias according to the present invention;

FIG. 6 is a cross-sectional view illustrating evaluation positions of copper plated film thicknesses of the wiring and a via plate according to the present invention;

FIG. 7 is a diagram explaining a characteristic of a plating solution according to the present invention; and

FIG. 8 is a diagram illustrating plating conditions of the production method for the wiring and the vias according to examples of the present invention.

DESCRIPTION OF REFERENCE NUMERALS

1: substrate
2: resist
3: first metal layer (seed layer)
4: second metal layer (copper plating film)
5: copper foil
6: mold
7: trench
8: via

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An outline of the present invention is described. According to the present invention, an additive is added to a plating solution to be used for electroplating. An acid copper sulfate solution may be used as the plating solution. The acid copper sulfate solution to be used for the electroplating is publicly known, and its details are not described here. When the acid copper sulfate solution is used, wiring and via holes are produced by copper. Wiring and via holes may be produced by metal other than copper. For example, nickel, aluminum and the like can be used. In this case, a metal solution whose metal is a raw material of the wiring and the vias is used as the plating solution. Metal to be used for a conductive layer as a seed layer for the electroplating may be copper, but other metals than copper, such as nickel, cobalt, chromium, tungsten, palladium, titanium and metal alloy containing at least one of these metals may be used.
According to the present invention, the additive has a capability for suppressing plating reaction, but has a characteristic such that the plating reacting suppressing capability is reduced as the plating reaction progresses. Any additive may be used as long as it has such a capability and a characteristic. Inventors of this application find out that cyanine dye and its derivative have such a capability and a characteristic. The cyanine dye is expressed by the following formula, where n is any one of 0, 1, 2 and 3.
As the additive to be used for copper plating, a substance which seppress the plating reaction and loses a plating reaction suppressing effect simultaneously with the progression of the plating reaction is suitable. The effect of the additive for suppressing the plating reaction can be checked by seeing if deposition overpotential of metal becomes higher when the additive is added to the plating solution. The effect that the additive loses the plating reaction suppressing effect simultaneously with the progression of the plating reaction can be checked by the fact that as a flow rate of the plating solution is higher, the deposition overpotential of the metal to be plated becomes higher. This means that as a supply speed of the additive to a first metal layer surface is higher, the plating reaction suppressing effect becomes higher. When the additive loses the plating reaction suppressing effect, the additive is decomposed and is changed into another substance or is reduced so as to be changed into a substance having a different oxidation number.
The reason why plating can be deposited in the concave section (the trench and the via) approximately selectively by carrying out plating using the plating solution containing such an additive is described below. When plating is carried out by using such an additive, the additive loses its effect on the surface of the first metal layer simultaneously with the progression of the plating reaction. As a result, an effective additive concentration relating to the plating reaction is reduced on the surface of the first metal layer. When the concentration of the additive is reduced, the additive is supplied by diffusion from the solution. At this time, the reduction speed of the additive concentration differs between the concave section and the substrate surface. Since unevenness is formed on the first metal layer in the concave section, its surface area is comparatively larger than that of the substrate surface. Therefore, the reduction speed of the additive concentration is high in the concave section. A distance from an bulk plating solution in the concave section is longer than that in the substrate surface. Therefore, the supply of the additive is slow in the concave section, and the increase speed of the additive concentration due to diffusion is low. For this reason, a state that its additive concentration is lower than that in the substrate surface is maintained in the concave section. Since this additive has the plating reaction suppressing effect, the plating reaction in the concave section where the additive concentration is low is not suppressed, and a plating film can be grown selectively in the concave section.
In the plating solution having such a characteristic, it is preferably that a rotating disk electrode has a potential area where a current value at 1000 rpm is 1/100 or less than that at the time of rest in a polarization curve obtained by measurement on the rotating disk electrode. In such a plating solution, as shown in FIG. 7, current density B at 1000 rpm is 1/100 or less than current density A at 0 rpm at a certain electric potential E′.
The plating solution having such a polarization curve enables metal to be deposited selectively in the trench and the via on the substrate.
According to the present invention, wiring and via holes are produced on the substrate by the Damascene method. Surface roughness in the trench and the via formed on the substrate is described together with the Damascene method. As a guidepost of the roughness, arithmetic average roughness Ra defined by JISB0601, and an average length RSm of a roughness curvilinear element defined by JISB0601 are known. According to the Damascene method, a trench and a via are formed on the substrate by a suitable method. The trench is formed in a shape corresponding to a wiring, and the via is formed on a position where the via holes are arranged. According to the present invention, the trench and the via are formed so as to have a predetermined surface roughness. The first metal layer as a seed layer for electroplating is formed on the substrate with the trench and the via formed thereon. A second metal layer is formed on the substrate surface by electroplating.
Before the electroplating is carried out, the surface roughness of the substrate with the first metal layer formed thereon was measured. As a result, the arithmetic average roughness Ra is 0.01 to 4 μm, and preferably 0.01 to 1.0 μm, in the trench and the via. The average length RSm of the rough curvilinear element is 0.005 to 8 μm, and preferably 0.01 to 2.0 μm. The arithmetic average roughness Ra on the area other than the trench and the via, namely, the substrate surface is preferably 0.001 to 0.002 μm. The average length RSm of the roughness curvilinear element is 10 to 50 μm, and preferably 20 to 40 μm.
The arithmetic average roughness Ra in the trench and the concave section is larger than the arithmetic average roughness Ra of the area other than the trench and the concave section, namely, the substrate surface. The arithmetic average roughness Ra in the trench and the via is ten or more times as large as the arithmetic average roughness Ra of the area other than the trench and the via. The average length RSm of the roughness curvilinear element in the trench and the via is smaller than the average length RSm of the roughness curvilinear element on the area other than the trench and the via, namely, the substrate surface. The average length RSm of the roughness curvilinear element in the trench and the via is 1/10 or less of the average length RSm of the roughness curvilinear element on the area other than the trench and the via.
The surface roughness in the trench and the via on the substrate hardly changes before and after the first metal layer is formed. Therefore, by forming the trench and the via having a desired surface roughness on the substrate previously, the trench and the via having a desired surface roughness can be obtained after the first metal layer is formed.
The trench and the via having a desired surface roughness are formed on the substrate, and the first metal layer is formed thereon. Further, the electroplating is carried out by using the plating solution to which the additive is added according to the present invention, so that metal can be precipitated selectively in the trench and the via on the substrate. The metal is not deposited on the area of the substrate other than the trench and the via, namely, the substrate surface. Therefore, the work for removing the metal deposited on the substrate surface can be alleviated. The present invention can be applied to formation of a copper wiring and a through silicon via technology in 3D packages.
An example of the electroplating carried out by the inventors of this application is described below. The inventors of this application conducted experiments of the electroplating in examples 1 to 8 and a comparative example 1. The examples 1 to 8 are electroplating experiments using the plating solution of the present invention to which the additive is added. The comparative example 1 is the electroplating experiment using a conventional plating solution. The plating solution was prepared by adding sulfuric acid with a concentration of 180 g/dm³to copper sulfate pentahydrate with a concentration of 150 g/dm³. The additive of the present invention was added to this plating solution so that the plating solution of the present invention was prepared.
FIG. 8 illustrates experimental conditions and experimental results of the examples 1 to 8 and the comparative example 1. Symbols described in a column of additive type represent the following chemical substances.

A-1:
2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-methyl]-1,3,3-trimethyl-3H-indolium perchlorate
A-2:
2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indolium chloride
A-3:
2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indolium iodide
A-4:
2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indolium iodide
B: 3-Ethyl-2-[5-(3-ethyl-2(3H)-benzothiazolylidene)-1,3-pentadienyl]benzothiazolium iodide
C: Janus Green B

The arithmetic average roughness Ra defined by JISB0601 and the average length RSm of the roughness curvilinear element defined by JISB0601 are measured values of the surface roughness in the trench and the via on the substrate, which values were measured after the first metal layer being formed.

EXAMPLE 1

A production method for the wiring according to the present invention is described with reference to FIGS. 1A to 1G. The example 1 by the inventors of this application is described. As shown in FIG. 1A, a polyimide film (Kapton EN made by DuPont-Toray Co., Ltd.) having a thickness of 25 μm was prepared as the substrate 1.
As shown in FIG. 1B, the surface of the substrate 1 was subject to a surface roughening treatment. A sandblast treatment for spraying alumina fine particulates to the surface of the substrate 1 was used for the surface roughening treatment. One of a chemical surface roughening treatment, an electric surface roughening treatment and a mechanical surface roughening treatment, or their combinations may be used as the surface roughening treatment. The chemical surface roughening treatment includes an alkali etching treatment using an alkali solution such as a NaOH aqueous solution, an oxidation treatment using acid salt such as permanganate, bichromate, persulfate, hypochlorite, chlorite or chlorate, and etching using hydrazine. The electric surface roughening treatment includes a plasma treatment in vacuum, a corona treatment in the atmosphere, and like. The mechanical roughening treatment includes brushing using a wire brush, and like.
After the surface roughening treatment, the surface roughness on the surface of the substrate 1 was measured by a surface roughness measuring device. As shown in FIG. 8, the arithmetic average roughness Ra defined by JISB0601 was 0.4 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 1.1 μm.
As shown in FIG. 1C, a resist film 2 was formed on the roughened surface of the substrate 1. V-259PA made by Nippon Steel Chemical Co., Ltd. was used as the resist. As the resist, RY-3219 made by Hitachi Chemical Co., Ltd., or SPG-202 made by Asahikasei EMD corporation can be used. The thickness of the resist film was 10 μm.
As show in FIG. 1D, trenches 2 a with widths of 7 to 100 μm were formed along the wiring pattern on the resist film 2 by a photolithography method.
As shown in FIG. 1E, a first metal layer 3 as a seed layer for electroplating was formed. The metal layer 3 was formed on the substrate surface, namely, in the trenches 3 a and on areas 3 c other than the trenches 3 a. In this example, the first metal layer 3 is a nickel film formed by electroless nickel plating. As an electroless nickel plating solution, TOP CHEMI ALLOY 66 made by Okuno Chemical Industries was used. The film thickness of the nickel was 200 nm. As the seed layer forming method, not only the electroless nickel plating method but also an evaporation method, a sputtering method or a chemical vapor deposition (CVD) method may be used. As the first metal layer, not only the nickel film but also a chromium film, a tungsten film, a palladium film or a titanium film, or their alloy film can be used.
After the first metal layer 3 was formed, the surface roughness in the trenches 3 a and the surface roughness of the areas 3 c other than the trenches 3 a were measured by the surface roughness measuring device. The surface roughness in the trenches 3 a were the same as the surface roughness on the surface of the substrate 1 measured after the surface roughening treatment. The arithmetic average roughness Ra defined by JISB0601 was 0.001 μm, and average length RSm of the roughness curvilinear element defined by JISB0601 was 34 μm on the areas 3 c other than the trenches 3 a.
As shown in FIG. 1F, a second metal layer 4 was formed by electrolytic copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in FIG. 8. Plating time was 10 minutes, current density was 1.0 A/dm², and temperature of the plating solution was 25° C.
After the electrolytic copper plating, a wiring cross-section was observed. As shown in FIG. 6, the thickness of the copper plating film in the trenches 3 a is represented by T1, and the thickness of the copper plating film on the areas 3 c other than the trenches 3 a is represented by T3. In the example 1, the thickness T1 of the copper plating film in the trenches 3 a was 10 m. The thickness T3 of the copper plating film on the areas 3 c other than the trenches 3 a was not more than 0.001 μm. In the example 1, therefore, it was found that the copper plating film grew selectively in the trenches 3 a on the substrate, but that the copper was hardly precipitated on the areas 3 c other than the trenches 3 a, namely, the substrate surface.
As shown in FIG. 1G, the first metal layer 3 on the surface of the resist film 2, namely, the nickel film was removed. CH-1935 made by MEC was used for removing the nickel film. Melstrip made by Meltex, Inc., or SEEDLON process made by Ebara-Udylite may be used for removing the nickel film. A slight copper plating film formed on the surface of the resist film 2 could be removed simultaneously with the nickel film.
In the example 1, the surface of the resist film 2, namely, the copper plating film on the areas 3 c other than the trenches 3 a does not have to be removed, and thus the production of a wiring plate having a copper wiring with a depth of 10 μm and widths of 7 to 100 μm became easy.

EXAMPLE 2

The production method for the vias according to the present invention is described with reference to FIGS. 2A to 2G. Example 2 by the inventors of this application is described. As shown in FIG. 2A, a polyimide film with a thickness of 25 μm (Kapton EN made by DuPont-Toray Co., Ltd.) was prepared as the substrate 1, and a copper foil 5 with a thickness of 12 μm was stuck to its surface.
As shown in FIG. 2B, the surface of the copper foil 5 was subject to the surface roughening treatment. The surface roughening treatment is similar to that in the example 1.
After the surface roughening treatment, the surface roughness of the copper foil 5 was measured by the surface roughness measuring device. As shown in FIG. 8, the arithmetic average roughness Ra defined by JISB0601 was 0.4 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 0.8 μm.
As shown in FIG. 2C, the resist film 2 was formed on the roughened surface of the copper foil 5. V-259PA made by Nippon Steel Chemical Co., Ltd. was used as the resist. The thickness of the resist film was 10 μm.
As shown in FIG. 2D, concave sections 2 a with diameters of 20 to 200 μm were formed on positions on the resist film 2 where the vias should be arranged, by the photolithography method.
As shown in FIG. 2E, the first metal layer 3 as a seed layer for the electroplating was formed. The metal layer 3 was formed on the substrate surface, namely, in the concave sections 3 b and the areas 3 c other than the concave sections 3 b. In this example, the first metal layer 3 is a nickel film formed by electroless nickel plating. As an electroless nickel plating solution, TOP CHEMI ALLOY 66 made by Okuno Chemical Industries was used. The film thickness of the nickel was 200 nm.
After the first metal layer 3 was formed, the surface roughness in the concave sections 3 b and the surface roughness on the areas 3 c other than the concave sections 3 b were measured by the surface roughness measuring device. The surface roughness in the concave sections 3 b was the same as the surface roughness on the surface of the substrate 1 measured after the surface roughening treatment. The arithmetic average roughness Ra defined by JISB0601 was 0.002 μm and the average length RSm of the roughness curvilinear element defined by JISB0601 was 27 μm on the areas 3 c other than the concave section 3 b.
As shown in FIG. 2F, the second metal layer 4 was formed by electrolytic copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in FIG. 8. The plating time was 10 minutes, the current density was 1.0 A/dm², and the temperature of the plating solution was 25° C.
As show in FIG. 2G, the first metal layer 3 on the surface of the resist film 2, namely, the nickel film was removed. The nickel film was removed by the method similar to that in the example 1.
In the example 2, the removal of the copper plating film is not necessary on the surface of the resist film 2, namely, the areas 3 c other than the concave sections 3 b. As a result, the production of the wiring plate having the vias with diameters of 20 to 200 μm became easy.

EXAMPLE 3

The production method for the vias according to the present invention is described with reference to FIGS. 3A to 3G. The example 3 by the inventors of this application is described. The example 3 is similar to the example 2 except that the roughening treatment step for copper foil is executed after the resist concave section is formed. As shown in FIG. 3A, a polyimide film with a thickness of 25 μm (Kapton EN made by DuPont-Toray Co., Ltd.) was prepared as the substrate 1, and a copper foil 5 with a thickness of 12 μm was stuck to its surface.
As shown in FIG. 3B, the resist film 2 was formed on the surface of the copper foil 5. V-259PA made by Nippon Steel Chemical Co., Ltd. was used as the resist. The thickness of the resist film was 10 μm.
As shown in FIG. 3C, the concave sections 2 a with diameters of 20 to 200 μm were formed on positions on the resist film 2 where the vias should be arranged, by the photolithography method.
As shown in FIG. 3D, the surface of the copper foil 5 was subject to the surface roughening treatment. That is to say, the copper foil 5 exposed in the concave sections 2 of the resist film 2 was subject to the surface roughening treatment. The surface roughening treatment is similar to that in the example 1. FIGS. 3E to 3G are similar to FIGS. 2E to 2G. That is to say, as shown in FIG. 3E, the first metal layer 3 as a seed layer for electroplating was formed. As shown in FIG. 3F, the second metal layer 4 was formed by electrolytic copper plating. The second metal layer 4 is the copper plating film. The plating conditions are as shown in FIG. 8.
The wiring cross-section was observed after the electrolytic copper plating. As shown in FIG. 6, the copper plating film thickness in the concave sections 3 b is represented by T2. In the example 3, the copper plating film thickness T2 in the concave sections 3 b was 10 μm. The copper plating film thickness T3 on the areas 3 c other than the concave sections 3 b was not more than 0.001 μm. In the example 3, therefore, it was found that the copper plating film grew selectively in the concave sections 3 b on the substrate, and that the copper is hardly precipitated on the areas 3 c other than the concave sections 3 b, namely, on the surface of the substrate.
As shown in FIG. 3G, the first metal layer 3 on the surface of the resist film 2, namely, the nickel film was removed. In the example 3, the removal of the copper plating film is not necessary on the surface of the resist film 2, namely, the areas 3 c other than the concave sections 3 b. As a result, the production of the wiring plate having the vias with diameters of 20 to 200 μm became easy.

EXAMPLE 4

The production method for wiring according to the present invention is described with reference to FIGS. 4A to 4E. Example 4 by the inventors of this application is described. As shown in FIG. 4A, a polyimide film (UPILEX made by Ube Industries) with a thickness of 50 μm was prepared as the substrate 1.
As shown in FIG. 4B, the trenches 1 a with a depth of 7 μm and widths of 7 to 100 μm were formed along the wiring pattern on the surface of the substrate 1 by using excimer laser.
The surface roughness in the trenches 1 a on the substrate 1 was measured by the surface roughness measuring device. As shown in FIG. 8, the arithmetic average roughness Ra defined by JISB0601 was 0.05 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 0.2 μm.
As shown in FIG. 4C, the first metal layer 3 was formed by the sputtering method. The metal layer 3 was formed on the surface of the substrate, namely, in the trenches 3 a and on the areas 3 c other than the trenches 3 a. The first metal layer is a nickel film containing 25% of chromium. The film thickness was 100 nm.
After the first metal layer 3 was formed, the surface roughness in the trenches 3 a and the surface roughness on the areas 3 c other than the trenches 3 a were measured by the surface measuring device. The surface roughness in the trenches 3 a was the same as the surface roughness before the first metal layer 3 was formed. On the areas 3 c other than the trenches 3 a, the arithmetic average roughness Ra defined by JISB0601 was 0.001 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 34 μm.
As shown in FIG. 4D, the second metal layer 4 was formed by electrolytic copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in FIG. 8. The plating time was 5 minutes, the current density was 2.0 A/dm², and the temperature of the plating solution was 25° C.
The wiring cross-section was observed after the electrolytic copper plating. In the example 4, the thickness T1 of the copper plating film in the trenches 3 a was 7 μm. The thickness T3 of the copper plating film on the areas 3 c other than the trenches 3 a was not more than 0.001 μm. In the example 4, therefore, it was found that the copper plating film grew selectively in the trenches 3 a on the substrate, and that the copper was hardly precipitated on the areas 3 c other than the trenches 3 a, namely, on the substrate surface.
As shown in FIG. 4E, the first metal layer 3 on the surface of the substrate 1, namely, the nickel film was removed. CH-1935 made by MEC was used for removing the nickel film. A slight copper plating film formed on the resist surface could be removed simultaneously along with the nickel film.
In the example 4, the removal of the copper plating film on the surface of the substrate 1, namely, on the areas 3 c other than the trenches 3 a was not necessary. As a result, the production for the wiring plate having the copper wiring with a depth of 7 μm and widths of 7 to 100 μm became easy.

EXAMPLE 5

The production method for the wiring and the vias according to the present invention is described with reference to FIGS. 5A to 5G. The example 5 by the inventors of this application is described. As shown in FIG. 5A, a polyethylene terephthalate film with a thickness of 100 μm (TEFLEX made by Teijin DuPont Films) was used as the substrate 1. This film contains the copper foil 5.
As shown in FIG. 5B, a trench 7 with a depth of 5 μm and widths of 5 to 100 μm was formed on the surface of the substrate 1 by a nanoimprint treatment using a nickel die 6. At the same time, a concave section 8 with a depth of 5 μm and a diameter of 5 μm was formed on a bottom surface of the trench 7. The trench 7 was formed along the wiring pattern, and the concave section 8 was formed on a position where the vias should be formed.
After the nanoimprint treatment, the surface roughness of the trench 7 and the concave section 8 was measured by the surface roughness measuring device. As shown in FIG. 8, the arithmetic average roughness Ra defined by JISB0601 was 0.4 μm and the average length RSm of the roughness curvilinear element defined by JISB0601 was 1.1 μm.
As shown in FIG. 5C, the resin on the bottom of the concave section 8 was removed by etching, so that the copper foil 5 was exposed. As shown in FIG. 5D, the surface of the exposed copper foil 5 was subject to the surface roughening treatment. The surface roughening treatment is similar to that in the example 1.
After the surface roughening treatment, the surface roughness of the exposed copper foil 5 was measured by the surface roughness measuring device. As shown in FIG. 8, the arithmetic average roughness Ra defined by JISB0601 was 0.4 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 1.1 μm.
As shown in FIG. 5E, the first metal layer 3 was formed by the sputtering method. The metal layer 3 was formed on the surface of the substrate, namely, in the trench 3 b and the concave section 3 a and on the other areas 3 c. The first metal layer 3 in the example 5 was a titanium film, and its thickness was 50 nm.
After the first metal layer 3 was formed, the surface roughness in the concave section 3 a and the trench section 3 b and on the other areas 3 c was measured by the surface roughness measuring device. The surface roughness of the copper foil in the trench section 3 b and the concave section 3 a was the same as the surface roughness measured before the first metal layer 3 was formed. On the areas 3 c other than the trench section and the concave section, namely, the substrate surface, the arithmetic average roughness defined by JISB0601 was 0.001 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 30 μm.
As shown in FIG. 5F, the second metal layer 4 was formed by electrolytic copper plating. The second metal layer 4 was a copper plating film. The plating conditions are as shown in FIG. 8. The plating time was 20 minutes, the current density was 0.5 A/dm², and the temperature of the plating solution was 25° C.
The wiring cross-section was observed after the electrolytic copper plating. In the example 5, the thickness T1 of the copper plating film in the trench 3 a was 5 μm, the thickness T2 of the copper plating film in the concave section was 10 μm. The thickness T3 of the copper plating film on the areas which were not subject to the nanoimprint treatment, namely, the substrate surface was not more than 0.001 μm. Therefore, in the example 5, it was found that the copper plating film grew selectively in the trench 3 a on the substrate, and that the copper is hardly precipitated on the areas 3 c other than the trench 3 a, namely, the substrate surface.
As shown in FIG. 5G, the first metal layer 3 on the substrate 1, namely, the nickel film was removed. CH-1935 made by MEC was used for removing the nickel film. A slight copper plating film formed on the resist surface could be removed simultaneously along with the nickel film.
In the example 5, the removal of the copper plating film was not necessary on the surface of the substrate 1, namely, the areas 3 c other than the trench 3 a. As a result, the production of the wiring plate collectively having the copper wiring with a depth of 5 μm and widths of 5 to 100 μm and the vias with a diameter of 5 μm became easy.

EXAMPLE 6

The production method for wiring according to the present invention is described again with reference to FIGS. 1A to 1G. The example 6 by the inventors of this application is described. As shown in FIG. 1A, a liquid crystal polymer film with a thickness of 50 μm (BIAC made by Japan Gore-Tex, Inc.) was prepared as the substrate 1.
As shown in FIG. 1B, the surface of the substrate 1 was subject to the surface roughening treatment. A sandblast treatment which sprays alumina fine particles to the surface of the substrate 1 was used as the surface roughening treatment.
After the surface roughening treatment, the surface roughness on the surface of the substrate 1 was measured by the surface roughness measuring device. As shown in FIG. 8, the arithmetic average roughness Ra defined by JISB0601 was 0.6 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 1.5 μm.
As shown in FIG. 1C, the resist film 2 was formed on the surface of the roughened substrate 1. RY-3219 made by Hitachi Chemical Co., Ltd. was used as the resist. The thickness of the resist film was 5 μm.
As show in FIG. 1D, trenches 2a with widths of 5 to 100 μm were formed on the resist film 2 by the photolithography method.
As shown in FIG. 1E, a first metal layer 3 as a seed layer for electroplating was formed. The first metal layer 3 was a copper film formed by the electroless plating. CUST-201 made by Hitachi Chemical Co., Ltd. was used as an electroless plating solution. The film thickness of the copper was 100 nm.
After the first metal layer 3 was formed, the surface roughness in the trenches 3 a and the surface roughness on the areas 3 c other than the trenches 3 a were measured by the surface roughness measuring device. The surface roughness in the trenches 3 a was the same as the surface roughness on the surface of the substrate 1 measured after the surface roughening treatment. On the areas 3 c other than the trenches 3 a, the arithmetic average roughness Ra defined by JISB0601 was 0.001 μm, and the average length RSm of the roughness curvilinear element defined by JISB0601 was 31 μm.
As shown in FIG. 1F, the second metal layer 4 was formed by electrolytic copper plating. The second metal layer 4 is a copper plating film. The plating conditions are as shown in FIG. 8. The plating time was 10 minutes, the current density was 1.0 A/dm², and the temperature of the plating solution was 25° C.
The wiring cross-section was observed after the electrolytic copper plating. In the example 6, the thickness T1 of the copper plating film in the trenches 3 a was 10 μm. The thickness T3 of the copper plating film on the areas 3 c other than the trenches 3 a was not more than 0.001 μm. In the example 6, therefore, it was found that the copper plating film grew selectively in the trenches 3 a on the substrate, and that the copper was hardly precipitated on the areas 3 c other than the trenches 3 a, namely on the substrate surface.
As shown in FIG. 1G, the first metal layer 3 on the surface of the resist film 2, namely, the copper film was removed. CH-1935 made by MEC was used for removing the copper film. MECBRITE VE-7 100 series made by MEC was used for removing the nickel film. The slight copper plating film formed on the resist surface could be removed simultaneously along with the nickel film.
In the example 6, the removal of the copper plating film was not necessary on the surface of the resist film 2, namely, the areas 3 c other than the trenches 3 a. As a result, the production of the wiring plate having copper wiring with a depth of 10 μm and widths of 5 to 100 μm became easy.

EXAMPLE 7

The production method for wiring according to the present invention is described with reference to FIGS. 1A to 1G. The examples 7 and 8 by the inventors of this application are described. The type of additive, the concentration of the additive and the plating current density in the examples 7 and 8 are different from those in the example 1. However, all the other things are similar to those in the example 1. The plating conditions are as shown in FIG. 8.
The wiring cross-section was observed after the electrolytic copper plating. In the examples 7 and 8, the thickness T1 of the copper plating film in the trenches 3 a was 10 m. The thickness T3 of the copper plating film on the areas 3 c other than the trenches 3 a was not more than 0.001 μm. In the examples 7 and 8, therefore, it was found that the copper plating film grew selectively in the trenches 3 a on the substrate, and that the copper was hardly precipitated on the areas 3 c other than the trenches 3 a, namely, the substrate surface.
In the examples 7 and 8, the removal of the copper plating film was not necessary on the surface of the resist film 2, namely, on the areas 3 c other than the trenches 3 a. As a result, the production for the wiring plate having copper wiring with a depth of 10 μm and widths of 7 to 100 μm became easy.

COMPARATIVE EXAMPLE 1

Comparative example 1 is similar to the example 1 except that the plating solution does not contain an additive. The plating conditions are as shown in FIG. 8. The wiring cross-section was observed after the electrolytic copper plating. In the comparative example, the thickness T1 of the copper plating film in the trenches 3 a was 2.1 μm. The thickness T3 of the copper plating film on the areas 3 c other than the trenches 3 a was 2.2 μm. In the comparative example, the copper plating film grew approximately uniformly in the trenches 3 a on the substrate and on the areas 3 c other than the trenches 3 a. That is to say, it was found that the copper with approximately the same thickness as that in the trenches 3 a was precipitated on the substrate surface.
In the comparative example, the removal of the copper plating film on the surface of the resist film 2, namely, on the areas 3 c other than the trenches 3 a was necessary. As a result, the production for the wiring plate having copper wiring with a depth of 10 μm and widths of 7 to 100 μm became difficult.
The examples of the present invention were described, but the present invention is not limited to the above examples, and various modifications within the scope of the present invention described in claims can be easily understood by those skilled in the art.

Claims

1. A production method for wiring and vias, comprising:

trenches and vias forming step for forming trenches corresponding to a wiring on a surface of a substrate and forming a vias on a position where the via holes should be formed;

a seed layer forming step for forming a first metal layer as a seed layer for electroplating on the substrate surface with the trench and the via formed thereon; and an electroplating step for forming a second metal layer in the trench and the via by electroplating,

wherein an additive, which has a plating reaction suppressing capability and a characteristic such that the plating reaction suppressing capability is reduced as the plating reaction progresses, is added to a plating solution to be used at the electroplating step.

2. The production method for wiring and vias according to claim 1, wherein the additive contains at least one of cyanine dye and its derivatives which are expressed by the following formula:

where n is any one of 0, 1, 2 and 3.

3. The production method for wiring and vias according to claim 1, wherein the additive has a capability for increasing a metal deposition overpotential.

4. The production method for wiring and vias according to claim 1, wherein the plating solution has a characteristic that when a polarization curve representing a relationship between an electric potential of a disk electrode and a current density is obtained per rotational speed of the disk electrode, the current density at the time when the rotational speed of the disk electrode is 1000 rpm is lower than the current density at the time when the rotational speed of the disk electrode is zero in an area of a first electric potential, and the current density at the time when the rotational speed of the disk electrode is 1000 rpm is higher than the current density at the time when the rotational speed of the disk electrode is zero in an area of a second applied potential which is more negative than the first electric potential.

5. The production method for wiring and vias according to claim 1, wherein the plating solution has a characteristic that when a polarization curve representing a relationship between an electric potential of a disk electrode and a current density is obtained per rotational speed of the disk electrode, the current density at the time when the rotational speed of the disk electrode is 1000 rpm is not more than 1/100 of the current density at the time when the rotational speed of the disk electrode is zero in a range where the electric potential is +100 to 200 mV with respect to a standard hydrogen electrode potential, and the current density at the time when the rotational speed of the disk electrode is 1000 rpm is higher than the current density at the time when the rotational speed of the disk electrode is zero in a range where the electric potential is more negative than −100 mV with respect to the standard hydrogen electrode potential.

6. The production method for wiring and vias according to claim 1, wherein the plating solution is an acid copper sulfate solution, and the second metal layer is made by copper.

7. The production method for wiring and vias according to claim 1, wherein the first metal layer is formed by copper, nickel, cobalt, chromium, tungsten, palladium and titanium, or nickel, cobalt, chromium, tungsten, palladium and titanium, or alloy which contains at least one of them.

8. The production method for wiring and vias according to claim 1, wherein only the trench and the via are subject to surface roughening treatment.

9. The production method for wiring and vias according to claim 1, wherein after the seed layer forming step and before the electroplating step, arithmetic average roughness Ra defined by JISB0601 in the trench and the via is larger than arithmetic average roughness Ra defined by JISB0601 on areas other than the trench and the via.

10. The production method for wiring and vias according to claim 1, wherein after the seed layer forming step and before the electroplating step, an average length RSm of a roughness curvilinear element defined by JISB0601 in the trench and the via is smaller than an average length RSm of a roughness curvilinear element defined by JISB0601 on areas other than the trench and the via.

11. The production method for wiring and vias according to claim 1, wherein after the seed layer forming step and before the electroplating step, arithmetic average roughness Ra defined by JISB0601 in the trench and the via is not less than 10 times as large as arithmetic average roughness Ra defined by JISB0601 on areas other than the trench and the via, and an average length RSm of a roughness curvilinear element defined by JISB0601 in the trench and the via is not more than 1/10 times as large as an average length RSm of a roughness curvilinear element defined by JISB0601 on areas other than the trench and the via.

12. The production method for wiring and vias according to claim 1, wherein after the seed layer forming step and before the electroplating step, arithmetic average roughness Ra defined by JISB0601 in the trench and the via is 0.01 to 4 μm, and an average length RSm of a roughness curvilinear element defined by JISB0601 in the trench and the via is 0.005 to 8 μm.

13. The production method for wiring and vias according to claim 1, wherein at the trench and the via forming step, the trench and the via are formed simultaneously on the substrate.

14. The production method for wiring and vias according to claim 1, wherein the trench and the via are formed by any one of a photolithography method, a laser radiation method and a nanoimprint method.