NO994201L - Krets for frekvenssyntese - Google Patents

Krets for frekvenssyntese

Info

Publication number
NO994201L
NO994201L NO994201A NO994201A NO994201L NO 994201 L NO994201 L NO 994201L NO 994201 A NO994201 A NO 994201A NO 994201 A NO994201 A NO 994201A NO 994201 L NO994201 L NO 994201L
Authority
NO
Norway
Prior art keywords
delay
multiplexer
clock cycle
phase
output
Prior art date
Application number
NO994201A
Other languages
English (en)
Other versions
NO994201D0 (no
Inventor
Alain Vergnes
Didier Valenti
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of NO994201D0 publication Critical patent/NO994201D0/no
Publication of NO994201L publication Critical patent/NO994201L/no

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

En direkte digital frekvenssyntheziser inneholdende en mo-duloakkumulator (17, 117) som adresserer en multiplekser (33, 133). Multiplekseren mottar en serie forsinkelses-signaler generert av digitale kretser (41-45, 141-153). Forsinkelsessignalene etablerer fasen til en referanse-oscillator (37, 137). Antallet enheter forsinkelse er tilstrekkelig til å oppløse forventet skjelving (jitter). Akkumulatoren er en digital teller som øker med bare ett enkelt tall for hver telling, slik som en Gray-kodeteller. I en utførelse genereres forsinkelsessignalene av en lad-ningspumpe (3, figur 5) som føder individuelle logiske kretser (41, figur 3-4) som driver integrerte kondensato-rer i en sløyfe. Tilbakekobling til ladningspumpen etablerer at den totale forsinkelse vil dele ned en enkelt klokkesyklus av referanseklokken. I en andre utførelse vil en enkelt skifter eller flere skiftere (151, 153), med utgang i fasereverserende forhold (45), dele ned en enkelt klokkesyklus. En klokkemultiplikator (141) og deler (147) brukes til å sikre synkroniseringen av hver klokkesyklus med det totale antall enheter med forsinkelse. Utgangen (33, 155) av multiplekseren (33, 133) er referanseoscil-latorsignalet, justert av faseforsinkelsen, som danner en syntetisert utgangsfrekvens.
NO994201A 1998-01-21 1999-08-30 Krets for frekvenssyntese NO994201L (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/010,434 US5977805A (en) 1998-01-21 1998-01-21 Frequency synthesis circuit tuned by digital words
PCT/US1999/000873 WO1999038252A1 (en) 1998-01-21 1999-01-14 Frequency synthesis circuit tuned by digital words

Publications (2)

Publication Number Publication Date
NO994201D0 NO994201D0 (no) 1999-08-30
NO994201L true NO994201L (no) 1999-11-22

Family

ID=21745751

Family Applications (1)

Application Number Title Priority Date Filing Date
NO994201A NO994201L (no) 1998-01-21 1999-08-30 Krets for frekvenssyntese

Country Status (12)

Country Link
US (1) US5977805A (no)
EP (1) EP0988691B1 (no)
JP (1) JP2001515695A (no)
KR (1) KR20010005533A (no)
CN (1) CN1127200C (no)
CA (1) CA2284842A1 (no)
DE (1) DE69926320T2 (no)
HK (1) HK1025685A1 (no)
MY (1) MY114617A (no)
NO (1) NO994201L (no)
TW (1) TW510084B (no)
WO (1) WO1999038252A1 (no)

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US7302237B2 (en) * 2002-07-23 2007-11-27 Mercury Computer Systems, Inc. Wideband signal generators, measurement devices, methods of signal generation, and methods of signal analysis
US20050013396A1 (en) * 2003-07-15 2005-01-20 Adtran, Inc. Digital clock recovery circuit employing fixed clock oscillator driving fractional delay line
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CN100392976C (zh) * 2005-01-11 2008-06-04 中国科学院半导体研究所 用于直接数字频率合成的高阶∑△噪声整形内插器
US7102403B2 (en) * 2005-02-03 2006-09-05 Mediatek Incorporation Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof
US7190201B2 (en) * 2005-02-03 2007-03-13 Mosaid Technologies, Inc. Method and apparatus for initializing a delay locked loop
US7164297B2 (en) * 2005-03-31 2007-01-16 Freescale Semiconductor, Inc. Multiple reference clock synthesizer
KR100666492B1 (ko) * 2005-08-11 2007-01-09 삼성전자주식회사 타이밍 생성기 및 그 동작 방법
WO2007109744A2 (en) * 2006-03-21 2007-09-27 Multigig Inc. Dual pll loop for phase noise filtering
US7433262B2 (en) * 2006-08-22 2008-10-07 Atmel Corporation Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction
US7539078B2 (en) * 2006-08-22 2009-05-26 Atmel Corporation Circuits to delay a signal from a memory device
US7642831B2 (en) * 2007-07-23 2010-01-05 Altera Corporation Phase shift circuit with lower intrinsic delay
US8046621B2 (en) * 2007-09-24 2011-10-25 Broadcom Corporation Method and system for generation of signals up to extremely high frequencies using a delay block
US8059706B2 (en) * 2007-09-24 2011-11-15 Broadcom Corporation Method and system for transmission and/or reception of signals utilizing a delay circuit and DDFS
US8160506B2 (en) * 2007-09-24 2012-04-17 Broadcom Corporation Method and system for transmission and/or reception of signals up to extremely high frequencies utilizing a delay circuit
CN100520672C (zh) * 2007-09-28 2009-07-29 电子科技大学 Dds信号发生器幅频特性补偿方法及相应的dds信号发生器
US20090138329A1 (en) * 2007-11-26 2009-05-28 William Paul Wanker Application of query weights input to an electronic commerce information system to target advertising
EP2141797A1 (en) * 2008-07-02 2010-01-06 Nxp B.V. Circuit with a time to digital converter and phase measuring method
US8044742B2 (en) 2009-03-11 2011-10-25 Qualcomm Incorporated Wideband phase modulator
US8588720B2 (en) 2009-12-15 2013-11-19 Qualcomm Incorproated Signal decimation techniques
EP2391000B1 (en) * 2010-05-26 2020-07-08 Integrated Device Technology, Inc. Digital Signal Generator
US20120139592A1 (en) * 2010-12-07 2012-06-07 Qualcomm Incorporated Method and Apparatus for Frequency Synthesizing
RU2470458C1 (ru) * 2011-10-28 2012-12-20 Федеральное государственное унитарное предприятие "Научно-производственное объединение автоматики имени академика Н.А. Семихатова" Устройство формирования интервалов
CN103368567B (zh) * 2012-04-06 2016-03-30 联咏科技股份有限公司 频率合成器
US9000858B2 (en) 2012-04-25 2015-04-07 Qualcomm Incorporated Ultra-wide band frequency modulator
US8817184B1 (en) * 2013-07-12 2014-08-26 Samsung Display Co., Ltd. Point to multi-point clock-forwarded signaling for large displays
EP3075078A4 (en) * 2013-11-28 2017-08-02 Nokia Technologies Oy Method and apparatus for generating oscillator signals
CN105337592B (zh) * 2015-08-28 2018-05-01 北京航天自动控制研究所 一种定周期脉冲周期稳定性监测方法
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Also Published As

Publication number Publication date
EP0988691A4 (en) 2003-05-07
NO994201D0 (no) 1999-08-30
CN1256023A (zh) 2000-06-07
CA2284842A1 (en) 1999-07-29
MY114617A (en) 2002-11-30
TW510084B (en) 2002-11-11
DE69926320T2 (de) 2006-04-20
KR20010005533A (ko) 2001-01-15
EP0988691A1 (en) 2000-03-29
JP2001515695A (ja) 2001-09-18
EP0988691B1 (en) 2005-07-27
WO1999038252A1 (en) 1999-07-29
US5977805A (en) 1999-11-02
DE69926320D1 (de) 2005-09-01
CN1127200C (zh) 2003-11-05
HK1025685A1 (en) 2000-11-17

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