KR970030474A - 반도체 소자의 앝은 접합 형성방법 - Google Patents

반도체 소자의 앝은 접합 형성방법 Download PDF

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KR970030474A
KR970030474A KR1019950041042A KR19950041042A KR970030474A KR 970030474 A KR970030474 A KR 970030474A KR 1019950041042 A KR1019950041042 A KR 1019950041042A KR 19950041042 A KR19950041042 A KR 19950041042A KR 970030474 A KR970030474 A KR 970030474A
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film
zirconium
forming
semiconductor device
titanium
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KR1019950041042A
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KR0164072B1 (ko
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박보현
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김주용
현대전자산업 주식회사
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Priority to US08/744,154 priority patent/US5795808A/en
Priority to DE19646927A priority patent/DE19646927C2/de
Priority to JP08301727A priority patent/JP3098198B2/ja
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Abstract

본 발명은 반도체소자의 얕은 접합 형성방법에 관한 것으로, 본 발명은 고집적 반도체 소자의 제조공정에서 필수적인 얕은 접함을 형성하기 위하여 게이트와 소오스/드레인인 형성될 영역의 상부에 지르코늄막을 증착한후 도펀트를 주입하고, 그 상부에 티타늄막을 증착한 후 실리사이드 공정을 진행함으로써 접합의 면저항, 접촉 저항 및 누설전류를 감소하는 반도체소자의 얕은 접합 형성방법을 제공한다. 이를 위하여 실리콘기판에 웰, 소자분리막, 게이트산화막, 게이트, 산화막스페이서를 형성하는 단계와, 전체 구조를 클리닝하는 단계와, 전체 구조의 상부에 지르코늄막을 증착하는 단계와, 상기 지르코늄막의 상부에서 이온을 주입하여 소오스/드레인의 접합부를 형성하는 단계와, 전체 구조의 표면을 클리닝하는 단계와, 전체 구조의 상부에 티타늄막을 증착하는 단계와, 상기 지르코늄막과 티타늄막을 제1차 단시간 급속 열처리하여 준 안정성 지르코늄실리사이드와, 준 안정성 티타늄실리사이드를 형성하는 단계와, 반응하지 않는 지르코늄막과 티타늄막을 식각하는 단계와, 상기 준 안정성 지르코늄실리사이드와 티타늄실리사이드를 제2차 단시간 급속 열처리하여 지르코늄실리사이드와, 안정성 티타늄실리사이드를 형성하는 단계와, 전체 구조의 상부에 층간절연막을 증착하고, 열처리하여 평탄화하는 단계를 포함한다.

Description

반도체 소자의 얕은 접합 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3a도 내지 제3f는 본 발명의 실시예에 의해 반도체소자의 얕은 접합을 형성하는 단계를 도시한 단면도.

Claims (10)

  1. 실리콘기판에 웰, 소자분리막, 게이트산화막, 게이트, 산화막스페이서를 형성하는 단계와, 전체 구조를 클리닝하는 단계와, 전체 구조의 상부에 지르코늄막을 증착하는 단계와, 상기 지르코늄막의 상부에서 이온을 주입하여 소오스/드레인의 접합부을 형성하는 단계와, 전체 구조의 표면을 클리닝하는 단계와, 전체 구조의 상부에 티타늄막을 증착하는 단계와, 상기 지르코늄막과 티타늄막을 제1차 단시간 급속 열처리하여 지르코늄실리사이드와, 티타늄실리사이드를 형성하는 단계와, 반응하지 않는 지르코늄막과 티타늄막을 식각하는 단계와, 상기 제1차 열처리된 지르코늄실리사이드와 티타늄실리사이드를 제2차 단시간 금속 열처리하여 지르코늄실리사이드와, 티타늄실리사이드를 형성하는 단계와, 전체 구조의 상부에 층간절연막을 증착하고, 열처리하여 평탄화하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 얕은 접합 형성 방법.
  2. 제1항에 있어서, 지르코늄막을 증착하기 전에 구조를 클로닝할때, 불화수소를 사용하여 클리닝하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  3. 제1항에 있어서, 상기 지르코늄막은 50 내지 200Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  4. 제1항에 있어서, 상기 지르코늄막을 증착할 때, RF 혹은 DC 스퍼터링법으로 증착온도 20 내지 500℃, 증착압력은 1 mtorr 내지 100 mtorr에서 전구체는 Zr/Ar(+N2)로 하여 증착하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  5. 제1항에 있어서, 상기 지르코늄막을 증착할 때, 전자빔 증착빔으로 108내지 1011torr의 초고진공 상태에서 99.0% 이상의 고순도의 지르코늄을 전자빔증발시켜서 증착하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  6. 제1항에 있어서, 상기 티타늄막은 100 내지 500Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  7. 제1항에 있어서, 상기 티타늄막을 증착할 때, RF 혹은 DC 스퍼터링법으로 증착온도 20 내지 500℃, 증착압력은 1 mtorr 내지 100 mtorr에서 전구체는 Ti/Ar(+N2)로 하여 증착하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  8. 제1항에 있어서, 상기 티타늄막을 증착할 때, 전자빔 증착법으로 10-8내지 1011torr의 초고진공 상태에서 99.0% 이상의 고순도의 지르코늄을 전자빔 증발시켜서 증착하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  9. 제1항에 있어서, 반응하지 않는 티타늄막과 지르코늄막을 제거할 때, 암모니아수, 과산화수소수, 증류수가 1:1:5의 비율로 혼합된 용액을 사용하여 제거하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
  10. 제1항에 있어서, 제1차 및 제2차 단시간 급속 열처리 대신에 제1차 및 제2차 퍼네이서 열처리법을 이용하는 것을 특징으로 하는 반도체소자의 얕은 접합 형성 방법.
KR1019950041042A 1995-11-13 1995-11-13 반도체 소자의 얕은 접합 형성방법 KR0164072B1 (ko)

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KR1019950041042A KR0164072B1 (ko) 1995-11-13 1995-11-13 반도체 소자의 얕은 접합 형성방법
US08/744,154 US5795808A (en) 1995-11-13 1996-11-12 Method for forming shallow junction for semiconductor device
DE19646927A DE19646927C2 (de) 1995-11-13 1996-11-13 Verfahren zum Herstellen eines flachen Übergangs einer Halbleitervorrichtung
JP08301727A JP3098198B2 (ja) 1995-11-13 1996-11-13 半導体素子の浅い接合形成方法

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