KR960043187A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR960043187A
KR960043187A KR1019960017320A KR19960017320A KR960043187A KR 960043187 A KR960043187 A KR 960043187A KR 1019960017320 A KR1019960017320 A KR 1019960017320A KR 19960017320 A KR19960017320 A KR 19960017320A KR 960043187 A KR960043187 A KR 960043187A
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KR
South Korea
Prior art keywords
memory
bits
semiconductor
input
switching
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Application number
KR1019960017320A
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English (en)
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KR100426747B1 (ko
Inventor
노보루 아카야마
세이고 유쿠타케
사다유키 오오쿠마
아키히코 에모리
타카시 아키오카
슈이찌 미야오카
신지 나카자토
킨야 미쯔모토
Original Assignee
카나이 쯔또무
가부시기가이샤 히다찌세이사구쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 카나이 쯔또무, 가부시기가이샤 히다찌세이사구쇼 filed Critical 카나이 쯔또무
Publication of KR960043187A publication Critical patent/KR960043187A/ko
Application granted granted Critical
Publication of KR100426747B1 publication Critical patent/KR100426747B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 반도체집적회로장치, 특히 패리티비트를 가진 고속의 반도체메모리 혹은 그것을 포함한 반도체장치에 관한 것으로서, 패리티비트를 가지고, 또한 입출력비트수를 복수가지로 절환하는 일이 가능한 반도체메모리에 있어서, 비트수 구성을 절환해도, 모리블록의 구성비트수가 균등하고, 지연시간을 증대시키지 않고 고속으로 동작하는 반도체메모리 또는 그것을 사용한 마이크로컴퓨터등의 반도체장치를 제공하는 것을 목적으로 한 것이며, 그 구성에 있어서, 패리티비트를 포함한 복수비트로 이루어지고, 복수의 메모리블록에 의해서 분할 되어서 구성되는 메모리어레이와, 상기 메모리어레이의 입출력비트수를 절환하는 비트구성절환부를 가진, 메모리장치에 있어서, 상기 메모리블록의 수를 3의 배수로 하고, 상기 복수의 메모리블록의 입출력비트수를 균등하게 한 것을 특징으로 한 것이다.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 메모리어레이의 일구성예를 표시한 도면, 제2도는 본 발명의 메모리블록이 일구성예를 표시한 도면.

Claims (6)

  1. 패리티비트를 포함한 복수비트로 이루어지고, 복수의 메모리블록으로 구성되는 메모리어레이와, 상기 메모리어레이의 입출력비트수를 절환하는 비트 구성절환부를 가지고, 상기 메모리블록의 수가 3의 배수이고, 상기 복수의 메모리블록의 각각의 입출력비트수를 균등하게 한 것을 특징으로 하는 반도체기억장치.
  2. 제1항에 있어서, 상기 복수개의 메모리블록중 칩중앙부에 있는 메모리블록에는, 그 메모리 블록의 중앙부에 주변회로를 배치한 것을 특징으로 하는 반도체기억장치.
  3. 패리티비트를 포함한 복수비트로 이루어지고, 복수의 메모리블록으로 구성되는 메모리어레이와, 상기 메모리어레이의 입출력비트수를 절환하는 비트구성절환부와, 상기 비트구성절환부가, 복수가지의 비트구성으로 부터 1개의 비트구성을 선택하는 I/O선택부와, 상기 I/O선택부의 출력신호를 받아서 데이터의 출력수, 또는, 데이터의 입력수를 절환하는 데이터선택부를 가지고, 상기 메모리블록의 수가 3의 배수이고, 상기 복수의 메모리블록의 각각의 입출력비트수를 균등하게 한 것을 특징으로 하는 반도체기억장치.
  4. 제3항에 있어서, 상기 데이터선택부는 적어도 메모리셀에 데이터를 기록하는 라이트앰프와, 메모리셀로부터 출력된 데이터를 증폭하는 센스앰프를 가진 것을 특징으로 하는 반도체기억장치.
  5. 제3항에 있어서, 상기 데이터선택부는, 적어도 메모리셀에 접속된 비트선과 상기 라이트앰프 및 센스앰프를 접속 또는 분리하는 컬럼선택스위치를 가진 것을 특징으로 하는 반도체기억장치.
  6. 제3항에 있어서, 상기 복수개의 메모리블록중 칩중앙부에 있는 메모리블록에는 그 메모리블록의 중앙부에 주변회로를 배치한 것을 특징으로 하는 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960017320A 1995-05-22 1996-05-22 반도체장치 KR100426747B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-122119 1995-05-22
JP12211995A JP3386924B2 (ja) 1995-05-22 1995-05-22 半導体装置

Publications (2)

Publication Number Publication Date
KR960043187A true KR960043187A (ko) 1996-12-23
KR100426747B1 KR100426747B1 (ko) 2004-10-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960017320A KR100426747B1 (ko) 1995-05-22 1996-05-22 반도체장치

Country Status (4)

Country Link
US (1) US5638335A (ko)
JP (1) JP3386924B2 (ko)
KR (1) KR100426747B1 (ko)
TW (1) TW306000B (ko)

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JP3291206B2 (ja) * 1996-09-17 2002-06-10 富士通株式会社 半導体記憶装置
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Also Published As

Publication number Publication date
JPH08315578A (ja) 1996-11-29
US5638335A (en) 1997-06-10
JP3386924B2 (ja) 2003-03-17
TW306000B (ko) 1997-05-21
KR100426747B1 (ko) 2004-10-08

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