KR940012619A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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KR940012619A
KR940012619A KR1019930023943A KR930023943A KR940012619A KR 940012619 A KR940012619 A KR 940012619A KR 1019930023943 A KR1019930023943 A KR 1019930023943A KR 930023943 A KR930023943 A KR 930023943A KR 940012619 A KR940012619 A KR 940012619A
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semiconductor substrate
insulating film
forming
impurity
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마사히로 시미즈
카쯔히로 쯔카모토
헤이지 고바야시
하지메 아라이
토모하루 마메타니
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/10DRAM devices comprising bipolar components
    • HELECTRICITY
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    • H10B99/00Subject matter not provided for in other groups of this subclass

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

소자의 미세화에 있어서, 협 채널효과(挾 채널效果)를 억제하고 또한 기판 바이어스 효과를 작게 억제한 반도체 장치의 제조방법을 제공한다.
소자형성 영역을 분리하도록 두꺼운 분리산화막을 실리콘 기판(1)의 표면에 선택적으로 형성한다.
두꺼운 분리산화막을 통해서 불순물을 실리콘 기판(1)의 영역내에 이온 주입한다.
그것으로 인해, 분리산화막의 밑에 위치하는 실리콘 기판(1)의 영역에 불순물 농도 피크위치(51b, 61b)를 가진 레트로 그리드 웰(51, 61)를 형성한다.
그후, 분리산화막의 상방부분을 제거하므로서, 막두께가 줄어진 분리산화막(21)이 형성된다.
불리산화막(21)은 축소된 소자간 분리길이 L를 가진다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제1공정을 표시하는 단면도.
제2도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제2공정을 표시하는 단면도.
제3도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제3공정을 표시하는 단면도.
제4도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제4공정을 표시하는 단면도.
제5도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제5공정을 표시하는 단면도.
제6도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제6공정을 표시하는 단면도.
제7도는 이 발명에 따른 제1의 실시예에 있어서의 제1실시예를 적용한 DRAM의 제조방법을 각 공정순으로 표시한 부분 단면도.

Claims (7)

  1. 소자형성 영역을 분리하도록 소정의 두께를 갖이는 분리 절연막을 반도체 기판의 주표면에 선택적으로 형성하는 공정과, 상기 반도체 기판의 주표면의 상방으로부터 상기 분리절연막을 통해서 불순물을 상기 반도체 기판의 영역내에 도입하므로서, 상기 분리절연막의 아래에 위치하는 상기 반도체 기판의 영역에 일정한 불순물 농도 분포를 갖이는 웰 영역을 형성하는 공정과, 상기 웰 영역을 형성한후, 상기 분리절연막의 표면부분을 제거하는 공정과를 구비한 반도체 장치의 제조방법.
  2. 소자형성 영역을 분리하도록 분리절연막을 반도체 기판의 주표면에 선택적으로 형성하는 공정과, 상기 분리 절연막의 표면을 노출시키는 마스크층을 형성하는 공정과, 상기 노출된 상기 분리절연막을 통해서 불순물을 도입하므로서, 상기 분리절연막에 근접하는 상기 반도체 기판내의 영역에 제1의 불순물 영역을 형성하는 공정과, 상기 반도체 기판의 상방으로부터 상기 제1의 불순물 영역보다도 상기 반도체 기판의 표면으로부터 떨어진 영역에 제2의 불순물 영역을 형성하는 공정과를 구비한 반도체 장치의 제조방법.
  3. 소자형성 영역을 분리하도록 소자분리층을 반도체 기판의 주표면에 선택적으로 형성하는 공정과, 상기 소자형성 영역의 표면을 노출시키는 마스크층을 상기 소자분리층의 위체 형성하는 공정과, 상기 마스크층과 상기 소자분리층을 통해서 불순물을 도입하므로서, 상기 분리절연막을 근접하는 상기 반도체 기판내의 제1의 영역으로부터, 그 제1의 영역보다도 상기 반도체 기판의 표면으로부터 떨어진 제2의 영역에 늘어놓도록 불순물 영역을 형성하는 공정과를 구비한 반도체 장치의 제조방법.
  4. 제3항에 있어서, 상기 마스크층은 상기 소자분리층의 일부를 구성하는 반도체 장치의 제조방법.
  5. 제3항에 있어서, 상기 소자분리층을 분리절연막을 포함하는 반도체장치의 제조방법.
  6. 제3항에 있어서, 상기 소자분리층은 상기 반도체 기판상에 형성된 절연층과 그 절연층상에 형성된 도전층과의 적층구조를 포함한 반도체장치의 제조방법.
  7. 반도체 기판의 소자분리 영역내의 제1의 영역에 선택적으로 불순물을 도입하는 공정과, 상기 소자분리 영역내에서 상기 제1의 영역을 포함하고 또한 둘러쌓는 제2의 영역에 소정의 두께를 갖이는 분리절연막을 상기 반도체 기판의 주표면에 형성하고, 그것에 의해 상기 제1의 영역에 제1의 불순물 영역을 형성하는 공정과, 상기 반도체 기판의 상방으로부터 상기 제1의 불순물 영역보다도 상기 반도체 기판의 표면에서 떨어진 영역에 제2의 불순물영역을 구성하는 공정과를 구비한 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930023943A 1992-11-26 1993-11-11 반도체 장치의 제조방법 KR0126230B1 (ko)

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JP4317110A JP2978345B2 (ja) 1992-11-26 1992-11-26 半導体装置の製造方法
JP92-317110 1992-11-26

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DE4340405C2 (de) 2001-03-15
KR0126230B1 (ko) 1997-12-29
JPH06163844A (ja) 1994-06-10
DE4340405A1 (de) 1994-06-01
JP2978345B2 (ja) 1999-11-15
US5478759A (en) 1995-12-26

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