KR940012619A - 반도체장치의 제조방법 - Google Patents
반도체장치의 제조방법 Download PDFInfo
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- KR940012619A KR940012619A KR1019930023943A KR930023943A KR940012619A KR 940012619 A KR940012619 A KR 940012619A KR 1019930023943 A KR1019930023943 A KR 1019930023943A KR 930023943 A KR930023943 A KR 930023943A KR 940012619 A KR940012619 A KR 940012619A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract 19
- 239000012535 impurity Substances 0.000 claims abstract 14
- 238000000926 separation method Methods 0.000 claims abstract 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract 5
- 238000002955 isolation Methods 0.000 claims 16
- 238000000034 method Methods 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- 230000000694 effects Effects 0.000 abstract 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/10—DRAM devices comprising bipolar components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
소자의 미세화에 있어서, 협 채널효과(挾 채널效果)를 억제하고 또한 기판 바이어스 효과를 작게 억제한 반도체 장치의 제조방법을 제공한다.
소자형성 영역을 분리하도록 두꺼운 분리산화막을 실리콘 기판(1)의 표면에 선택적으로 형성한다.
두꺼운 분리산화막을 통해서 불순물을 실리콘 기판(1)의 영역내에 이온 주입한다.
그것으로 인해, 분리산화막의 밑에 위치하는 실리콘 기판(1)의 영역에 불순물 농도 피크위치(51b, 61b)를 가진 레트로 그리드 웰(51, 61)를 형성한다.
그후, 분리산화막의 상방부분을 제거하므로서, 막두께가 줄어진 분리산화막(21)이 형성된다.
불리산화막(21)은 축소된 소자간 분리길이 L를 가진다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제1공정을 표시하는 단면도.
제2도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제2공정을 표시하는 단면도.
제3도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제3공정을 표시하는 단면도.
제4도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제4공정을 표시하는 단면도.
제5도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제5공정을 표시하는 단면도.
제6도는 이 발명에 따른 제1의 실시예에 있어서의 반도체장치의 제조방법의 제6공정을 표시하는 단면도.
제7도는 이 발명에 따른 제1의 실시예에 있어서의 제1실시예를 적용한 DRAM의 제조방법을 각 공정순으로 표시한 부분 단면도.
Claims (7)
- 소자형성 영역을 분리하도록 소정의 두께를 갖이는 분리 절연막을 반도체 기판의 주표면에 선택적으로 형성하는 공정과, 상기 반도체 기판의 주표면의 상방으로부터 상기 분리절연막을 통해서 불순물을 상기 반도체 기판의 영역내에 도입하므로서, 상기 분리절연막의 아래에 위치하는 상기 반도체 기판의 영역에 일정한 불순물 농도 분포를 갖이는 웰 영역을 형성하는 공정과, 상기 웰 영역을 형성한후, 상기 분리절연막의 표면부분을 제거하는 공정과를 구비한 반도체 장치의 제조방법.
- 소자형성 영역을 분리하도록 분리절연막을 반도체 기판의 주표면에 선택적으로 형성하는 공정과, 상기 분리 절연막의 표면을 노출시키는 마스크층을 형성하는 공정과, 상기 노출된 상기 분리절연막을 통해서 불순물을 도입하므로서, 상기 분리절연막에 근접하는 상기 반도체 기판내의 영역에 제1의 불순물 영역을 형성하는 공정과, 상기 반도체 기판의 상방으로부터 상기 제1의 불순물 영역보다도 상기 반도체 기판의 표면으로부터 떨어진 영역에 제2의 불순물 영역을 형성하는 공정과를 구비한 반도체 장치의 제조방법.
- 소자형성 영역을 분리하도록 소자분리층을 반도체 기판의 주표면에 선택적으로 형성하는 공정과, 상기 소자형성 영역의 표면을 노출시키는 마스크층을 상기 소자분리층의 위체 형성하는 공정과, 상기 마스크층과 상기 소자분리층을 통해서 불순물을 도입하므로서, 상기 분리절연막을 근접하는 상기 반도체 기판내의 제1의 영역으로부터, 그 제1의 영역보다도 상기 반도체 기판의 표면으로부터 떨어진 제2의 영역에 늘어놓도록 불순물 영역을 형성하는 공정과를 구비한 반도체 장치의 제조방법.
- 제3항에 있어서, 상기 마스크층은 상기 소자분리층의 일부를 구성하는 반도체 장치의 제조방법.
- 제3항에 있어서, 상기 소자분리층을 분리절연막을 포함하는 반도체장치의 제조방법.
- 제3항에 있어서, 상기 소자분리층은 상기 반도체 기판상에 형성된 절연층과 그 절연층상에 형성된 도전층과의 적층구조를 포함한 반도체장치의 제조방법.
- 반도체 기판의 소자분리 영역내의 제1의 영역에 선택적으로 불순물을 도입하는 공정과, 상기 소자분리 영역내에서 상기 제1의 영역을 포함하고 또한 둘러쌓는 제2의 영역에 소정의 두께를 갖이는 분리절연막을 상기 반도체 기판의 주표면에 형성하고, 그것에 의해 상기 제1의 영역에 제1의 불순물 영역을 형성하는 공정과, 상기 반도체 기판의 상방으로부터 상기 제1의 불순물 영역보다도 상기 반도체 기판의 표면에서 떨어진 영역에 제2의 불순물영역을 구성하는 공정과를 구비한 반도체장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4317110A JP2978345B2 (ja) | 1992-11-26 | 1992-11-26 | 半導体装置の製造方法 |
JP92-317110 | 1992-11-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940012619A true KR940012619A (ko) | 1994-06-24 |
KR0126230B1 KR0126230B1 (ko) | 1997-12-29 |
Family
ID=18084553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930023943A KR0126230B1 (ko) | 1992-11-26 | 1993-11-11 | 반도체 장치의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5478759A (ko) |
JP (1) | JP2978345B2 (ko) |
KR (1) | KR0126230B1 (ko) |
DE (1) | DE4340405C2 (ko) |
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JP2004079775A (ja) * | 2002-08-19 | 2004-03-11 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US6855985B2 (en) * | 2002-09-29 | 2005-02-15 | Advanced Analogic Technologies, Inc. | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology |
US6767809B2 (en) * | 2002-11-19 | 2004-07-27 | Silterra Malayisa Sdn. Bhd. | Method of forming ultra shallow junctions |
CN1290178C (zh) * | 2003-08-27 | 2006-12-13 | 上海宏力半导体制造有限公司 | 利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法 |
TWI260717B (en) * | 2004-05-17 | 2006-08-21 | Mosel Vitelic Inc | Ion-implantation method for forming a shallow junction |
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JP5751531B2 (ja) | 2012-06-15 | 2015-07-22 | 信越半導体株式会社 | 半導体基板の評価方法、評価用半導体基板、半導体装置 |
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US4633289A (en) * | 1983-09-12 | 1986-12-30 | Hughes Aircraft Company | Latch-up immune, multiple retrograde well high density CMOS FET |
JPS60101946A (ja) * | 1983-11-07 | 1985-06-06 | Nec Corp | 半導体装置の製造方法 |
NL8501992A (nl) * | 1985-07-11 | 1987-02-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
US5061654A (en) * | 1987-07-01 | 1991-10-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit having oxide regions with different thickness |
JPH0821615B2 (ja) * | 1987-07-01 | 1996-03-04 | 三菱電機株式会社 | 半導体記憶装置の製造方法 |
DE3856150T2 (de) * | 1987-10-08 | 1998-08-06 | Matsushita Electric Ind Co Ltd | Halbleiteranordnung und verfahren zur herstellung |
US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
JPH01194436A (ja) * | 1988-01-29 | 1989-08-04 | Nec Yamaguchi Ltd | 半導体装置 |
JPH01244635A (ja) * | 1988-03-25 | 1989-09-29 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH02309653A (ja) * | 1989-05-24 | 1990-12-25 | Matsushita Electron Corp | 半導体集積回路の製造方法 |
JP3090669B2 (ja) * | 1989-10-27 | 2000-09-25 | ソニー株式会社 | 半導体装置の製造方法 |
US5138420A (en) * | 1989-11-24 | 1992-08-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having first and second type field effect transistors separated by a barrier |
-
1992
- 1992-11-26 JP JP4317110A patent/JP2978345B2/ja not_active Expired - Fee Related
-
1993
- 1993-11-11 KR KR1019930023943A patent/KR0126230B1/ko not_active IP Right Cessation
- 1993-11-24 US US08/156,748 patent/US5478759A/en not_active Expired - Lifetime
- 1993-11-26 DE DE4340405A patent/DE4340405C2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE4340405C2 (de) | 2001-03-15 |
KR0126230B1 (ko) | 1997-12-29 |
JPH06163844A (ja) | 1994-06-10 |
DE4340405A1 (de) | 1994-06-01 |
JP2978345B2 (ja) | 1999-11-15 |
US5478759A (en) | 1995-12-26 |
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