JP5751531B2 - 半導体基板の評価方法、評価用半導体基板、半導体装置 - Google Patents
半導体基板の評価方法、評価用半導体基板、半導体装置 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 90
- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000011156 evaluation Methods 0.000 title claims description 29
- 239000002019 doping agent Substances 0.000 claims description 37
- 238000009792 diffusion process Methods 0.000 claims description 28
- 238000005468 ion implantation Methods 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 15
- 230000007547 defect Effects 0.000 claims description 12
- 238000012360 testing method Methods 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 128
- 235000012431 wafers Nutrition 0.000 description 47
- 125000004429 atom Chemical group 0.000 description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 23
- 238000005259 measurement Methods 0.000 description 12
- 239000002344 surface layer Substances 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 238000011109 contamination Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- 229910001385 heavy metal Inorganic materials 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001444 catalytic combustion detection Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- WQGWDDDVZFFDIG-UHFFFAOYSA-N pyrogallol Chemical compound OC1=CC=CC(O)=C1O WQGWDDDVZFFDIG-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000013441 quality evaluation Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06596—Structural arrangements for testing
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- Computer Hardware Design (AREA)
- Automation & Control Theory (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Element Group)を構成している。なお、図1の箇所101は、セル20が形成された複数の箇所から任意に選択した一の箇所とされている。図2のセル20の接合構造と従来の接合構造30(図7参照)の一番大きな違いは、セル20には、空乏層が表層近傍及びEP層/EP基板界面の2箇所に存在していることである。以下、セル20の接合構造を詳細に説明する。
2 EP層(エピタキシャル層)
3、7 pn接合
4、8 空乏層
5 ウェル
6 拡散層
9 分離酸化膜
10 チャネルストップ層
20 セル(半導体装置)
100 シリコンウェーハ(評価用半導体基板)
Claims (11)
- 第1の導電型の半導体基板とは異なる第2の導電型のエピタキシャル層を該半導体基板上に成長させ、該エピタキシャル層と同じ第2の導電型のウェルを該エピタキシャル層中に形成し、該ウェルの接合周辺にチャネルストップ層を設け、該ウェル中に、該ウェルと異なる第1の導電型のドーパントを拡散させてpn接合を設け一方の電極とし、もう一方の電極は前記半導体基板のエピタキシャル層を成長させていない面としてひとつのセルとし、該セルを前記半導体基板上に複数形成してTEG(Test Element Group)として使用し、各ウェル中に形成される空乏層及びエピタキシャル層と半導体基板の界面に形成される空乏層の2つの空乏層からの接合リーク電流を測定し、
前記ウェルのドーパント濃度を1×10 16 atoms/cm 3 から1×10 17 atoms/cm 3 としたことを特徴とする半導体基板の評価方法。 - 前記半導体基板上に前記エピタキシャル層を成長させた後、そのエピタキシャル層上に、窓開けした部分を有した分離酸化膜を形成し、イオン注入により前記窓開けした部分直下に前記ウェルを形成するとともに、前記分離酸化膜直下に該イオン注入で注入されるドーパントで前記チャネルストップ層を形成することを特徴とする請求項1に記載の半導体基板の評価方法。
- 前記ウェル形成時において、前記分離酸化膜以外の酸化膜を形成せず直接イオン注入し、このイオン注入において注入量はGOI(酸化膜耐圧)に影響する欠陥が生じない範囲とすることを特徴とする請求項2に記載の半導体基板の評価方法。
- 前記ウェル上の電極の電極面積が4mm2以下であることを特徴とする請求項1乃至3のいずれか1項に記載の半導体基板の評価方法。
- 前記ウェルはドーパント濃度1×1016atoms/cm3から1×1017atoms/cm3で深さ2μm以下であり、前記ウェル内部に形成された拡散層はドーパント濃度1×1018atoms/cm3から5×1020atoms/cm3で深さ1μm以下であり、前記チャネルストップ層はドーパント濃度1×1016atoms/cm3から1×1017atoms/cm3で深さ0.5μm以下であることを特徴とする請求項1乃至4のいずれか1項に記載の半導体基板の評価方法。
- 第1の導電型の半導体基板とは異なる第2の導電型のエピタキシャル層を該半導体基板上に成長させ、該エピタキシャル層と同じ第2の導電型のウェルを該エピタキシャル層中に形成し、該ウェルの接合周辺にチャネルストップ層を設け、該ウェル中に、該ウェルと異なる第1の導電型のドーパントを拡散させてpn接合を設け一方の電極とし、もう一方の電極は前記半導体基板のエピタキシャル層を成長させていない面としてひとつのセルとし、該セルを前記半導体基板上に複数形成してTEG(Test Element Group)として使用し、
前記ウェルのドーパント濃度を1×10 16 atoms/cm 3 から1×10 17 atoms/cm 3 としたことを特徴とする評価用半導体基板。 - 前記ウェル上の電極の電極面積が4mm2以下であることを特徴とする請求項6に記載の評価用半導体基板。
- 前記ウェルはドーパント濃度1×1016atoms/cm3から1×1017atoms/cm3で深さ2μm以下であり、前記ウェル内部に形成された拡散層はドーパント濃度1×1018atoms/cm3から5×1020atoms/cm3で深さ1μm以下であり、前記チャネルストップ層はドーパント濃度1×1016atoms/cm3から1×1017atoms/cm3で深さ0.5μm以下であることを特徴とする請求項6または7に記載の評価用半導体基板。
- 第1の導電型の半導体基板とは異なる第2の導電型のエピタキシャル層を該半導体基板上に成長させ、該エピタキシャル層と同じ第2の導電型のウェルを該エピタキシャル層中に形成し、該ウェルの接合周辺にチャネルストップ層を設け、該ウェル中に、該ウェルと異なる第1の導電型のドーパントを拡散させてpn接合を設け一方の電極とし、もう一方の電極は前記半導体基板のエピタキシャル層を成長させていない面としてひとつのセルとし、
前記ウェルのドーパント濃度を1×10 16 atoms/cm 3 から1×10 17 atoms/cm 3 としたことを特徴とする半導体装置。 - 前記ウェル上の電極の電極面積が4mm2以下であることを特徴とする請求項9に記載の半導体装置。
- 前記ウェルはドーパント濃度1×1016atoms/cm3から1×1017atoms/cm3で深さ2μm以下であり、前記ウェル内部に形成された拡散層はドーパント濃度1×1018atoms/cm3から5×1020atoms/cm3で深さ1μm以下であり、前記チャネルストップ層はドーパント濃度1×1016atoms/cm3から1×1017atoms/cm3で深さ0.5μm以下であることを特徴とする請求項9または10に記載の半導体装置。
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JP2012135726A JP5751531B2 (ja) | 2012-06-15 | 2012-06-15 | 半導体基板の評価方法、評価用半導体基板、半導体装置 |
CN201380025843.0A CN104303280B (zh) | 2012-06-15 | 2013-04-25 | 半导体基板的评价方法、评价用半导体基板、半导体装置 |
KR1020147026435A KR101943067B1 (ko) | 2012-06-15 | 2013-04-25 | 반도체 기판의 평가 방법, 평가용 반도체 기판, 반도체 장치 |
US14/404,848 US9696368B2 (en) | 2012-06-15 | 2013-04-25 | Semiconductor substrate evaluating method, semiconductor substrate for evaluation, and semiconductor device |
PCT/JP2013/062277 WO2013187140A1 (ja) | 2012-06-15 | 2013-04-25 | 半導体基板の評価方法、評価用半導体基板、半導体装置 |
DE112013002978.2T DE112013002978B4 (de) | 2012-06-15 | 2013-04-25 | Halbleitersubstrat-Beurteilungsverfahren, Halbleitersubstrat zur Beurteilung und Halbleiterbauelement |
TW102116137A TWI521217B (zh) | 2012-06-15 | 2013-05-07 | An evaluation method for a semiconductor substrate, a semiconductor substrate for evaluation, and a semiconductor device |
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CN (1) | CN104303280B (ja) |
DE (1) | DE112013002978B4 (ja) |
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JP5967019B2 (ja) * | 2013-05-31 | 2016-08-10 | 信越半導体株式会社 | 半導体ウェーハの評価方法 |
CN104766809B (zh) * | 2015-03-27 | 2017-11-21 | 西交利物浦大学 | 一种pn结瞬时电容能谱测量方法和*** |
JP6413938B2 (ja) * | 2015-06-05 | 2018-10-31 | 信越半導体株式会社 | 半導体基板の評価方法 |
JP7135998B2 (ja) * | 2019-05-08 | 2022-09-13 | 信越半導体株式会社 | エピタキシャルウェーハの評価方法 |
JP7176483B2 (ja) * | 2019-06-24 | 2022-11-22 | 信越半導体株式会社 | 半導体基板の評価方法および評価用半導体基板 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0467646A (ja) * | 1990-07-09 | 1992-03-03 | Mitsubishi Materials Corp | 半導体材料の結晶評価方法 |
KR930006735B1 (ko) | 1991-02-28 | 1993-07-23 | 삼성전자 주식회사 | 바이씨모스장치의 제조방법 |
JP3250158B2 (ja) | 1992-09-14 | 2002-01-28 | 三菱マテリアル株式会社 | Pn接合のリーク電流の解析方法 |
JP2978345B2 (ja) | 1992-11-26 | 1999-11-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH07201974A (ja) | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH1131725A (ja) * | 1997-05-15 | 1999-02-02 | Komatsu Denshi Kinzoku Kk | シリコンウェーハの評価方法及びシリコンウェーハ |
JP2001077168A (ja) * | 1999-09-08 | 2001-03-23 | Toshiba Corp | 半導体基板の評価方法並びに半導体基板及び半導体装置 |
JP2001274108A (ja) * | 2000-03-24 | 2001-10-05 | Toshiba Corp | 半導体基板およびその製造方法 |
JP3741086B2 (ja) * | 2002-07-04 | 2006-02-01 | 株式会社デンソー | 絶縁分離型半導体装置のための評価用半導体基板及び絶縁不良評価方法 |
KR100448915B1 (ko) * | 2002-07-26 | 2004-09-16 | 삼성전자주식회사 | 고전압 출력회로의 풀업 트랜지스터 어레이 |
JP2004127968A (ja) * | 2002-09-30 | 2004-04-22 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US6924531B2 (en) | 2003-10-01 | 2005-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | LDMOS device with isolation guard rings |
US6960056B2 (en) * | 2003-10-17 | 2005-11-01 | Deere & Company | Geometry for a sugar cane loader boom including a top-supported swivel mast |
JP2006310495A (ja) * | 2005-04-27 | 2006-11-09 | Sharp Corp | 半導体集積回路ウェハ、その試験方法および半導体集積回路部品の製造方法 |
US7868422B2 (en) | 2005-11-16 | 2011-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | MOS device with a high voltage isolation structure |
JP2008103598A (ja) * | 2006-10-20 | 2008-05-01 | Shin Etsu Handotai Co Ltd | 半導体ウエーハの評価方法 |
US8008696B2 (en) * | 2008-06-26 | 2011-08-30 | International Business Machines Corporation | Band gap modulated optical sensor |
JP4978583B2 (ja) * | 2008-08-01 | 2012-07-18 | 信越半導体株式会社 | 評価用ウエーハ及びその製造方法並びに半導体ウエーハの評価方法 |
US8329499B2 (en) * | 2008-12-10 | 2012-12-11 | Truesense Imaging, Inc. | Method of forming lateral overflow drain and channel stop regions in image sensors |
JP5343721B2 (ja) * | 2009-06-12 | 2013-11-13 | 信越半導体株式会社 | シリコン基板の評価方法及び半導体デバイスの製造方法 |
JP2011100964A (ja) | 2009-10-08 | 2011-05-19 | Hoya Corp | 半導体装置及びその製造方法 |
JP5434491B2 (ja) * | 2009-11-09 | 2014-03-05 | 信越半導体株式会社 | 半導体基板の評価方法及び半導体デバイスの製造方法 |
DE102010030766A1 (de) * | 2010-06-30 | 2012-01-05 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Teststruktur zum Steuern des Einbaus von Halbleiterlegierungen in Transistoren, die Metallgateelektrodenstrukturen mit großem Σ aufweisen |
US9070652B2 (en) * | 2012-04-13 | 2015-06-30 | United Microelectronics Corp. | Test structure for semiconductor process and method for monitoring semiconductor process |
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CN104303280B (zh) | 2016-12-28 |
WO2013187140A1 (ja) | 2013-12-19 |
KR101943067B1 (ko) | 2019-01-28 |
TW201350881A (zh) | 2013-12-16 |
DE112013002978B4 (de) | 2019-05-29 |
KR20150030637A (ko) | 2015-03-20 |
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JP2014003060A (ja) | 2014-01-09 |
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