KR920008891A - 금속박막의 평탄화 형성방법 - Google Patents

금속박막의 평탄화 형성방법 Download PDF

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Publication number
KR920008891A
KR920008891A KR1019900017093A KR900017093A KR920008891A KR 920008891 A KR920008891 A KR 920008891A KR 1019900017093 A KR1019900017093 A KR 1019900017093A KR 900017093 A KR900017093 A KR 900017093A KR 920008891 A KR920008891 A KR 920008891A
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KR
South Korea
Prior art keywords
thin film
metal thin
depositing
contact hole
film
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Application number
KR1019900017093A
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English (en)
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KR930005238B1 (ko
Inventor
조경수
고철기
김헌도
Original Assignee
정몽헌
현대전자산업 주식회사
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=19305142&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR920008891(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019900017093A priority Critical patent/KR930005238B1/ko
Priority to US07/780,891 priority patent/US5200030A/en
Priority to JP3275591A priority patent/JP2587335B2/ja
Publication of KR920008891A publication Critical patent/KR920008891A/ko
Application granted granted Critical
Publication of KR930005238B1 publication Critical patent/KR930005238B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음.

Description

금속박막의 평탄화 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 도전층 상부에 콘택홀이 형성된 절연막을 도시한 단면도.
제2도는 콘택홀 및 절연막 상부에 제1금속박막이 증착된 것을 도시한 단면도.
제3도는 제1금속박막 상부에 제2금속박막이 증착되어 평탄화된 것을 도시한 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 도전층 2 : 절연층
3 : 제1금속박막 4 : 제2금속박막
10 : 콘택홀

Claims (6)

  1. 도전층 상부에 콘택홀이 형성된 절연막을 형성하고 절연막 및 콘택홀에 금속박막을 증착하여 금속박막이 평탄화되도록 형성하는 방법에 있어서, 상기 절연막 및 콘택홀 상부에 소정의 챔버내에서 150℃ 이하의 온도조건에서 제1금속박막을 전체금속 박막 두께의 30% 증착시키는 단계와, 또다른 챔버로 이동하여 상기 제1금속박막 상부에 400℃ 이상의 조건에서 제2금속박막을 전체 금속 박막 두께의 70% 정도를 증착하는 단계로 이루어져 상기 콘택홀 및 절연막 상부에서 금속박막이 평탄하게 되는 것을 특징으로 하는 금속박막의 평탄화 형성방법.
  2. 제1항에 있어서, 상기 제1금속박막을 증착하는 단계전에 400℃ 이상에서 상기 절연막 및 콘택홀에 약 2분정도 가스분출(Degassing)시킨다음 상온으로 낮추는 것을 특징으로 하는 금속박막의 평탄화 형성방법.
  3. 제1항에 있어서, 상기 제2금속박막을 증착하는 단계전체 400℃ 이상에서 상기 제1금속박막을 약 1분정도 가열시키는 것을 특징으로 하는 금속박막의 평탄화 형성방법.
  4. 제1항에 있어서, 상기 제1금속박막을 소정의 챔버에서 증착하고, 제2금속박막을 또다른 챔버내에서 증착하는 단계는 스퍼터링 장비를 이용하여 연속적으로 실시되는 것을 특징으로 하는 금속박막의 평탄화 형성방법.
  5. 제1항에 있어서, 상기 도전층을 산화막을 질화물을 사용되는 것을 특징으로 하는 금속박막의 평탄화 형성방법.
  6. 제1항에 있어서, 상기 제1금속박막 및 제2금속박막은 알루미늄 또는 알루미늄 합금을 사용하는 것을 특징으로 하는 금속박막의 평탄화 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900017093A 1990-10-25 1990-10-25 금속박막의 평탄화 형성방법 KR930005238B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019900017093A KR930005238B1 (ko) 1990-10-25 1990-10-25 금속박막의 평탄화 형성방법
US07/780,891 US5200030A (en) 1990-10-25 1991-10-23 Method for manufacturing a planarized metal layer for semiconductor device
JP3275591A JP2587335B2 (ja) 1990-10-25 1991-10-23 金属薄膜の平坦化形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900017093A KR930005238B1 (ko) 1990-10-25 1990-10-25 금속박막의 평탄화 형성방법

Publications (2)

Publication Number Publication Date
KR920008891A true KR920008891A (ko) 1992-05-28
KR930005238B1 KR930005238B1 (ko) 1993-06-16

Family

ID=19305142

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Application Number Title Priority Date Filing Date
KR1019900017093A KR930005238B1 (ko) 1990-10-25 1990-10-25 금속박막의 평탄화 형성방법

Country Status (3)

Country Link
US (1) US5200030A (ko)
JP (1) JP2587335B2 (ko)
KR (1) KR930005238B1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5346587A (en) * 1993-08-12 1994-09-13 Micron Semiconductor, Inc. Planarization of a gate electrode for improved gate patterning over non-planar active area isolation
US5432073A (en) * 1993-09-27 1995-07-11 United Microelectronics Corporation Method for metal deposition without poison via
JP3382031B2 (ja) * 1993-11-16 2003-03-04 株式会社東芝 半導体装置の製造方法
JPH07245343A (ja) * 1994-03-03 1995-09-19 Toshiba Corp 半導体装置及びその製造方法
US5658830A (en) * 1996-07-12 1997-08-19 Vanguard International Semiconductor Corporation Method for fabricating interconnecting lines and contacts using conformal deposition
JP2000150653A (ja) * 1998-09-04 2000-05-30 Seiko Epson Corp 半導体装置の製造方法
KR100433846B1 (ko) 2001-05-23 2004-06-04 주식회사 하이닉스반도체 반도체장치의 금속도전막 형성방법
KR100439475B1 (ko) * 2001-09-28 2004-07-09 삼성전자주식회사 금속층 적층방법 및 장치
US20060009030A1 (en) * 2004-07-08 2006-01-12 Texas Instruments Incorporated Novel barrier integration scheme for high-reliability vias
CN107275278A (zh) * 2016-04-07 2017-10-20 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4508609A (en) * 1983-09-26 1985-04-02 Exxon Research & Engineering Co. Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets
US4631806A (en) * 1985-05-22 1986-12-30 Gte Laboratories Incorporated Method of producing integrated circuit structures
US4812419A (en) * 1987-04-30 1989-03-14 Hewlett-Packard Company Via connection with thin resistivity layer
JPS6467963A (en) * 1987-09-09 1989-03-14 Hitachi Ltd Semiconductor integrated circuit device
JPS6473745A (en) * 1987-09-16 1989-03-20 Fujitsu Ltd Semiconductor device and manufacture thereof
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten

Also Published As

Publication number Publication date
KR930005238B1 (ko) 1993-06-16
US5200030A (en) 1993-04-06
JP2587335B2 (ja) 1997-03-05
JPH04264729A (ja) 1992-09-21

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