JPS6467963A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6467963A JPS6467963A JP62223915A JP22391587A JPS6467963A JP S6467963 A JPS6467963 A JP S6467963A JP 62223915 A JP62223915 A JP 62223915A JP 22391587 A JP22391587 A JP 22391587A JP S6467963 A JPS6467963 A JP S6467963A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon layer
- polycrystalline silicon
- seed
- dose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent the connection resistance of aluminum wirings to a substrate from increasing by forming a section for connecting metal wirings on the substrate of an amorphous silicon layer or a polycrystalline silicon layer thereby to eliminate that it becomes the seed of an epitaxial growth. CONSTITUTION:Si ions are implanted to the exposed surfaces of N<+> type source, drain 8 and P<+> type source, drain 10 from connecting holes 12 to form amorphous layers 14 or polycrystalline silicon layers 14. The energy of ion implantation may be approx. 10-100keV, and its dose may be 5X10<13>-5X10<14>atoms/cm<2>. Since a crystal structure on a substrate 1 may be broken, the energy and the dose are not required to be finely controlled,, and the amorphous silicon layer 14 or the polycrystalline silicon layer 14 may be formed by a simple method. Thus, the exposed surface from the hole 12 of the substrate 1 does not become the seed of growing an epitaxial layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62223915A JPS6467963A (en) | 1987-09-09 | 1987-09-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62223915A JPS6467963A (en) | 1987-09-09 | 1987-09-09 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6467963A true JPS6467963A (en) | 1989-03-14 |
Family
ID=16805706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62223915A Pending JPS6467963A (en) | 1987-09-09 | 1987-09-09 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6467963A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04264729A (en) * | 1990-10-25 | 1992-09-21 | Hyundai Electron Ind Co Ltd | Flattening and formation method of metal thin film |
-
1987
- 1987-09-09 JP JP62223915A patent/JPS6467963A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04264729A (en) * | 1990-10-25 | 1992-09-21 | Hyundai Electron Ind Co Ltd | Flattening and formation method of metal thin film |
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