KR910015144A - 매체 호출 제어기 - Google Patents

매체 호출 제어기 Download PDF

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Publication number
KR910015144A
KR910015144A KR1019900022361A KR900022361A KR910015144A KR 910015144 A KR910015144 A KR 910015144A KR 1019900022361 A KR1019900022361 A KR 1019900022361A KR 900022361 A KR900022361 A KR 900022361A KR 910015144 A KR910015144 A KR 910015144A
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KR
South Korea
Prior art keywords
data
input
input data
units
stored
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KR1019900022361A
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English (en)
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KR100216857B1 (ko
Inventor
제트. 데소우자 에드윈
제이.시미노 다니엘
쉬라니 라민(엔엠아이)
알. 와그고너 마크
Original Assignee
존 지.웨브
내셔날 세미컨덕터 코포레이션
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Publication of KR910015144A publication Critical patent/KR910015144A/ko
Priority to KR1019990002810A priority Critical patent/KR100250784B1/ko
Priority to KR1019990002812A priority patent/KR100250785B1/ko
Application granted granted Critical
Publication of KR100216857B1 publication Critical patent/KR100216857B1/ko

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462—LAN interconnection over a bridge based backbone
    • H04L12/4625—Single bridge functionality, e.g. connection of two networks over a single bridge
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/7453—Address table lookup; Address filtering using hashing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Computer And Data Communications (AREA)

Abstract

내용 없음

Description

매체 호출 제어기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 단순화된 기능적인 블록 다이어 그램 형태로 본 발명에 따른 매체 호출 제어기를 예시한 도면, 제7도는 단순화된 기능적인 블록 다이어 그램 형태로 본 발명에 따른 호출 제어기의 내용 주소화 기억장치를 예시한 도면, 제8도는 논리 및 계략적인 다이어 그램 형태로 본 발명에 따른 매체 호출 제어기의 내용 주소와 기억장치(CAM)에 사용되는 CAM셀을 예시한 도면.

Claims (4)

  1. 복수개의 2진 비트를 각기 포함하는 복수개의 데이타 단위를 저장하여 다른 데이타 단위와 비교하는 내용 주소화 기억 장치에 있어서, 각기 상호 유일한 것일 수 있는 복수개의 기준 데이타 단위를 미리 저장하는 복수개의 기준 데이타 저장 수단, 입력 데이타 단위를 각기 저장하는 복수개의 입력 데이타 저장 수단, 상기 저장된 입력 데이타 단위를 상기 복수개의 미리 저장된 기준 데이타 단위중 각각의 기준 데이타 단위와 동시에 비교하는 복수개의 데이타 비교 수단, 상기 저장된 입력 데이타 단위가 상기 복수개의 미리 저장된 기준 데이타 단위중 어느한 기준 데이타 단위와 정합하는지를 나타내는 정합 표시 수단을 포함하는 내용 주소화 기억장치.
  2. 입력 데이타를 수신하는 데이타 수신 수단 및 상기 수신된 데이타를 저장하는 데이타 저장 수단을 지니는 네트워크 브리지에 있어서, 기준 데이타를 미리 저장하는 데이타 저장수단, 상기 미리 저장된 기준 데이타와 비교하도록 상기입력데이타를 이 입력 데이타의 상태에 의존하여 선택적으로 인출하는 데이타 인출수단, 상기 인출된 입력 데이타를 상기 미리 저장된 기준 데이타와 배교하는 데이타 비교 수단, 상기 인출된 입력 데이타가 상기 미리 저장된 기준 데이타와 정합하는 차를 나타내는 데이타 표시 수단, 상기 인출된 데이타가 상기 미리 저장된 기준 데이타와 정합하는 지를 기초로하며 더우기 입력 데이타를 선택적으로 거부하는 데이타 거부 수단을 포함하는 네트워크 브리지.
  3. 입력 데이타 신호를 지니며 입력 익스클루시브-OR게이트를 포함하는 복수개의 익스클루시브-OR 게이트 및 복수개의 스프트 레지스터를 구비하는 순환 여유 검사 회로에 있어서, 상기 익스클루시브-OR 게이트의 출력이 선택적으로 상기 익스클루시브-OR게이트의 활성 입력 다음에 오도록 동작상 연결되는 복수개의 AND게이트, 상기 입력 데이타 신호가 상기 입력 익스클루시브-OR게이트를 바이패스할 수 있도록 동작상 연결되는 멀티플렉서를 포함하는 순환 여유 검사 회로.
  4. 바이트 크기 단위로 입력 데이타를 저장하는 선입선출 기억 장치에 있어서, 관련된 유효성 표시 요소를 각기 지니는 저장된 입력 데이타 바이트 각각이 유효한 데이타를 표시하는지를 나타내도록 복수개의 유효성 표시 요소를 생성하는 유효 수단, 상기 저장된 입력 데이타 바이트가 유효한 데이타를 표시하는 지를 나타내도록 유효성 표시 요소를 지니는 그러한 저장 입력 데이타 바이트만을 판독하는 데이타 판독수단을 포함하는 선입 선출 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900022361A 1990-01-02 1990-12-29 내용 어드레스 메모리 장치 KR100216857B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019990002810A KR100250784B1 (ko) 1990-01-02 1999-01-29 컴퓨터 네트워크 브리지 회로
KR1019990002812A KR100250785B1 (ko) 1990-01-02 1999-01-29 선입 선출 메모리 회로

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45943990A 1990-01-02 1990-01-02
US459,439 1995-06-02

Related Child Applications (2)

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KR1019990002812A Division KR100250785B1 (ko) 1990-01-02 1999-01-29 선입 선출 메모리 회로
KR1019990002810A Division KR100250784B1 (ko) 1990-01-02 1999-01-29 컴퓨터 네트워크 브리지 회로

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KR910015144A true KR910015144A (ko) 1991-08-31
KR100216857B1 KR100216857B1 (ko) 1999-09-01

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US (2) US5164943A (ko)
EP (1) EP0436194A3 (ko)
JP (1) JPH04211851A (ko)
KR (1) KR100216857B1 (ko)

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Also Published As

Publication number Publication date
US5379289A (en) 1995-01-03
KR100216857B1 (ko) 1999-09-01
EP0436194A2 (en) 1991-07-10
JPH04211851A (ja) 1992-08-03
US5164943A (en) 1992-11-17
EP0436194A3 (en) 1992-12-16

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