KR910001949A - 무플래그 리드프레임, 피키지 및 방법 - Google Patents

무플래그 리드프레임, 피키지 및 방법 Download PDF

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Publication number
KR910001949A
KR910001949A KR1019900009448A KR900009448A KR910001949A KR 910001949 A KR910001949 A KR 910001949A KR 1019900009448 A KR1019900009448 A KR 1019900009448A KR 900009448 A KR900009448 A KR 900009448A KR 910001949 A KR910001949 A KR 910001949A
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South Korea
Prior art keywords
leads
semiconductor die
leadframe
flagless
device package
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KR1019900009448A
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English (en)
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리 올슨 티모시
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빈센트 죠셉 로너
모토로라 인코포레이티드
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Publication of KR910001949A publication Critical patent/KR910001949A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
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    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

내용 없음

Description

무플래그 리드프레임, 피키지 및 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 무플래그 리드프레임의 확대된 상부도.
제2도는 제1도의 리드프레임을 이용하는 반도체 소자 패키지의 확대된 횡단면도.

Claims (3)

  1. 다수의 리드를 가진 무플래그 리드프레임으로서, 반도체 다이가 상기 다수의 리드에 부착되도록 하여 상기 반도체 다이의 후면에 대해 표면 영역의 50%가 상기 다수의 리드에 열적으로 결합되며, 몇몇 또는 모두 상기 다수의 리드가 상기 반도체 다이에 열적으로 및 전기적으로 결합되게 한 무플래그 리드프레임.
  2. 반도체 소자 패키지에 있어서, 다수의 리드를 가진 무플래그 리드프레임과, 반도체 다이의 후면에 대해 표면영역의 50%가 상기 다수의 리드에 열적으로 결합되며 상기 다수 리드의 몇몇 또는 모든 리드가 상기 반도체 다이에 열적으로 및 전기적으로 결합되도록 상기 다수의 리드에 결합된 상기 반도체 다이와, 상기 다수 리드의 부분이 인캡슐레이션에서부터 연장되는 상기 반도체 다이 및 상기 리드프레임에 대해 배열된 상기 인캡슐레이션을 구비하여 이루어지는 반도체 소자 패키지.
  3. 반도체 소자 패키지 제조방법에 있어서, 다수의 리드를 가진 무플래그 리드프레임을 제공하는 단계와, 상기 반도체 다이의 후면에 대해 표면 영역의 최소50%가 상기 다수의 리드에 열적으로 결합되도록 상기 리드프레임의 상기 다수 리드에 반도체 다이를 결합하는 단계와, 상기 리드프레임의 상기 다수 리드에 상기 반도체 다이를 전기적으로 접속하는 단계와, 상기 다수 리드의 일부분이 인캡슐레이션에서부터 연장하도록 상기 반도체 다이와 상기 리드프레임을 인캡슐레이트 하는 단계를 구비하여 이루어지는 반도체 소자 패키지 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900009448A 1989-06-29 1990-06-26 무플래그 리드프레임, 피키지 및 방법 KR910001949A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37312889A 1989-06-29 1989-06-29
US373,128 1989-06-29

Publications (1)

Publication Number Publication Date
KR910001949A true KR910001949A (ko) 1991-01-31

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ID=23471089

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Application Number Title Priority Date Filing Date
KR1019900009448A KR910001949A (ko) 1989-06-29 1990-06-26 무플래그 리드프레임, 피키지 및 방법

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EP (1) EP0405330A3 (ko)
JP (1) JPH0338057A (ko)
KR (1) KR910001949A (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168345A (en) * 1990-08-15 1992-12-01 Lsi Logic Corporation Semiconductor device having a universal die size inner lead layout
JPH04120765A (ja) * 1990-09-12 1992-04-21 Seiko Epson Corp 半導体装置とその製造方法
JP2735509B2 (ja) * 1994-08-29 1998-04-02 アナログ デバイセス インコーポレーテッド 改善された熱放散を備えたｉｃパッケージ
WO1996013855A1 (en) * 1994-10-27 1996-05-09 National Semiconductor Corporation A leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die
DE10146306A1 (de) * 2001-09-19 2003-01-02 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens einem Halbleiterchip und Verfahren zu seiner Herstellung
US7109573B2 (en) * 2003-06-10 2006-09-19 Nokia Corporation Thermally enhanced component substrate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716761A (en) * 1972-05-03 1973-02-13 Microsystems Int Ltd Universal interconnection structure for microelectronic devices
CA1238119A (en) * 1985-04-18 1988-06-14 Douglas W. Phelps, Jr. Packaged semiconductor chip
US4740868A (en) * 1986-08-22 1988-04-26 Motorola Inc. Rail bonded multi-chip leadframe, method and package
JPH01161743A (ja) * 1987-12-17 1989-06-26 Toshiba Corp 半導体装置

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EP0405330A2 (en) 1991-01-02
EP0405330A3 (en) 1992-05-06

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