KR860003605A - 반도체 메모리 장치 - Google Patents
반도체 메모리 장치 Download PDFInfo
- Publication number
- KR860003605A KR860003605A KR1019850007619A KR850007619A KR860003605A KR 860003605 A KR860003605 A KR 860003605A KR 1019850007619 A KR1019850007619 A KR 1019850007619A KR 850007619 A KR850007619 A KR 850007619A KR 860003605 A KR860003605 A KR 860003605A
- Authority
- KR
- South Korea
- Prior art keywords
- shift register
- data
- transfer
- portions
- random access
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 210000000078 claw Anatomy 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제7도는 본 발명의 양호한 실시예의 도면.
제8도는 본 발명의 다른 실시예의 도면.
제9도는 (a) RAM으로 부터 쉬프트 레지스터로의 전송, 그리고 (b) 쉬프트 레지스터로 부터 RAM으로의 전송을 설명하기 위한 파형도.
Claims (1)
- 랜돔 억세스 메모리 부분과, 상기 랜덤 억세스 메모리 부분과 쉬프트 레지스터간의 상호 랜돔 억세스메모리 부분의 데이타의 한 워드라인양의 평행 전송을 가능하게 하기 위한 쉬프트 레지스터로서, 상기 쉬프트 레지스터는 다수의 쉬프트 레지스터 부분들로 분할되며, 직렬입력 데이타는 멀티플렉서의 동작에 의해 상기 쉬프트 레지스터 부분들간에 교호로 분포되며, 직렬 출력 데이타는 다른 멀티플렉서의 동작에 의해 상기 쉬프트 레지스터로 부터 교호로 데이타를 인출하여 얻어지는 그러한 쉬프트 레지스터와, 평행이송을 수행하기 위해 상기 랜돔 억세스 메모리부분과 상기 쉬프트 레지스터사이에 삽입되는 전송게이트부분으로서, 상기 전송게이트 부분은 상기 랜돔 억세스 메모리 부분에서 인접한 짝수 비트라인 및 홀수 비트라인 중 하나의 상기 쉬프트 레지스터 부분들의 각단들의 입력 및 출력 단자들을 선택적으로 연결해 주기 위한 다수의 전송게이트들의 그룹들로 구성되며, 상기 다수의 전송게이트 그룹들은 쉬프트 클로신호들에 상응하여 스위치되는 그러한 전송게이트 부분을 포함하는 것이 특징인 반도체 메모리장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59-216785 | 1984-10-16 | ||
JP59216785A JPS6194295A (ja) | 1984-10-16 | 1984-10-16 | 半導体記憶装置 |
JP216785 | 1984-10-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR860003605A true KR860003605A (ko) | 1986-05-28 |
KR900007996B1 KR900007996B1 (ko) | 1990-10-23 |
Family
ID=16693848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850007619A KR900007996B1 (ko) | 1984-10-16 | 1985-10-16 | 반도체 메모리장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4773045A (ko) |
EP (1) | EP0178922B1 (ko) |
JP (1) | JPS6194295A (ko) |
KR (1) | KR900007996B1 (ko) |
DE (1) | DE3578254D1 (ko) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63276138A (ja) * | 1987-04-30 | 1988-11-14 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | レジスタ・フアイル |
US5200925A (en) * | 1988-07-29 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Serial access semiconductor memory device and operating method therefor |
NL8802125A (nl) * | 1988-08-29 | 1990-03-16 | Philips Nv | Geintegreerde geheugenschakeling met parallelle en seriele in- en uitgang. |
DE3832328A1 (de) * | 1988-09-23 | 1990-03-29 | Broadcast Television Syst | Speicheranordnung fuer digitale signale |
US5161221A (en) * | 1988-12-12 | 1992-11-03 | Eastman Kodak Company | Multi-memory bank system for receiving continuous serial data stream and monitoring same to control bank switching without interrupting continuous data flow rate |
GB8925723D0 (en) * | 1989-11-14 | 1990-01-04 | Amt Holdings | Processor array system |
US4984214A (en) * | 1989-12-05 | 1991-01-08 | International Business Machines Corporation | Multiplexed serial register architecture for VRAM |
JP2592986B2 (ja) * | 1990-09-29 | 1997-03-19 | 株式会社東芝 | 半導体記憶装置 |
JP2753129B2 (ja) * | 1990-10-02 | 1998-05-18 | 株式会社東芝 | 半導体記憶装置 |
US10973397B2 (en) | 1999-03-01 | 2021-04-13 | West View Research, Llc | Computerized information collection and processing apparatus |
US8636648B2 (en) | 1999-03-01 | 2014-01-28 | West View Research, Llc | Endoscopic smart probe |
US7914442B1 (en) | 1999-03-01 | 2011-03-29 | Gazdzinski Robert F | Endoscopic smart probe and method |
US8068897B1 (en) | 1999-03-01 | 2011-11-29 | Gazdzinski Robert F | Endoscopic smart probe and method |
KR100385228B1 (ko) | 2001-04-18 | 2003-05-27 | 삼성전자주식회사 | 불휘발성 메모리를 프로그램하는 방법 및 장치 |
US10318904B2 (en) | 2016-05-06 | 2019-06-11 | General Electric Company | Computing system to control the use of physical state attainment of assets to meet temporal performance criteria |
EP3939044A1 (en) * | 2019-05-16 | 2022-01-19 | Xenergic AB | Shiftable memory and method of operating a shiftable memory |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51147225A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Semiconductor memory |
US4151609A (en) * | 1977-10-11 | 1979-04-24 | Monolithic Memories, Inc. | First in first out (FIFO) memory |
US4321695A (en) * | 1979-11-23 | 1982-03-23 | Texas Instruments Incorporated | High speed serial access semiconductor memory with fault tolerant feature |
US4330852A (en) * | 1979-11-23 | 1982-05-18 | Texas Instruments Incorporated | Semiconductor read/write memory array having serial access |
US4347587A (en) * | 1979-11-23 | 1982-08-31 | Texas Instruments Incorporated | Semiconductor integrated circuit memory device with both serial and random access arrays |
US4281401A (en) * | 1979-11-23 | 1981-07-28 | Texas Instruments Incorporated | Semiconductor read/write memory array having high speed serial shift register access |
US4412313A (en) * | 1981-01-19 | 1983-10-25 | Bell Telephone Laboratories, Incorporated | Random access memory system having high-speed serial data paths |
JPS6194296A (ja) * | 1984-10-16 | 1986-05-13 | Fujitsu Ltd | 半導体記憶装置 |
-
1984
- 1984-10-16 JP JP59216785A patent/JPS6194295A/ja active Pending
-
1985
- 1985-10-16 DE DE8585307459T patent/DE3578254D1/de not_active Expired - Fee Related
- 1985-10-16 KR KR1019850007619A patent/KR900007996B1/ko not_active IP Right Cessation
- 1985-10-16 US US06/788,000 patent/US4773045A/en not_active Expired - Fee Related
- 1985-10-16 EP EP85307459A patent/EP0178922B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0178922A2 (en) | 1986-04-23 |
EP0178922B1 (en) | 1990-06-13 |
DE3578254D1 (de) | 1990-07-19 |
EP0178922A3 (en) | 1988-03-30 |
KR900007996B1 (ko) | 1990-10-23 |
US4773045A (en) | 1988-09-20 |
JPS6194295A (ja) | 1986-05-13 |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |