KR20070003652A - 트랜지스터 및 트랜지스터 제조 방법 - Google Patents
트랜지스터 및 트랜지스터 제조 방법 Download PDFInfo
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- KR20070003652A KR20070003652A KR1020060060225A KR20060060225A KR20070003652A KR 20070003652 A KR20070003652 A KR 20070003652A KR 1020060060225 A KR1020060060225 A KR 1020060060225A KR 20060060225 A KR20060060225 A KR 20060060225A KR 20070003652 A KR20070003652 A KR 20070003652A
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Abstract
Description
Claims (5)
- 반도체 기판상에 제공된 소자 형성 영역;절연막으로 형성되어, 상기 소자 형성 영역을 한정하는 소자 분리막;상기 소자 형성 영역에 형성된 게이트 절연물; 및상기 게이트 절연물상에 형성되어, 상기 소자 분리막상에서 연재하는 게이트 전극을 포함하며,상기 게이트 전극이 연재하는 상기 소자 분리막의 표면은, 상기 게이트 절연물의 표면보다 두께 방향으로 더 높게 형성되며,상기 소자 분리막과 상기 게이트 절연물과의 사이의 경계에서의 상기 게이트 전극의 두께는, 상기 경계로부터 상기 게이트 절연물 측을 향하여 떨어진 위치에서의 상기 게이트 전극의 두께보다 더 큰, 트랜지스터.
- 반도체 기판상에 제공된 소자 형성 영역;절연막으로 형성되어, 상기 소자 형성 영역을 한정하는 소자 분리막;상기 소자 형성 영역에 형성된 게이트 절연물; 및상기 게이트 절연물상에 형성되어, 상기 소자 분리막상에서 연재하는 게이트 전극을 포함하며,상기 게이트 전극이 연재하는 상기 소자 분리막의 표면은, 상기 게이트 절연물의 표면보다 두께 방향으로 더 높게 형성되며,상기 소자 분리막은, 평면도로 관측할 때, 상기 소자 분리막이 상기 게이트 절연물과 인접한 경계에서보다 내측에 제공되는, 상기 경계에서보다 두께 방향으로 더 높게 형성되어 상기 반도체 기판의 평면 방향으로 연재하는 평탄부를 가지며,상기 게이트 전극이 연재하는 상기 소자 분리막의 표면과 상기 게이트 절연물의 표면과의 사이의 높이 차 (A), 상기 소자 분리막의 상기 평탄부의 선단으로부터 상기 경계까지의 가로 방향의 거리 (B), 및 상기 소자 형성 영역의 상기 게이트 전극의 두께 (D) 가 다음의 수식 (1), 즉,D > B … (1)과 수식 (2), 즉A/D+(1-(B/D)2)0.5 > 1 … (2)를 만족하는, 트랜지스터.
- 제 1 항 또는 제 2 항에 있어서,상기 소자 형성 영역의 상기 반도체 기판의 상기 표면 근방에 불순물을 부가하여, 상기 소자 형성 영역이, 상기 소자 분리막으로부터 더 먼 부분에서보다 상기 소자 분리막에 더 근접한 부분에서 더 높은 농도를 갖는, 트랜지스터.
- 반도체 기판상에 제 1 산화물을 형성하는 단계;상기 제 1 산화물상에 질화물을 형성하는 단계;상기 반도체 기판에 도달하도록, 상기 질화물과 상기 제 1 산화물을 통해 연재하는 트렌치를 형성하는 단계;상기 트렌치에 노출된 상기 반도체 기판의 표면상에 제 2 산화물을 형성하는 단계;상기 트렌치를 채우며, 상기 질화물의 표면과 실질적으로 동일 평면에 있는표면을 갖는 제 1 절연막을 형성하는 단계;상기 반도체 기판의 상기 표면이 노출되도록 상기 질화물과 상기 제 1 산화물을 제거하는 단계;상기 반도체 기판의 상기 노출면 상에 제 2 절연막을 형성하는 단계;다음의 수식 (3), 즉D > B … (3)과, 수식 (4), 즉A/D+(1-(B/D)2)0.5 > 1 … (4)를 만족하도록, 상기 제 1 절연막과 상기 제 2 절연막상에 전기 도전층을 형성하는 단계; 및이온 주입 프로세스로, 상기 도전층과 상기 제 2 절연막을 통해, 상기 반도체 기판에 불순물을 도입하는 제 1 불순물 부가 단계를 포함하며,상기 수식에서, A 는, 상기 도전층이 연재하는 상기 제 1 절연막의 표면과 상기 제 2 절연막의 표면과의 사이의 높이 차를 나타내며, B 는, 상기 제 1 절연막 이 상기 제 2 절연막과 인접한 경계로부터, 평면도로 관측할 때, 상기 경계보다 내측에 제공되는, 상기 경계에서보다 두께 방향으로 더 높게 형성되어 평면 방향으로 연재하는 평탄부의 선단까지의 가로 방향의 거리를 나타내며, D 는, 상기 제 2 절연막상의 상기 도전층의 두께를 나타내는, 트랜지스터 제조 방법.
- 제 4 항에 있어서,주입 에너지, 불순물 주입량 및 불순물 중 적어도 하나가 상기 제 1 불순물 부가 단계의 이온 주입 프로세스와 다른 이온 주입 프로세스로, 상기 반도체 기판에 불순물을 도입하는 제 2 불순물 부가 단계를 더 포함하는, 트랜지스터 제조 방법.
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JPJP-P-2005-00193782 | 2005-07-01 | ||
JP2005193782A JP2007012988A (ja) | 2005-07-01 | 2005-07-01 | トランジスタ及びトランジスタの製造方法 |
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US8642441B1 (en) * | 2006-12-15 | 2014-02-04 | Spansion Llc | Self-aligned STI with single poly for manufacturing a flash memory device |
US8785291B2 (en) | 2011-10-20 | 2014-07-22 | International Business Machines Corporation | Post-gate shallow trench isolation structure formation |
US8466496B2 (en) | 2011-11-17 | 2013-06-18 | International Business Machines Corporation | Selective partial gate stack for improved device isolation |
CN107611168B (zh) * | 2017-08-24 | 2020-07-10 | 长江存储科技有限责任公司 | 一种消除体效应中窄沟道效应影响的mos器件结构 |
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JP3127893B2 (ja) | 1998-07-07 | 2001-01-29 | 日本電気株式会社 | 半導体装置および半導体装置の製造方法 |
US6277697B1 (en) * | 1999-11-12 | 2001-08-21 | United Microelectronics Corp. | Method to reduce inverse-narrow-width effect |
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- 2006-06-29 TW TW095123555A patent/TWI325637B/zh not_active IP Right Cessation
- 2006-06-30 KR KR1020060060225A patent/KR100804458B1/ko active IP Right Grant
- 2006-07-03 US US11/478,854 patent/US7560775B2/en active Active
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TWI325637B (en) | 2010-06-01 |
US7560775B2 (en) | 2009-07-14 |
KR100804458B1 (ko) | 2008-02-20 |
US20070023792A1 (en) | 2007-02-01 |
JP2007012988A (ja) | 2007-01-18 |
TW200707743A (en) | 2007-02-16 |
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