KR20030049309A - Method for forming a silicide of semiconductor device - Google Patents
Method for forming a silicide of semiconductor device Download PDFInfo
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- KR20030049309A KR20030049309A KR1020010079489A KR20010079489A KR20030049309A KR 20030049309 A KR20030049309 A KR 20030049309A KR 1020010079489 A KR1020010079489 A KR 1020010079489A KR 20010079489 A KR20010079489 A KR 20010079489A KR 20030049309 A KR20030049309 A KR 20030049309A
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- Prior art keywords
- silicide
- cobalt
- titanium
- heat treatment
- forming
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 45
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 32
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 33
- 239000010941 cobalt Substances 0.000 claims abstract description 33
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 21
- 239000010936 titanium Substances 0.000 claims abstract description 21
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 10
- NNSIWZRTNZEWMS-UHFFFAOYSA-N cobalt titanium Chemical compound [Ti].[Co] NNSIWZRTNZEWMS-UHFFFAOYSA-N 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000010408 film Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 239000010409 thin film Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- -1 silicide compound Chemical class 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
Abstract
Description
본 발명은 반도체 소자용 실리사이드에 관한 것으로, 더욱 상세하게는 낮은 접촉 저항과 안정된 콘택 저항을 실현하는데 적합한 반도체 소자의 실리사이드 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to silicides for semiconductor devices, and more particularly, to a silicide formation method of semiconductor devices suitable for realizing low contact resistance and stable contact resistance.
잘 알려진 바와 같이, 반도체 장치가 고 집적화 되어감에 따라 게이트의 폭과 소오스 및 드레인 영역으로 이용되어질 불순물 영역이 감소되고 있는 추세이며,이에 수반하여 반도체 장치에서는 불순물 영역에서의 접촉 저항과 게이트에서의 시트 저항이 증가하여 동작 속도가 저하되는 현상이 야기되고 있는 실정이다.As is well known, as semiconductor devices have been highly integrated, the width of gates and impurity regions to be used as source and drain regions are decreasing. Accordingly, in semiconductor devices, contact resistances at the impurity regions and gates are reduced. It is a situation that the phenomenon that the operating speed is lowered due to the increase in sheet resistance.
따라서, 반도체 장치 내 소자들의 전극을 알루미늄 합금, 텅스텐 등의 저 저항 물질로 형성하거나 혹은 게이트 전극을 다결정 실리콘으로 형성하는 경우 그 상부에 실리사이드 층을 형성하여 저항을 감소시키며, 이와 같이 게이트 전극 상에 실리사이드 층을 형성할 때, 접촉 저항을 감소시키기 위하여, 소오스/드레인 영역으로 사용되어질 불순물 영역의 표면에도 실리사이드 층을 형성하고 있다.Therefore, when the electrodes of the elements in the semiconductor device are formed of a low resistance material such as aluminum alloy or tungsten or the gate electrode is formed of polycrystalline silicon, a silicide layer is formed on the gate electrode to reduce the resistance. In forming the silicide layer, in order to reduce the contact resistance, the silicide layer is also formed on the surface of the impurity region to be used as the source / drain region.
일반적으로, 게이트 전극(다결정 실리콘) 상에 형성되는 실리사이드로는 티타늄 실리사이드가 주로 이용, 즉 스퍼터링 등의 방법을 이용하여 티타늄 금속을 증착하고, 급속 열처리 공정을 수행하여 금속과 실리콘을 반응시킴으로써, 티타늄 실리사이드를 형성하는데, 이러한 티타늄 실리사이드의 경우, 다결정 실리콘 박막의 배선폭이 어느 한계치보다 작을 경우에는, 대략적으로 0.2㎛ 정도, 티타늄 실리사이드 형성이 다결정 실리콘 상에서 균일하게 형성되지 못하게 되는 단점을 갖는다.In general, as the silicide formed on the gate electrode (polycrystalline silicon), titanium silicide is mainly used, that is, titanium metal is deposited using a method such as sputtering, and a rapid heat treatment process is performed to react the metal and silicon, thereby In the case of forming the silicide, in the case of such a titanium silicide, when the wiring width of the polycrystalline silicon thin film is smaller than a certain limit, about 0.2 μm, titanium silicide formation is not uniformly formed on the polycrystalline silicon.
즉, 종래 방법에 따라 티타늄 실리사이드를 형성하는 경우, 일 예로서 도 3에 도시된 바와 같이, 다결정 실리콘(302)의 일정 지역이 티타늄 실리사이드(306)로 되지 못하고 실리콘(308)으로 존재하게 되는 문제가 있으며, 설혹 실리콘(308)이 티타늄을 포함하더라도 그 양이 극히 미량이 되기 때문에 그로 인해 접촉 저항이 증가하게 되는 문제점을 갖는다. 도 3에 있어서, 미설명 참조번호 304는 결정립을 나타낸다.That is, in the case of forming the titanium silicide according to the conventional method, as shown in FIG. 3 as an example, a problem that a certain region of the polycrystalline silicon 302 does not become the titanium silicide 306 but exists as the silicon 308 Even if the silicon 308 contains titanium, the amount thereof is extremely small, thereby causing a problem of increasing contact resistance. In Fig. 3, reference numeral 304 denotes a crystal grain.
다른 한편으로, 티타늄 실리사이드 대신에 코발트 실리사이드를 채용하는 경우가 있는데, 이 경우 다결정 실리콘 박막의 배선폭이 대략 0.1㎛ 정도까지 코발트 실리사이드가 균일하게 형성된다는 장점을 가지나 티타늄 실리사이드보다 자체 저항치가 크기 때문에 접촉 저항이 커지는 문제점을 여전히 내포하고 있다.On the other hand, cobalt silicide is sometimes used instead of titanium silicide. In this case, the cobalt silicide is uniformly formed up to about 0.1 μm in the width of the polycrystalline silicon thin film. There is still a problem of increased resistance.
따라서, 본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로, 낮은 접촉 저항과 안정된 콘택 저항을 유지할 수 있는 반도체 소자용 실리사이드 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a silicide forming method for a semiconductor device capable of maintaining the low contact resistance and stable contact resistance.
상기 목적을 달성하기 위하여 본 발명은, 반도체 기판의 소정 부분에 형성되며, 측벽 스페이서를 갖는 게이트 전극과 소오스/드레인 영역의 상부에 실리사이드를 형성하는 방법에 있어서, 상기 반도체 기판의 상부 전면에 티타늄 금속막을 형성하는 과정; 상기 반도체 기판을 제1열처리하여 상기 티타늄 금속막과 게이트 전극 및 소오스/드레인 영역 실리콘의 실리사이드화 반응에 의한 티타늄 실리사이드를 형성하는 과정; 상기 반도체 기판 상부에 잔류하는 미반응 티타늄 금속막을 제거한 후, 상기 반도체 기판을 제2열처리하여 상기 티타늄 실리사이드를 저저항화하는 과정; 상기 반도체 기판 전면에 코발트 금속막을 형성하는 과정; 상기 반도체 기판을 제3열처리하여 상기 코발트 금속막과 티타늄 실리사이드 및 게이트 전극, 소오스/드레인 영역 실리콘의 실리사이드화 반응에 의한 코발트 티타늄 실리사이드 및 코발트 실리사이드를 형성하는 과정; 상기 반도체 기판을 제4열처리하여 상기 코발트 티타늄 실리사이드 및 코발트 실리사이드를 저저항화하는 과정을 포함하는반도체 소자의 실리사이드 형성 방법을 제공한다.In order to achieve the above object, the present invention is formed on a predetermined portion of the semiconductor substrate, a method of forming a silicide on the gate electrode having a sidewall spacer and the source / drain region, the titanium metal on the upper front surface of the semiconductor substrate Forming a film; First heat treating the semiconductor substrate to form titanium silicide by silicideation of the titanium metal film, the gate electrode, and the source / drain region silicon; Removing the unreacted titanium metal film remaining on the semiconductor substrate, and then performing a second heat treatment on the semiconductor substrate to lower the titanium silicide; Forming a cobalt metal film on the entire surface of the semiconductor substrate; Performing a third heat treatment of the semiconductor substrate to form cobalt titanium silicide and cobalt silicide by silicideation of the cobalt metal film, titanium silicide and gate electrode, and source / drain region silicon; It provides a method of forming a silicide of a semiconductor device comprising a fourth heat treatment of the semiconductor substrate to reduce the cobalt titanium silicide and cobalt silicide.
도 1a 내지 1e는 본 발명의 바람직한 실시 예에 따라 반도체 소자용 실리사이드를 형성하는 주요 과정을 도시한 공정 순서도,1A to 1E are process flowcharts illustrating a main process of forming a silicide for a semiconductor device according to a preferred embodiment of the present invention;
도 2는 본 발명에 따라 반도체 소자용 실리사이드를 형성할 때 코발트 실리사이드와 티타늄 실리사이드가 동시에 존재하는 구조를 보여주는 도면,2 is a view showing a structure in which cobalt silicide and titanium silicide exist simultaneously when forming a silicide for a semiconductor device according to the present invention;
도 3은 종래 방법에 따라 반도체 소자용 실리사이드를 형성할 때 다결정 실리콘의 일정 지역이 실리콘으로 존재하는 구조를 보여주는 도면.3 is a view showing a structure in which a predetermined region of polycrystalline silicon exists as silicon when forming silicide for a semiconductor device according to a conventional method.
본 발명의 상기 및 기타 목적과 여러 가지 장점은 첨부된 도면을 참조하여 하기에 기술되는 본 발명의 바람직한 실시 예로부터 더욱 명확하게 될 것이다.The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1e는 본 발명의 바람직한 실시 예에 따라 반도체 소자용 실리사이드를 형성하는 주요 과정을 도시한 공정 순서도이다.1A to 1E are flowcharts illustrating a main process of forming silicide for a semiconductor device according to a preferred embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(102) 상에 게이트 절연막 형성용 산화막과 게이트 전극용 다결정 실리콘을 순차 형성한 후 포토리쏘그라피(photolithography) 공정을 이용하여 다결정 실리콘과 산화막을 패터닝(patterning)함으로써 게이트 절연막(104)과 게이트 전극(106)을 형성하고, 게이트 전극(106)과 게이트 절연막(104)의 노출된 측벽 부분에 질화막 등으로 이루어진 측벽 스페이서(108)를 형성한다.Referring to FIG. 1A, a gate film is formed by sequentially forming an oxide film for forming a gate insulating film and polycrystalline silicon for a gate electrode on a semiconductor substrate 102, and then patterning the polycrystalline silicon and the oxide film using a photolithography process. An insulating film 104 and a gate electrode 106 are formed, and sidewall spacers 108 made of a nitride film or the like are formed in the exposed sidewall portions of the gate electrode 106 and the gate insulating film 104.
이때, 도면에서의 도시는 생략하였으나, 이온 주입 마스크를 이용하는 이온 주입 공정을 수행하여 저농도 또는 고농도의 불순물을 반도체 기판(102)의 소오스/드레인 영역에 주입함으로써, 반도체 소자의 소오스/드레인을 형성한다.In this case, although not shown in the drawing, a source or a drain of the semiconductor device is formed by performing an ion implantation process using an ion implantation mask to inject impurities of low or high concentration into the source / drain regions of the semiconductor substrate 102. .
다음에, 도 1b에 도시한 바와 같이, 스퍼터링 등과 같은 증착 공정에 의해 반도체 기판(102)의 상부 전면에 걸쳐 박막, 예를 들면 200Å 내지 600Å의 두께(바람직하게는, 400Å)를 갖는 박막의 티타늄 금속층(110)을 형성한다.Next, as shown in FIG. 1B, a thin film of titanium having a thickness (for example, 400 kPa) of a thin film, for example, 200 kPa to 600 kPa over the entire upper surface of the semiconductor substrate 102 by a deposition process such as sputtering or the like. The metal layer 110 is formed.
이어서, 급속 열처리 공정, 예를 들면 650℃ 내지 850℃의 온도 조건과 질소 분위기에서 대략 10초 내지 60초 동안(보다 바람직하게는, 750℃의 온도 조건에서 30초 동안) 급속 열처리 공정을 수행함으로써, 티타늄 금속층(110)을 실리사이드화, 즉 티타늄과 실리콘을 화학 반응시켜 실리사이드화시킨다. 이때, 반도체 기판(102)의 상부, 보다 상세하게는 소오스/드레인 영역의 상부와 다결정 실리콘인 게이트 전극(106)의 상부에 존재하는 티타늄 금속층(110)은 티타늄과 실리콘의 화학 반응에 의해 실리사이드화(즉, 실리사이드 화합물)되는 반면에 질화막인 측벽 스페이서(108) 상부에 존재하는 티타늄 금속층(110)은 실리사이드화되지 않는다.Then, by performing a rapid heat treatment process, for example, a rapid heat treatment process for about 10 seconds to 60 seconds (more preferably, for 30 seconds at a temperature condition of 750 ℃) in a temperature condition of 650 ℃ to 850 ℃ and nitrogen atmosphere The titanium metal layer 110 is silicided, that is, the silicide is formed by chemical reaction between titanium and silicon. At this time, the titanium metal layer 110 existing on the semiconductor substrate 102, more specifically, on the source / drain regions and on the gate electrode 106, which is polycrystalline silicon, is silicided by a chemical reaction between titanium and silicon. (I.e., a silicide compound) while the titanium metal layer 110 on the sidewall spacer 108, which is a nitride film, is not silicided.
다음에, 도 1c에 도시한 바와 같이, 식각 공정 등을 통해 반도체 기판(102) 상부에 잔류하는 실리사이드화 되지 않은 미반응 티타늄 금속층을 제거한다. 그러면, 게이트 전극(106)의 상부와 반도체 기판(102)내 소오스/드레인 영역의 상부에만 티타늄 실리사이드(110a, 110b)가 남게 된다. 그리고, 이때 형성된 게이트 전극()과 소오스/드레인 영역의 반도체 기판(102)에 형성된 티타늄 실리사이드(110a. 110b)는 저항이 높으므로 850℃ 내지 920℃의 온도 조건과 질소 분위기에서 대략 10초 내지 30초 동안(보다 바람직하게는, 900℃에서 10초 동안) 재차 열처리 공정을 수행하여 낮은 저항을 갖는 티타늄 실리사이드()로 상(phase) 변이되도록 한다.Next, as shown in FIG. 1C, the unsilicided unreacted titanium metal layer remaining on the semiconductor substrate 102 is removed through an etching process or the like. Then, the titanium silicides 110a and 110b remain only at the top of the gate electrode 106 and at the top of the source / drain regions in the semiconductor substrate 102. In this case, the titanium silicides 110a and 110b formed on the semiconductor substrate 102 in the source / drain region and the gate electrode formed at this time have a high resistance, and thus, are about 10 seconds to about 30 seconds in a temperature condition of 850 ° C to 920 ° C and nitrogen atmosphere. The heat treatment process is performed again for seconds (more preferably, at 10O < 0 > C for 10 seconds) to cause phase transition to titanium silicide () having low resistance.
다음에, 도 1d에 도시한 바와 같이, 스퍼터링 등과 같은 증착 공정을 수행하여 티타늄 실리사이드(110a, 110b)가 형성된 반도체 기판(102)의 상부 전면에 걸쳐 박막, 예를 들면 50Å 내지 200Å의 두께(바람직하게는, 100Å)를 갖는 박막의 코발트 금속층(112)을 형성한다.Next, as illustrated in FIG. 1D, a thin film, for example, 50 μm to 200 μm (preferably 50 μm to 200 μm over the entire upper surface of the semiconductor substrate 102 on which the titanium silicides 110a and 110b are formed by performing a deposition process such as sputtering or the like, is preferable. Preferably, a thin cobalt metal layer 112 having a thickness of 100 μs) is formed.
이어서, 급속 열처리 공정, 예를 들면 400℃ 내지 600℃의 온도 조건과 질소 분위기에서 대략 10초 내지 60초 동안(보다 바람직하게는, 500℃의 온도 조건에서 30초 동안) 급속 열처리 공정을 수행함으로써, 코발트 금속층(112)을 실리사이드화, 즉 코발트와 실리콘을 화학 반응시켜 실리사이드화시킨다. 이때, 티타늄 실리사이드(110a, 110b)의 상부에 존재하는 코발트 금속층(112)은 코발트와 실리콘의 반응 및 코발트와 티타늄 실리사이드의 반응에 의해 실리사이드화(즉, 실리사이드 화합물)되는 반면에 질화막인 측벽 스페이서(108) 상부에 존재하는 코발트 금속층(112)은 실리사이드화되지 않는다.Subsequently, by performing a rapid heat treatment process, for example, a rapid heat treatment process at a temperature condition of 400 ° C. to 600 ° C. and a nitrogen atmosphere for about 10 seconds to 60 seconds (more preferably, for 30 seconds at a temperature condition of 500 ° C.) The cobalt metal layer 112 is silicided, that is, the silicide is formed by chemical reaction between cobalt and silicon. At this time, the cobalt metal layer 112 present on the titanium silicides 110a and 110b is silicided (ie, a silicide compound) by the reaction of cobalt and silicon and the reaction of cobalt and titanium silicide, while the sidewall spacers, which are nitride layers, 108) The cobalt metal layer 112 present on top is not suicided.
다음에, 도 1e에 도시한 바와 같이, 식각 공정을 통해 실리사이드화되지 않은 미반응 코발트 금속층을 제거함으로써 티타늄 실리사이드(110a, 110b) 상부에만 코발트 티타늄 실리사이드 및 코발트 실리사이드(112a, 112b)가 남게 된다. 그리고, 이때 형성된 코발트 티타늄 실리사이드 및 코발트 실리사이드(112a, 112b)는 높은 저항을 가지고 있으므로, 800℃ 내지 920℃의 온도 조건과 질소 분위기에서 대략 10초 내지 50초 동안(보다 바람직하게는, 850℃의 온도에서 30초 동안) 열처리 공정을 재차 수행함으로써 낮은 저항을 가진 코발트 실리사이드를 완성한다.Next, as shown in FIG. 1E, cobalt titanium silicide and cobalt silicide 112a and 112b remain only on the titanium silicide 110a and 110b by removing the unreacted cobalt metal layer through an etching process. In addition, the cobalt titanium silicide and cobalt silicides 112a and 112b formed at this time have high resistance, and thus, for about 10 to 50 seconds (more preferably, at 850 ° C.) under a temperature condition of 800 ° C. to 920 ° C. and a nitrogen atmosphere. Cobalt silicide with low resistance is completed by performing the heat treatment process again for 30 seconds at temperature).
이때, 본 실시 예에 따라 형성되는 반도체 소자의 실리사이드는, 도 2에 도시된 바와 같이, 티타늄/코발트 실리사이드(206)와 코발트 실리사이드(208)가 혼재하는 형태로 존재하는 구조를 가지면서 실리사이드화되지 않은 실리콘 영역이 존재하지 않으므로 종래에 비해 낮은 접촉 저항과 안정된 콘택 저항을 얻을 수가 있으며, 이를 통해 반도체 소자의 제품 신뢰도를 대폭적으로 증진시킬 수 있다. 즉, 종래 티타늄 실리사이드 형성에 있어서 실리사이드화 되지 않고 잔류하는 실리콘 영역(도 3의 308)이 본 발명에서는 코발트 금속층에 의해 완전히 실리사이드화되므로 균일한 반도체 소자의 실리사이드 형성이 가능하여 낮은 접촉 저항과 안정된 콘택 저항을 얻을 수 있다. 도 2에 있어서, 미설명 참조번호 202는 다결정 실리콘을 나타내고, 204는 결정립을 나타낸다.In this case, as shown in FIG. 2, the silicide of the semiconductor device formed according to the present embodiment may not be silicided while having a structure in which titanium / cobalt silicide 206 and cobalt silicide 208 are present in a mixed form. Since there is no silicon region, low contact resistance and stable contact resistance can be obtained as compared with the related art, thereby greatly improving product reliability of the semiconductor device. That is, in the conventional titanium silicide formation, the silicon region (308 of FIG. 3) remaining without being silicided is completely silicided by the cobalt metal layer in the present invention, so that silicide formation of a uniform semiconductor device is possible, resulting in low contact resistance and stable contact. Resistance can be obtained. In Fig. 2, reference numeral 202 denotes polycrystalline silicon, and 204 denotes crystal grains.
한편, 본 발명의 실시예는, 티타늄 또는 코발트 금속을 증착한 후 실리사이드화를 위한 급속 열처리를 수행하기 전에, 열처리 시의 티타늄(또는 코발트, 탄탈륨) 산화를 방지할 수 있도록 그 상부에 티타늄 나이트라이드 등과 같은 박막(예를 들면, 100Å 내지 300Å)의 리프렉토리 금속(산화 방지용 금속)을 증착한 후에 열처리 공정을 수행하도록 설정할 수도 있으며, 이러한 기술적 수단을 통해 반도체 소자의 제품 신뢰도를 더욱 증진시킬 수 있다.On the other hand, the embodiment of the present invention, after depositing the titanium or cobalt metal and before performing the rapid heat treatment for silicidation, titanium nitride on the upper portion to prevent the oxidation of titanium (or cobalt, tantalum) during the heat treatment It is also possible to set to perform a heat treatment process after depositing a thin film (for example, 100 kPa to 300 kPa) of a repository metal (antioxidation metal), and through this technical means, it is possible to further improve product reliability of semiconductor devices. .
다른 한편, 본 발명의 실시 예는 티타늄 실리사이드의 저저항화를 위한 열처리를 수행하였지만, 이와는 달리 코발트 실리사이드 형성 이후 저저항화를 위한 열처리 공정과 동시에 진행할 수도 있다.On the other hand, the embodiment of the present invention performed a heat treatment for the low resistance of the titanium silicide, alternatively, it may proceed simultaneously with the heat treatment process for the low resistance after cobalt silicide formation.
이상 설명한 바와 같이 본 발명에 따르면, 단일의 티타늄 또는 코발트 금속을 이용하여 반도체 소자용 실리사이드를 형성하는 종래 방법과는 달리, 서로 다른 두 종류의 금속 물질을 이용하여 혼합 실리사이드를 형성, 즉 실리콘 기판 상에 제 1 금속 물질을 증착한 후 급속 가열시켜 제 1 실리사이드를 형성하고, 이어서 제 1금속 물질과는 다른 종류의 제 2 금속 물질을 증착한 후 급속 가열시켜 제 1 실리사이드 상에 제 2 실리사이드를 형성하는 두 단계의 공정을 통해 게이트 전극과 소오스/드레인 영역 상에 혼합 실리사이드를 형성하도록 함으로써, 낮은 접촉 저항과 안정된 콘택 저항을 확보하여 반도체 소자의 제품 신뢰도를 증진시킬 수 있다.As described above, according to the present invention, unlike the conventional method of forming silicides for semiconductor devices using a single titanium or cobalt metal, mixed silicides are formed using two different metal materials, that is, on a silicon substrate. Depositing a first metal material on the substrate and rapidly heating to form a first silicide, followed by depositing a second metal material of a different type from the first metal material and then rapidly heating to form a second silicide on the first silicide By forming a mixed silicide on the gate electrode and the source / drain regions through a two-step process, low contact resistance and stable contact resistance may be ensured to improve product reliability of the semiconductor device.
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KR100591176B1 (en) * | 2004-05-28 | 2006-06-19 | 동부일렉트로닉스 주식회사 | Silicide formation method of semiconductor device |
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KR100591176B1 (en) * | 2004-05-28 | 2006-06-19 | 동부일렉트로닉스 주식회사 | Silicide formation method of semiconductor device |
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