KR100334866B1 - Transistor Formation Method of Semiconductor Device - Google Patents
Transistor Formation Method of Semiconductor Device Download PDFInfo
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- KR100334866B1 KR100334866B1 KR1019980059551A KR19980059551A KR100334866B1 KR 100334866 B1 KR100334866 B1 KR 100334866B1 KR 1019980059551 A KR1019980059551 A KR 1019980059551A KR 19980059551 A KR19980059551 A KR 19980059551A KR 100334866 B1 KR100334866 B1 KR 100334866B1
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- Prior art keywords
- melting point
- point metal
- high melting
- forming
- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 230000008018 melting Effects 0.000 claims abstract description 27
- 238000002844 melting Methods 0.000 claims abstract description 27
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- 239000010936 titanium Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 4
- 229910021341 titanium silicide Inorganic materials 0.000 description 22
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로,The present invention relates to a method of forming a transistor of a semiconductor device,
자기정렬적인 실리사이드 형성공정을 진행하기 전에 게이트전극의 실리콘막 상부에 고융점금속을 형성하고 후속공정으로 게이트전극 상측과 소오스/드레인 접합 영역 상측에 자기정렬적인 실리사이드를 형성할 때 상기 기 증착된 고융점금속의 두께와 합쳐져 게이트전극 상측에 두꺼운 두께의 고융점금속 실리사이드가 형성되도록 함으로써 반도체소자의 고속화 및 고집적화를 가능하게 하는 기술이다.Prior to the self-aligned silicide forming process, a high melting point metal is formed on the silicon film of the gate electrode, and in the subsequent process, the self-aligned silicide is formed on the gate electrode and the source / drain junction region. The high melting point metal silicide having a thick thickness is formed on the gate electrode in combination with the thickness of the melting point metal, thereby enabling high speed and high integration of the semiconductor device.
Description
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 특히 고속화된 반도체소자의 구동이 가능하도록 낮은 저항의 게이트전극을 형성할 수 있도록 하되, 트랜지스터의 특성열화를 방지할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transistor of a semiconductor device, and more particularly, to a technique of enabling the formation of a low resistance gate electrode so as to drive a semiconductor device at a high speed, and preventing the deterioration of transistor characteristics.
일반적으로, 반도체소자의 게이트전극은 도핑된 다결정실리콘이 가장 많이 사용된다.In general, doped polysilicon is most used as a gate electrode of a semiconductor device.
이러한 다결정실리콘을 이용한 게이트전극은 공정이 안정하다는 장점이 있지만 다결정실리콘의 높은 비저항으로 인해 디자인룰 ( design rule ) 이 작아짐에 따라 소자의 동작속도 향상에 문제가 된다.The gate electrode using the polysilicon has the advantage that the process is stable, but due to the high specific resistance of the polysilicon, the design rule is reduced, which causes a problem in improving the operation speed of the device.
이러한 문제점을 해결하기 위하여, 비저항이 낮은 텅스텐 등의 고융점금속을 게이트전극으로 사용하는 방법이 제안되고 있다.In order to solve this problem, a method of using a high melting point metal such as tungsten having a low specific resistance as a gate electrode has been proposed.
도 1 은 종래기술에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도로서, 티타늄 실리사이드를 게이트전극 상측과 소오스/드레인 접합영역에 자기정렬적으로 형성하는 경우를 도시한다.FIG. 1 is a cross-sectional view illustrating a method of forming a transistor of a semiconductor device according to the prior art, and illustrates a case in which titanium silicide is self-aligned on the gate electrode and a source / drain junction region.
먼저, 반도체기판(31)의 비활성영역 상측에 소자분리막(32)을 형성한다.First, the device isolation layer 32 is formed on the inactive region of the semiconductor substrate 31.
그리고, 상기 반도체기판(31)의 활성영역에 게이트산화막(33), 게이트전극용 다결정실리콘막(34)의 적층구조를 형성한다.A stack structure of a gate oxide film 33 and a polysilicon film 34 for a gate electrode is formed in an active region of the semiconductor substrate 31.
그리고, 상기 적층구조를 게이트전극 마스크(도시안됨)를 이용한 식각공정으로 식각하여 게이트전극을 형성한다.The stacked structure is etched by an etching process using a gate electrode mask (not shown) to form a gate electrode.
그리고, 상기 게이트전극을 마스크로하여 상기 반도체기판(31)에 저농도의 불순물을 이온주입하여 저농도의 불순물 접합영역(35)을 형성하고, 상기 게이트전극 측벽에 절연막 스페이서(36)를 형성한다.A low concentration of impurity junction region 35 is formed by ion implantation of low concentration of impurities into the semiconductor substrate 31 using the gate electrode as a mask, and an insulating film spacer 36 is formed on sidewalls of the gate electrode.
그리고, 상기 게이트전극과 절연막스페이서(36)를 마스크로하여 상기 반도체기판(31)에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역(37)을 형성한다.A high concentration of impurities are implanted into the semiconductor substrate 31 using the gate electrode and the insulating layer spacer 36 as a mask to form a high concentration impurity junction region 37.
그리고, 상기 반도체기판(31)의 노출된 활성영역과 다결정실리콘막(34) 상측에 자기정렬적으로 선택적인 티타늄 실리사이드막(38)을 형성한다. (도 1)In addition, a titanium silicide film 38 that is self-aligned selectively is formed on the exposed active region of the semiconductor substrate 31 and on the polycrystalline silicon film 34. (Figure 1)
일반적으로, 게이트전극은 저항이 낮을수록 좋기 때문에 가능하면 두꺼운 두께의 티타늄 실리사이드가 필요하다.In general, the lower the resistance, the better the gate electrode, so thick titanium silicide is required if possible.
그러나, 소오스/드레인 접합영역의 상부는 두꺼운 티타늄 실리사이드가 형성되면 티타늄과 실리콘의 반응이 불균일하고 소오스/드레인 접합영역 깊이로 티타늄 실리사이드가 침투하기 때문에 접합누설전류가 커지는 치명적인 문제가 있다. 또한, 티타늄 실리사이드를 두껍게 형성하게 되면 게이트전극과 소오스/드레인 접합영역 상부에 형성된 티타늄 실리사이드가 접속되는 문제가 발생된다.However, when the thick titanium silicide is formed at the top of the source / drain junction region, the reaction between titanium and silicon is uneven and titanium silicide penetrates deep into the source / drain junction region, thereby causing a fatal problem in that the junction leakage current increases. In addition, when the titanium silicide is formed thick, the titanium silicide formed on the gate electrode and the source / drain junction region is connected.
그리하여, 종래기술에서는 자기정렬적으로 티타늄 실리사이드를 사용할 때 얇은 두께만을 사용하였으며, 이는 고집적 소자로 갈수록 더 낮은 게이트 저항을 요구하는 반도체소자를 충족시키지 못하는 문제점이 있다.Therefore, the conventional art uses only a thin thickness when using titanium silicide in the self-alignment, which is a problem that does not meet the semiconductor device that requires a lower gate resistance toward higher integration devices.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트전극 상측의 고융점금속은 두껍게 형성하고 소오스/드레인 접합영역 상측의 고융점금속은 얇게 형성하여 반도체소자의 고속화와 고집적화를 가능하게 하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, the high melting point metal on the gate electrode is formed thick and the high melting point metal on the source / drain junction region is formed thin to enable a high speed and high integration of the semiconductor device It is an object of the present invention to provide a method for forming a transistor in a device.
도 1 은 종래기술에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단며도.1 is a diagram showing a method of forming a transistor of a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.2A to 2D are cross-sectional views showing a transistor forming method of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1,31 : 반도체기판 2,32 : 소자분리막1,31: semiconductor substrate 2,32: device isolation film
3,33 : 게이트산화막 4,34 : 다결정실리콘막3,33 gate oxide film 4,34 polycrystalline silicon film
5 : 게이트전극용 제1티타늄막 6 : 마스크절연막5: first titanium film for gate electrode 6: mask insulating film
7,36 : 절연막 스페이서 8 : 소오스/드레인 접합영역7,36: insulating film spacer 8: source / drain junction region
9 : 제2티타늄막 10,38 : 티타늄 실리사이드9: 2nd titanium film 10, 38: titanium silicide
35 : 저농도의 불순물 접합영역 37 : 고농도의 불순물 접합영역35: low concentration impurity junction region 37: high concentration impurity junction region
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
반도체기판 상에 게이트산화막, 다결정실리콘층, 제1고융점금속 및 마스크 절연막을 적층구조를 형성하는 공정과,Forming a stacked structure of a gate oxide film, a polycrystalline silicon layer, a first high melting point metal and a mask insulating film on a semiconductor substrate;
게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막 패턴, 제1고융점금속층 패턴, 다결정실리콘층패턴 및 게이트산화막패턴으로 되는 게이트전극을 형성하는 공정과,Forming a gate electrode including a mask insulating layer pattern, a first high melting point metal layer pattern, a polysilicon layer pattern, and a gate oxide layer pattern by etching the stack structure using a gate electrode mask as an etch mask;
상기 게이트전극을 마스크로하는 저농도의 불순물을 이온주입공정으로 LDD 영역을 형성하는 공정과,Forming an LDD region using an ion implantation process of a low concentration of impurities using the gate electrode as a mask;
상기 마스크 절연막 패턴을 제거하는 공정과,Removing the mask insulating film pattern;
상기 게이트전극 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on the sidewalls of the gate electrode;
상기 반도체기판에 고농도의 불순물을 이온주입하여 소오스/드레인 접합영역을 형성하는 공정과,Forming a source / drain junction region by ion implanting a high concentration of impurities into the semiconductor substrate;
전체표면 상부에 제2고융점금속을 증착하는 공정과,Depositing a second high melting point metal on the entire surface;
상기 구조를 열처리하여 게이트전극의 표면과 소오스/드레인 접합영역 상에 고융점금속 실리사이드막을 형성하는 공정과,Heat-treating the structure to form a high melting point metal silicide film on the surface of the gate electrode and the source / drain junction region;
상기 제2고융점금속의 남은 부분을 제거하는 공정을 포함하는 것과,Removing the remaining portion of the second high melting point metal;
상기 도프드 실리콘막은 500 - 3000 Å 두께로 형성하는 것과,The doped silicon film is formed to a thickness of 500 to 3000 mm 3,
상기 제1고융점금속과 제2고융점금속은 티탄늄, 코발트, 몰리브덴, 니켈 및 텅스텐 등과 같이 실리사이드화될 수 있는 금속을 사용하는 것과,The first high melting point metal and the second high melting point metal may be silicided metals such as titanium, cobalt, molybdenum, nickel and tungsten, and the like.
상기 제1고융점금속은 스퍼터링방법으로 100 - 1000 Å 두께 형성하는 것과,The first high melting point metal is formed by the sputtering method 100-1000 Å thickness,
상기 열처리공정은 600 - 900 ℃ 온도에서 RTP 방법으로 실시하는 것과,The heat treatment step is performed by the RTP method at 600-900 ℃ temperature,
상기 실리사이드 형성공정을 소오스/드레인 접합영역 형성공정 전에 실시하는 것과,Performing the silicide forming step before the source / drain junction region forming step;
상기 고융점금속 실리사이드는 고융점금속 실리사이드를 타켓으로 하여 스퍼터링이나 화학기상증착방법으로 형성하는 것과,The high melting point metal silicide is formed by sputtering or chemical vapor deposition using a high melting point metal silicide as a target;
상기 게이트산화막 상부에 실리콘막, 티타늄막 및 실리콘막의 적층구조를 형성하고 자기정렬적인 실리사이드 형성공정을 실시하는 것을 특징으로 한다.Forming a stacked structure of a silicon film, a titanium film and a silicon film on the gate oxide film, characterized in that the self-aligned silicide forming process.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 자기정렬적인 티타늄 실리사이드 형성공정을 진행하기 전에 게이트전극의 다결정실리콘 상부에 티타늄을 형성하고 후속공정으로 게이트전극 상측과 소오스/드레인 접합영역 상측에 자기정렬적인 티타늄 실리사이드를 형성할 때 상기 티타늄의 두께와 합쳐져 게이트전극 상측에 높은 티타늄 실리사이드가 형성되도록 하는 것이다. 이때, 상기 티타늄 실리사이드는 텅스텐, 코발트, 니켈 또는 몰리브덴 등과 같이 실리사이드를 형성할 수 있는 다른 물질을 이용하여 다른 물질의 실리사이드를 형성할 수도 있다.On the other hand, the principle of the present invention for achieving the above object is to form a titanium on the polysilicon top of the gate electrode before proceeding the self-aligned titanium silicide forming process, and in the subsequent process on the gate electrode and the source / drain junction region When forming the self-aligned titanium silicide is combined with the thickness of the titanium so that a high titanium silicide is formed on the gate electrode. In this case, the titanium silicide may form silicide of another material by using another material capable of forming silicide such as tungsten, cobalt, nickel, or molybdenum.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a transistor forming method of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(1)의 비활성영역에 소자분리막(2)을 형성한다.First, the device isolation film 2 is formed in an inactive region of the semiconductor substrate 1.
그리고, 전체표면상부에 게이트산화막(3), 게이트전극용 다결정실리콘막(4),게이트전극용 제1티타늄막(5) 및 마스크절연막(6)을 적층한다.Then, the gate oxide film 3, the polycrystalline silicon film 4 for the gate electrode, the first titanium film 5 for the gate electrode 5, and the mask insulating film 6 are laminated on the entire surface.
이때, 상기 다결정실리콘막(4)은 불순물이 도핑된 500 - 3000 Å 두께로 형성되고, 상기 제1티타늄막(5)은 스퍼터링방법으로 100 - 1000 Å 두께 형성된다. (도 2a)In this case, the polysilicon film 4 is formed to have a thickness of 500-3000 mm 3 doped with impurities, and the first titanium film 5 is formed to be 100-1000 mm thick by a sputtering method. (FIG. 2A)
그 다음, 상기 적층구조를 마스크로하여 상기 반도체기판(1)에 저농도의 불순물이온을 주입하여 저농도의 소오스/드레인 접합영역을 형성한다.Subsequently, a low concentration of source / drain junction region is formed by implanting a low concentration of impurity ions into the semiconductor substrate 1 using the stacked structure as a mask.
그리고, 상기 마스크절연막(6)을 제거하고 상기 게이트산화막(3) 다결정실리콘막(4) 및 제1티타늄막(5) 적층구조의 측벽에 절연막 스페이서(7)를 형성한다.Then, the mask insulating film 6 is removed, and the insulating film spacer 7 is formed on sidewalls of the gate oxide film 3 polycrystalline silicon film 4 and the first titanium film 5 stacked structure.
그리고, 상기 적층구조, 절연막 스페이서(7) 및 소자분리막(2)을 마스크로하여 상기 반도체기판(1)에 고농도의 불순물이온을 주입하여 LDD 구조의 소오스/드레인 접합영역(8)을 형성한다. (도 2b)The source / drain junction region 8 of the LDD structure is formed by implanting a high concentration of impurity ions into the semiconductor substrate 1 using the stacked structure, the insulating film spacer 7 and the device isolation film 2 as a mask. (FIG. 2B)
그 다음에, 전체표면상부에 제2티타늄막(9)을 일정두께 증착하고, 후속열공정으로 실리콘과 만나는 부분, 다시말하면 게이트전극의 다결정실리콘막(4) 및 반도체기판(1)에 접속되는 제2티타늄막(9)을 실리사이드화하여 티타늄 실리사이드(10)를 자기정렬적으로 형성한다.Then, the second titanium film 9 is deposited to a predetermined thickness on the entire surface, and is subsequently connected to silicon in the subsequent thermal process, that is, to the polysilicon film 4 and the semiconductor substrate 1 of the gate electrode. The second titanium film 9 is silicided to form the titanium silicide 10 in a self-aligned manner.
이때, 상기 게이트전극 상측에 형성된 제1티타늄막(5)도 실리사이드화되어 상기 게이트전극의 상측에 형성되는 티타늄 실리사이드(10)의 두께가 소오스/드레인 접합영역(8)에 형성된 티타늄 실리사이드(10)보다 두껍게 형성된다.At this time, the first titanium film 5 formed on the gate electrode is also silicided so that the thickness of the titanium silicide 10 formed on the gate electrode is formed in the source / drain junction region 8. It is formed thicker.
여기서, 상기 열처리공정은 600 - 900 ℃ 온도에서 RTP 방법으로 실시한다. (도 2c)Here, the heat treatment step is carried out by the RTP method at 600-900 ℃ temperature. (FIG. 2C)
그 다음에, 실리콘과 접속되지않은 부분에 남아있는 상기 제2티타늄막(9)을 제거하여 게이트전극 상측의 티타늄 실리사이드(10)를 두껍게 형성하고, 소오스/드레인 접합영역(8) 상측의 티타늄 실리사이드(10)는 얇게 형성한 트랜지스터를 형성한다. (도 2d)Then, the second titanium film 9 remaining in the portion not connected with silicon is removed to form a thick titanium silicide 10 on the upper side of the gate electrode, and titanium silicide on the source / drain junction region 8 above. (10) forms a thinly formed transistor. (FIG. 2D)
한편, 본 발명은 자기정렬적인 실리사이드 형성공정을 소오스/드레인 접합영역 형성공정 전에 실시할 수도 있다.In the meantime, the self-aligned silicide formation process may be performed before the source / drain junction region formation process.
그리고, 상기 자기정렬적인 실리사이드 형성공정은 텅스텐, 코발트, 니켈 또는 몰리브덴 등과 같이 실리사이드를 형성할 수 있는 다른 물질을 이용하여 다른 물질의 실리사이드를 형성할 수도 있다.In addition, the self-aligned silicide forming process may form silicides of other materials by using other materials capable of forming silicides such as tungsten, cobalt, nickel, or molybdenum.
그리고, 상기 티타늄 실리사이드는 티타늄 실리사이드 타켓을 이용하여 스퍼터링이나 화학기상증착방법으로 형성할 수도 있다.The titanium silicide may be formed by sputtering or chemical vapor deposition using a titanium silicide target.
또한, 상기 다결정실리콘막, 티타늄막 및 다결정실리콘막의 적층구조를 형성하고 그 상부에 자기정렬적인 실리사이드 형성공정을 실시할 수도 있다.In addition, a lamination structure of the polysilicon film, the titanium film, and the polysilicon film may be formed, and a self-aligned silicide forming process may be performed thereon.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 자기정렬적인 티타늄 실리사이드 형성공정을 진행하기 전에 게이트전극의 다결정실리콘 상부에 티타늄을 형성하고 후속공정으로 게이트전극 상측과 소오스/드레인 접합영역 상측에 자기정렬적인 티타늄 실리사이드를 형성할 때 상기 티타늄의 두께와 합쳐져 게이트전극 상측에 높은 티타늄 실리사이드가 형성되도록 함으로써 반도체소자의 고속화 및 고집적화를 가능하게 하는 효과가 있다.As described above, in the method of forming a transistor of a semiconductor device according to the present invention, before the process of forming a self-aligned titanium silicide, titanium is formed on the polysilicon of the gate electrode, and a source / drain junction is formed on the gate electrode at the subsequent process. When the self-aligned titanium silicide is formed on the region, high titanium silicide is formed on the gate electrode by being combined with the thickness of the titanium to enable high speed and high integration of the semiconductor device.
Claims (7)
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| JPH1065171A (en) * | 1996-06-25 | 1998-03-06 | Hyundai Electron Ind Co Ltd | Manufacture of mos transistor |
| KR19980057007A (en) * | 1996-12-30 | 1998-09-25 | 김영환 | Method for manufacturing field effect transistor of semiconductor device |
| KR19980055970A (en) * | 1996-12-28 | 1998-09-25 | 김영환 | Transistor manufacturing method |
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| JPS6266679A (en) * | 1985-09-19 | 1987-03-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH1065171A (en) * | 1996-06-25 | 1998-03-06 | Hyundai Electron Ind Co Ltd | Manufacture of mos transistor |
| KR19980055970A (en) * | 1996-12-28 | 1998-09-25 | 김영환 | Transistor manufacturing method |
| KR19980057007A (en) * | 1996-12-30 | 1998-09-25 | 김영환 | Method for manufacturing field effect transistor of semiconductor device |
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