KR100476702B1 - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR100476702B1 KR100476702B1 KR10-2000-0084735A KR20000084735A KR100476702B1 KR 100476702 B1 KR100476702 B1 KR 100476702B1 KR 20000084735 A KR20000084735 A KR 20000084735A KR 100476702 B1 KR100476702 B1 KR 100476702B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 무전해 도금법에 의해 구리 배선을 형성함에 있어, 구리 배선용 패턴이 형성된 절연층(dielectric layer) 위에 배리어 메탈층(barrier metal layer)을 형성하고, 가장자리 부분을 포함한 웨이퍼 뒷면을 활성화 용액에 담구어 활성화시킨 후 무전해 구리 도금액에 전체 웨이퍼를 담금으로써, 불순물이 없는 순도 높은 구리 도금막을 웨이퍼 앞면에 형성시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. In forming a copper wiring by an electroless plating method, a barrier metal layer is formed on a dielectric layer on which a copper wiring pattern is formed. A method of forming a copper wiring of a semiconductor device in which a high purity copper plating film free of impurities can be formed on the front surface of a wafer by immersing the back surface of the wafer including the edge portion in an activation solution and immersing the entire wafer in an electroless copper plating solution. Are described.
Description
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 무전해 도금법에 의해 구리 배선을 형성함에 있어, 구리 배선용 패턴이 형성된 절연층(dielectric layer) 위에 배리어 메탈층(barrier metal layer)을 형성하고, 가장자리 부분을 포함한 웨이퍼 뒷면을 활성화 용액에 담구어 활성화시킨 후 무전해 구리 도금액에 전체 웨이퍼를 담금으로써, 불순물이 없는 순도 높은 구리 도금막을 웨이퍼 앞면에 형성시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. In particular, in forming a copper wiring by an electroless plating method, a barrier metal layer is formed on a dielectric layer on which a copper wiring pattern is formed. In the method for forming a copper wiring of a semiconductor device, a high purity copper plating film free of impurities can be formed on the wafer front side by immersing and activating the back surface of the wafer including the edge portion in an activation solution and then immersing the entire wafer in an electroless copper plating solution. It is about.
구리 배선 공정에 대한 필요성이 대두되기 시작한 1990년을 전후해서 전해 도금법, 무전해 도금법, 물리기상증착(PVD)법, 화학기상증착(CVD)법 등에 대한 연구가 경쟁적으로 진행되고 있다.Around 1990, when the need for copper wiring began to emerge, research on electrolytic plating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., has been competitively conducted.
무전해 구리 도금 방식은 1960년대부터 PCB(printed circuit board)에 널리 응용되어 온 기술이다. 무전해 도금이란 외부에서 전기를 가하지 않고도 용액 내에 존재하는 물질들의 자발적인 산화 환원 반응에 의하여 막이 형성되는 것을 말하며, 도금액은 CuSO4 와 같은 구리의 양이온을 포함하는 물질, 포름알데히드(formaldehyde; HCHO)와 같은 환원제(reductant), 그리고 각 용도(pH조절, 용액 안정)에 따른 몇 가지 첨가제들로 구성되어 있다. 이 경우 도금되어야 할 표면에서 자발적인 산화 환원 반응에 의한 도금이 진행되려면 표면이 활성화(activation)되어야 한다. 이를 위해 무전해 도금액에 담그기 전에 표면 활성화를 위해 활성화 욕(activation bath)에 담구어 미리 표면에 미세한 입자의 Pd와 같은 활성화 입자(activated particle)를 형성시킨다. 따라서, 표면에 형성된 이들 활성화 입자들의 크기 및 밀도에 따라서 도금되는 구리막의 특성이 크게 좌우된다. 한편, PCB에 응용되는 경우에는 도금되는 구리막의 치수(dimension)가 대략 수십 내지 수백㎛ 정도로 크기 때문에 구리막의 특성이 회로에 미치는 영향은 상대적으로 미약하다. 그러나, 서브마이크론(submicron) 이하의 ULSI(ultra large scale integrated)회로에 적용할 경우에는 도금되는 구리막의 특성이 매우 중요하게 된다. 또한, ULSI회로에 적용할 경우에는 절연층(dielectric layer)으로 구리가 확산되는 것을 방지하기 위하여 배리어 메탈층(barrier metal layer)을 먼저 증착한 후, 이 표면 위에 도금을 해야 하는데, 이 배리어 메탈층으로 사용되는 TiN, TaN, WN 등의 재료들은 전도체임에도 불구하고 구리 무전해 도금을 위해서는 표면의 활성화가 필요한 것으로 알려져 있다. 보편적 방법의 하나로써 배리어 메탈의 표면은 Pd 입자로 활성화시키는 방법이 있는데, Pd 활성화 입자는 도금되는 구리막의 불순물로 작용하여 구리막의 비저항을 높이는 문제점이 있다. 이를 방지하기 위한 방편으로 배리어 메탈층 위에 물리기상증착 방식으로 매우 얇은 구리막을 증착하고, 그 위에 보호막으로서 알루미늄(Al)을 인-시튜(in-situ)로 증착하는 방법이 있다. 구리막이 일단 대기 중에 노출되면 표면에 형성된 산화막으로 인해 무전해 도금이 불가능하다. 따라서, 표면에 알루미늄을 증착하므로써 도금시 무전해 구리 도금액의 높은 pH(=10∼13)로 인해 알루미늄이 용해되면서 노출된 얇은 구리막 상에 무전해 구리 도금이 이루어진다. 그러나, 이 방법은 얇은 구리막을 물리기상증착법으로 형성해야 하고, 구리막 상에 알루미늄층을 형성해야 하는 등 공정상의 번거로움으로 생산성 저하를 초래하게 된다.Electroless copper plating has been widely applied to printed circuit boards since the 1960s. Electroless plating refers to the formation of a film by spontaneous redox reaction of materials present in a solution without applying electricity from the outside. The plating solution is formed of a material containing a cation of copper, such as CuSO 4 , formaldehyde (HCHO) and the like. It consists of the same reductant and several additives for each application (pH control, solution stability). In this case, the surface must be activated for plating by spontaneous redox reaction on the surface to be plated. To this end, before immersing in the electroless plating solution, it is immersed in an activation bath for surface activation to form activated particles such as fine particles of Pd on the surface in advance. Therefore, the characteristics of the copper film to be plated largely depend on the size and density of these activation particles formed on the surface. On the other hand, when applied to the PCB, since the dimensions of the copper film to be plated is about tens to hundreds of micrometers, the influence of the characteristics of the copper film on the circuit is relatively small. However, when applied to a ULSI (ultra large scale integrated) circuit below submicron, the characteristics of the copper film to be plated are very important. In addition, when applied to a ULSI circuit, a barrier metal layer must be deposited first and then plated on this surface to prevent copper from diffusing into the dielectric layer. Although materials such as TiN, TaN, and WN are used as conductors, it is known that surface activation is required for copper electroless plating. As one of the common methods, there is a method of activating the surface of the barrier metal with Pd particles, and the Pd activation particles act as impurities of the copper film to be plated, thereby increasing the specific resistance of the copper film. In order to prevent this, there is a method of depositing a very thin copper film on the barrier metal layer by physical vapor deposition, and depositing aluminum (Al) in-situ as a protective film thereon. Once the copper film is exposed to the atmosphere, electroless plating is impossible due to the oxide film formed on the surface. Therefore, by depositing aluminum on the surface, electroless copper plating is performed on the thin copper film exposed as aluminum is dissolved due to the high pH (= 10 to 13) of the electroless copper plating solution during plating. However, this method requires a thin copper film to be formed by a physical vapor deposition method, resulting in a decrease in productivity due to the troublesome process, such as forming an aluminum layer on the copper film.
따라서, 본 발명은 구리 배선용 패턴이 형성된 절연층 위에 배리어 메탈층을 형성하고, 가장자리 부분을 포함한 웨이퍼 뒷면을 활성화 용액에 담구어 활성화시킨 후 무전해 구리 도금액에 전체 웨이퍼를 담금으로써, 불순물이 없는 순도 높은 구리 도금막을 웨이퍼 앞면에 형성시킬 수 있는 반도체 소자의 구리 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention forms a barrier metal layer on the insulating layer on which the copper wiring pattern is formed, activates the back surface of the wafer including the edge part by activating solution, and then immerses the entire wafer in the electroless copper plating solution, thereby providing purity without impurities. It is an object of the present invention to provide a method for forming a copper wiring of a semiconductor device capable of forming a high copper plated film on a wafer front surface.
본 발명의 다른 목적은 불순물이 없는 순도 높은 구리 도금막을 무전해 구리 도금법을 적용한 단순 공정을 통해 형성시켜 생산성 증대 및 실용화를 이룰 수 있는 반도체 소자의 구리 배선 형성 방법을 제공함에 있다. Another object of the present invention is to provide a method for forming a copper wiring of a semiconductor device capable of increasing productivity and making practical use by forming a high purity copper plating film free of impurities through a simple process using an electroless copper plating method.
이러한 목적을 달성하기 위한 본 발명의 실시 예에 따른 반도체 소자의 구리 배선 형성 방법은 구리 배선용 패턴을 갖는 절연층이 형성된 웨이퍼가 제공되는 단계; 상기 절연층 상에 배리어 메탈층을 형성하는 단계; 상기 배리어 메탈층 상에 포토레지스트막을 형성하는 단계; 상기 포토레지스트막이 존재하는 부분을 제외한 상기 웨이퍼의 표면에 활성화층을 형성하는 단계; 상기 포토레지스트막을 제거한 후, 상기 웨이퍼를 무전해 구리 도금액에 담구어 상기 배리어 메탈층 및 상기 활성화층 상에 구리막을 형성하는 단계; 상기 구리막 제거 공정을 통해 상기 웨이퍼 앞면의 상기 배리어 메탈층상에만 상기 구리막을 남기는 단계; 및 상기 남겨진 구리막을 화학적 기계적 연마 공정으로 연마하여 상기 절연층에 형성된 패턴 내에 구리 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: providing a wafer having an insulating layer having a copper wiring pattern; Forming a barrier metal layer on the insulating layer; Forming a photoresist film on the barrier metal layer; Forming an activation layer on a surface of the wafer except for a portion where the photoresist film is present; Removing the photoresist film, and then immersing the wafer in an electroless copper plating solution to form a copper film on the barrier metal layer and the activation layer; Leaving the copper film only on the barrier metal layer on the front surface of the wafer through the copper film removal process; And polishing the remaining copper film by a chemical mechanical polishing process to form a copper wiring in a pattern formed on the insulating layer.
상기에서, 배리어 메탈층은 화학기상증착법이나 물리기상증착법에 의해 Ta, TaN, WN, TiN, TiW, TiSiN, WBN 와 같은 전도체를 상기 웨이퍼의 앞면에 증착하여 형성된다.In the above, the barrier metal layer is formed by depositing a conductor such as Ta, TaN, WN, TiN, TiW, TiSiN, WBN on the front surface of the wafer by chemical vapor deposition or physical vapor deposition.
포토레지스트막은 상기 웨이퍼 가장자리 부분에서 2 내지 15mm 정도 제거시켜 상기 배리어 메탈층이 일부 노출되도록 형성한다.The photoresist film is removed from the edge portion of the wafer by about 2 to 15 mm to partially expose the barrier metal layer.
활성화층은 상기 웨이퍼를 활성화 용액에 담구어 형성하며, 활성화 용액은 PdCl2를 용해시켜 사용하며, 상기 웨이퍼 표면에 존재하는 산화막을 제거하기 위하여 0.05 내지 2%의 HF를 첨가한다. 활성화 용액은 Pd2+ 이온의 농도가 10-4 내지 10M이 되도록 제조하며, 20 내지 100℃의 온도로 유지시킨다.The activation layer is formed by immersing the wafer in an activation solution. The activation solution is used by dissolving PdCl 2 and adding 0.05 to 2% of HF to remove an oxide film existing on the wafer surface. The activation solution is prepared such that the concentration of Pd 2+ ions is 10 −4 to 10M, and maintained at a temperature of 20 to 100 ° C.
무전해 구리 도금액은 Cu2+ 이온의 농도가 10-4 내지 10M이 되도록 제조하며, 도금액의 pH는 10 내지 13을 유지하도록 하며, 도금액의 온도는 20 내지 100℃가 유지되도록 한다.The electroless copper plating solution is prepared so that the concentration of Cu 2+ ions is 10 −4 to 10M, the pH of the plating solution is maintained at 10 to 13, and the temperature of the plating solution is maintained at 20 to 100 ° C.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1의 (a) 내지 (f)는 무전해 구리 도금법을 적용하여 본 발명의 실시 예에 따라 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for explaining a method of forming a copper wiring of a semiconductor device according to an exemplary embodiment of the present invention by applying an electroless copper plating method.
도 1의 (a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성되고, 구리 배선용 패턴을 갖는 절연층(도시 안됨)이 형성된 웨이퍼(11)가 제공된다. 구리 배선용 패턴을 갖는 절연층 상에 배리어 메탈층(12)을 형성한다.Referring to FIG. 1A, a wafer 11 is provided in which various elements for forming a semiconductor element are formed, and an insulating layer (not shown) having a pattern for copper wiring is formed. The barrier metal layer 12 is formed on the insulating layer which has a copper wiring pattern.
상기에서, 절연층은 SiO2 또는 저 유전체(low-k) 등의 절연 재료로 형성한다. 배리어 메탈층(12)은 웨이퍼(11)의 가장자리 제외 없이(edge exclusion) 웨이퍼 앞면(11F)에 형성한다. 배리어 메탈층(12)은 화학기상증착법이나 물리기상증착법에 의해 Ta, TaN, WN, TiN, TiW, TiSiN, WBN 와 같은 전도체 등을 증착하여 형성된다.In the above, the insulating layer is formed of an insulating material such as SiO 2 or a low dielectric (low-k). The barrier metal layer 12 is formed on the wafer front surface 11F without edge exclusion of the wafer 11. The barrier metal layer 12 is formed by depositing a conductor such as Ta, TaN, WN, TiN, TiW, TiSiN, WBN, or the like by chemical vapor deposition or physical vapor deposition.
도 1의 (b)를 참조하면, 배리어 메탈층(12)이 형성된 웨이퍼 앞면(11F)에 포토레지스트막(13)을 형성하는데, 포토레지스트를 코팅(coating)한 후 웨이퍼(11) 가장자리 부분의 포토레지스트막(13)을 2 내지 15mm 정도 제거시켜 배리어 메탈층(12)을 일부 노출시킨다.Referring to FIG. 1B, a photoresist film 13 is formed on the front surface 11F of the wafer on which the barrier metal layer 12 is formed. After coating the photoresist, the edge of the wafer 11 is formed. The photoresist film 13 is removed by about 2 to 15 mm to partially expose the barrier metal layer 12.
상기에서, 배리어 메탈층(12)을 일부 노출시키는 것은 후속 활성화 공정에 의해 형성되는 활성화층과 배리어 메탈층(12)이 이어지게 하기 위해서이다. 포토레지스트막(13)은 후속 활성화 공정에서 배리어 메탈층(12)이 활성화되는 것을 방지하기 위한 보호막 역할을 한다.In the above, the partial exposure of the barrier metal layer 12 is intended to connect the barrier metal layer 12 with the activation layer formed by a subsequent activation process. The photoresist film 13 serves as a protective film to prevent the barrier metal layer 12 from being activated in a subsequent activation process.
도 1의 (c)를 참조하면, 포토레지스트막(13)이 형성된 웨이퍼(11)를 활성화 욕(activation bath; 16)에 채워진 활성화 용액(17)에 담구어 포토레지스트막(13)이 형성된 부분을 제외한 웨이퍼 뒷면(11B) 및 웨이퍼 옆면(11S)의 표면을 Pd입자로 활성화시켜 활성화층(14)을 형성한다. 활성화층(14)은 배리어 메탈층(12)의 노출된 부분과 중첩된다. Referring to FIG. 1C, a portion of the photoresist film 13 formed by dipping the wafer 11 on which the photoresist film 13 is formed into an activation solution 17 filled in an activation bath 16 is shown. The surface of the wafer back surface 11B and the wafer side surface 11S except for the above is activated with Pd particles to form the activation layer 14. The activation layer 14 overlaps the exposed portion of the barrier metal layer 12.
상기에서, 활성화 용액(17)은 PdCl2를 용해시켜 사용하며, 웨이퍼(11) 표면에 존재하는 산화막을 제거하기 위하여 0.05 내지 2%의 HF를 첨가한다. 이때 Pd2+ 이온의 농도가 10-4 내지 10M이 되도록 제조하며, 활성화 시간은 1 내지 200초 정도 유지한다. 활성화 용액(17)의 온도는 20 내지 100℃가 유지되도록 한다. 한편, 웨이퍼 뒷면(11B)에 산화막이 존재할 경우에는 활성화 용액(17)에 담그기 전에 0.05 내지 2%의 HF용액에 10 내지 120초 정도 담근다.In the above, the activation solution 17 is used by dissolving PdCl 2 and adding 0.05 to 2% of HF to remove the oxide film existing on the wafer 11 surface. At this time, the concentration of Pd 2+ ions is prepared to be 10 -4 to 10M, the activation time is maintained for 1 to 200 seconds. The temperature of the activating solution 17 is maintained at 20 to 100 ° C. On the other hand, if an oxide film is present on the back surface 11B of the wafer, it is immersed in 0.05 to 2% of HF solution for 10 to 120 seconds before immersing in the activation solution 17.
도 1의 (d)를 참조하면, 활성화 공정이 완료된 웨이퍼(11)를 활성화 욕(16)에서 꺼낸 후, 포토레지스트막(13)을 제거한다. 포토레지스트막(13)이 제거된 웨이퍼(11)는 배리어 메탈층(12)과 활성화층(14)으로 둘러싸이게 된다.Referring to FIG. 1D, after the wafer 11 in which the activation process is completed is removed from the activation bath 16, the photoresist film 13 is removed. The wafer 11 from which the photoresist film 13 is removed is surrounded by the barrier metal layer 12 and the activation layer 14.
도 1의 (e)를 참조하면, 웨이퍼 앞면(11F)에는 배리어 메탈층(12)이 형성되고, 그 이외의 부분, 즉 웨이퍼 뒷면(11B) 및 웨이퍼 옆면(11S)에는 활성화층(14)이 형성된 웨이퍼(11)를 무전해 구리 도금 욕(18)에 채워진 무전해 구리 도금액(19)에 담구어 배리어 메탈층(12) 및 활성화층(14) 상에 구리막(15)을 형성한다. 즉, 구리막(15)은 웨이퍼(11) 전체 표면에 형성된다.Referring to FIG. 1E, the barrier metal layer 12 is formed on the front surface 11F of the wafer, and the activation layer 14 is formed on the other portions of the wafer, that is, the wafer rear surface 11B and the wafer side surface 11S. The formed wafer 11 is immersed in the electroless copper plating solution 19 filled in the electroless copper plating bath 18 to form a copper film 15 on the barrier metal layer 12 and the activation layer 14. That is, the copper film 15 is formed on the entire surface of the wafer 11.
상기에서, 무전해 구리 도금액(19)은 Cu2+ 이온의 농도가 10-4 내지 10M이 되도록 제조하며, 도금액(19)의 pH는 10 내지 13을 유지하도록 한다. 도금액(19)의 온도는 20 내지 100℃가 유지되도록 한다.In the above, the electroless copper plating solution 19 is prepared so that the concentration of Cu 2+ ions is 10 −4 to 10M, and the pH of the plating solution 19 is maintained at 10 to 13. The temperature of the plating liquid 19 is maintained to 20 to 100 ℃.
한편, 무전해 구리 도금이 진행되기 위해서는 표면에서 환원제의 산화 반응이 진행되어야 하는데, 구리막(15)이 형성되어야 할 배리어 메탈층(12)에서는 이러한 산화 반응이 불가능하기 때문에 표면을 활성화시키는 공정이 필요한 것으로 알려져 있지만, 본 발명에서는 배리어 메탈층(12)을 활성화시키지 않은 상태에서 무전해 구리 도금법으로 구리막(15)을 형성하였는데, 이러한 구리 도금에 대한 메커니즘(mechanism)은 후술할 것이다. On the other hand, in order for the electroless copper plating to proceed, an oxidation reaction of a reducing agent must proceed on the surface. However, in the barrier metal layer 12 on which the copper film 15 is to be formed, the oxidation reaction is not possible. Although it is known to be necessary, in the present invention, the copper film 15 was formed by the electroless copper plating method without the barrier metal layer 12 being activated. The mechanism for such copper plating will be described later.
도 1의 (f)를 참조하면, 구리 도금 공정이 완료된 웨이퍼(11)를 무전해 구리 도금 욕(18)에서 꺼낸 후, 웨이퍼 뒷면(11B) 및 웨이퍼 옆면(11S)에 형성된 구리막(15)을 제거하여 웨이퍼 앞면(11F)에만 구리막(15)을 남긴다. 이후, 화학적 기계적 연마(CMP) 공정으로 구리막(15)을 연마하여 절연층에 형성된 패턴 내에 구리 배선을 형성한다.Referring to FIG. 1F, after the copper plating process is completed, the wafer 11 is removed from the electroless copper plating bath 18, and the copper film 15 formed on the wafer backside 11B and the wafer side surface 11S. Is removed to leave the copper film 15 only on the wafer front surface 11F. Thereafter, the copper film 15 is polished by a chemical mechanical polishing (CMP) process to form a copper wiring in a pattern formed on the insulating layer.
도 2는 무전해 구리 도금막의 형성 메커니즘을 도시한 도면이다.2 is a view showing a mechanism for forming an electroless copper plating film.
웨이퍼(21) 상에 배리어 메탈층(22)을 형성하고, 웨이퍼(21)의 일부분에 활성화 공정을 진행하여 활성화 지역(AA)과 비활성화 지역(BB)으로 나누어지게 한다. 활성화 지역(AA)에는 활성화 입자(23)가 존재한다. 이러한 웨이퍼(21)를 구리 도금액에 담그면, 도시된 바와 같이, 도금액의 환원제가 활성화 표면에서 산화되어 활성화 지역(AA)에 전자를 발생시키게 되는데, 이는 활성화 입자(23) 위에서, 그리고 전도체인 배리어 메탈층(22)의 표면에서 용액 중에 존재하는 Cu2+ 이온과 결합하여 구리 핵(24)을 형성하게 된다. 일단 전자가 발생한 경우에는 전자의 빠른 이동도 때문에 웨이퍼(21)의 위치에 관계없이 Cu2+ 이온이 존재하는 용액 내의 모든 위치에서 구리 핵(24)의 생성을 가능하게 한다. 즉, 활성화 지역(AA)에서 발생된 전자는 비활성 지역(BB)의 배리어 메탈층(22)으로 이동하게 되고, 이 전자에 의해 비활성 지역(BB)의 배리어 메탈층(23)의 표면에도 구리 핵(24)이 생성된다. 일단 구리 핵(24)이 형성되면 활성화된 표면이 된 것이므로 계속해서 무전해 도금이 진행된다.The barrier metal layer 22 is formed on the wafer 21, and an activation process is performed on a portion of the wafer 21 to be divided into an activation region AA and an inactivation region BB. Activation particles 23 are present in the activation zone AA. When the wafer 21 is immersed in the copper plating liquid, as shown, the reducing agent of the plating liquid is oxidized at the activation surface to generate electrons in the activation region AA, which is on the activation particles 23 and the barrier metal as a conductor. At the surface of layer 22, it combines with Cu 2+ ions present in solution to form copper nuclei 24. Once generated, the rapid mobility of the electrons makes it possible to produce the copper nucleus 24 at any location in the solution where Cu 2+ ions are present, regardless of the location of the wafer 21. That is, electrons generated in the activation region AA move to the barrier metal layer 22 of the inactive region BB, and the electrons are also used on the surface of the barrier metal layer 23 of the inactive region BB by the electrons. (24) is generated. Once the copper nucleus 24 is formed, it becomes an activated surface, and thus electroless plating proceeds.
상술한 바와 같이, 본 발명은 구리 배선용 패턴이 형성된 절연층 위에 배리어 메탈층을 형성하고, 가장자리 부분을 포함한 웨이퍼 뒷면을 활성화 용액에 담구어 활성화시킨 후 무전해 구리 도금액에 전체 웨이퍼를 담금으로써, 단순 공정을 통해 불순물이 없는 순도 높은 구리 도금막을 웨이퍼 앞면에 형성시킬 수 있어, 생산성 증대 및 무전해 구리 도금법을 실용화시킬 수 있고, 고 성능(high performance) 소자를 제조할 수 있다. As described above, the present invention is simple by forming a barrier metal layer on the insulating layer on which the copper wiring pattern is formed, and immersing the entire wafer in an electroless copper plating solution by immersing and activating the back surface of the wafer including the edge portion in an activation solution. Through the process, a high purity copper plating film free of impurities can be formed on the front surface of the wafer, thereby increasing productivity and making the electroless copper plating method practical, and manufacturing a high performance device.
도 1의 (a) 내지 도 (f)는 본 발명의 실시 예에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention.
도 2는 무전해 구리 도금막의 형성 메커니즘을 도시한 도면.2 shows a mechanism of forming an electroless copper plating film.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 웨이퍼 11F: 웨이퍼 앞면11: wafer 11F: wafer front
11B: 웨이퍼 뒷면 11S: 웨이퍼 옆면11B: Wafer backside 11S: Wafer side
12: 배리어 메탈층 13: 포토레지스트막12: barrier metal layer 13: photoresist film
14: 활성화층 15: 구리막14: activation layer 15: copper film
16: 활성화 욕 17: 활성화 용액16: activation bath 17: activation solution
18: 무전해 구리 도금 욕 19: 무전해 구리 도금액18: electroless copper plating bath 19: electroless copper plating solution
21:웨이퍼 22: 배리어 메탈층21: wafer 22: barrier metal layer
23: 활성화 입자 24: 구리 핵23: activated particles 24: copper core
AA: 활성화 지역 BB: 비활성화 지역AA: active area BB: inactive area
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| JPH04130727A (en) * | 1990-09-21 | 1992-05-01 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPH05206316A (en) * | 1991-07-16 | 1993-08-13 | Philips Gloeilampenfab:Nv | Method for formation of copper pattern on dielectric substrate |
| KR940016499A (en) * | 1992-12-31 | 1994-07-23 | 김주영 | Method of forming barrier metal layer of semiconductor device |
| KR950004839A (en) * | 1993-07-16 | 1995-02-18 | 이헌조 | Apparatus and method for recording time on an answering machine |
| KR19990049050A (en) * | 1997-12-11 | 1999-07-05 | 구본준 | Wiring Formation Method of Semiconductor Device |
| KR19990057289A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Metal wiring layer formation method of MOS PET transistor |
| JP2000212754A (en) * | 1999-01-22 | 2000-08-02 | Sony Corp | Plating method, its device and plated structure |
| KR100265615B1 (en) * | 1998-06-29 | 2000-10-02 | 김영환 | Manufacturing method of a metal line for a semiconductor |
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2000
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130727A (en) * | 1990-09-21 | 1992-05-01 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPH05206316A (en) * | 1991-07-16 | 1993-08-13 | Philips Gloeilampenfab:Nv | Method for formation of copper pattern on dielectric substrate |
| KR940016499A (en) * | 1992-12-31 | 1994-07-23 | 김주영 | Method of forming barrier metal layer of semiconductor device |
| KR950004839A (en) * | 1993-07-16 | 1995-02-18 | 이헌조 | Apparatus and method for recording time on an answering machine |
| KR19990049050A (en) * | 1997-12-11 | 1999-07-05 | 구본준 | Wiring Formation Method of Semiconductor Device |
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| KR19990057289A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Metal wiring layer formation method of MOS PET transistor |
| KR100265615B1 (en) * | 1998-06-29 | 2000-10-02 | 김영환 | Manufacturing method of a metal line for a semiconductor |
| JP2000212754A (en) * | 1999-01-22 | 2000-08-02 | Sony Corp | Plating method, its device and plated structure |
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