KR100744244B1 - Method for fabricating copper line in semiconductor device - Google Patents

Method for fabricating copper line in semiconductor device Download PDF

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KR100744244B1
KR100744244B1 KR1020050131235A KR20050131235A KR100744244B1 KR 100744244 B1 KR100744244 B1 KR 100744244B1 KR 1020050131235 A KR1020050131235 A KR 1020050131235A KR 20050131235 A KR20050131235 A KR 20050131235A KR 100744244 B1 KR100744244 B1 KR 100744244B1
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copper
film
oxide film
insulating film
semiconductor device
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KR1020050131235A
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Korean (ko)
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KR20070069291A (en
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주상민
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

본 발명은 반도체 소자의 구리배선 제조 방법에 관한 것으로, 절연막을 식각하여 제 1 구리막의 소정 표면을 노출시키는 절연막 패턴을 형성하는 단계와, 메틸 레디칼(CH3)과 아세톤(CH3COCH3)이 혼합된 수용액을 사용하여 노출된 제 1 구리막을 세정하여 구리 산화막의 생성을 억제하는 단계와, 절연막 패턴상에 배리어메탈을 형성하는 단계와, 배리어메탈상에 제2 구리막을 형성하는 단계를 포함하며, 구리배선에 의한 구리 산화막 생성을 억제하는 새로운 방지 기술이 채용하여 구리 산화막의 억제 효율이 상승하며, 이로써 구리 산화막으로 인한 반도체 소자의 특성을 향상시킬 수 이점이 있다.The present invention relates to a method for manufacturing a copper wiring of a semiconductor device, comprising the steps of: etching an insulating film to form an insulating film pattern exposing a predetermined surface of the first copper film, and methyl radical (CH 3 ) and acetone (CH 3 COCH 3 ) Cleaning the exposed first copper film using the mixed aqueous solution to suppress the formation of a copper oxide film, forming a barrier metal on the insulating film pattern, and forming a second copper film on the barrier metal; In addition, a new prevention technology for suppressing the formation of a copper oxide film by copper wiring is adopted to increase the suppression efficiency of the copper oxide film, thereby improving the characteristics of the semiconductor device due to the copper oxide film.

구리배선, 구리 산화막, 금속배선 Copper wiring, copper oxide film, metal wiring

Description

반도체 소자의 구리배선 제조 방법{METHOD FOR FABRICATING COPPER LINE IN SEMICONDUCTOR DEVICE}Copper wiring manufacturing method of semiconductor device {METHOD FOR FABRICATING COPPER LINE IN SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 구리배선 제조 방법을 설명하기 위한 공정 단면도,1A to 1C are cross-sectional views illustrating a method for manufacturing a copper wiring of a semiconductor device according to the prior art;

도 2는 본 발명에 따른 반도체 소자의 구리배선 제조 방법을 설명하기 위한 공정 흐름도.2 is a process flowchart for explaining a method for manufacturing a copper wiring of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 구리배선 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 소자에서 구리배선에 의한 구리 산화막 생성을 억제하는 반도체 소자의 구리배선 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing copper wiring of a semiconductor device, and more particularly, to a method for manufacturing copper wiring of a semiconductor device that suppresses the formation of a copper oxide film by copper wiring in a semiconductor device.

구리 배선 공정에 대한 필요성이 대두되기 시작한 1990년을 전후해서 전해도금법, 무전해도금법, 물리기상증착법, 화학기상증착법 등에 대한 연구가 경쟁적으로 진행되고 있다. 현재까지 상용화되고 있는 기술은 전해도금법이지만, 전기도금을 위해 필수적인 것이 바로 시드층(seed layer) 기술이다.Around 1990, when the need for copper wiring process began to emerge, researches on electroplating method, electroless plating method, physical vapor deposition method, chemical vapor deposition method, etc. have been competitively conducted. The technology commercially available up to now is an electroplating method, but the seed layer technology is essential for electroplating.

시드층 기술은 바로 전해도금법의 기술적 한계에 직접적으로 영향을 미치게 되어, 이에 대한 대안으로 무전해 도금법이 제시되고 있다.The seed layer technology directly affects the technical limitations of the electroplating method, and an electroless plating method is proposed as an alternative.

무전해 구리 도금법은 1960년대부터 인쇄회로기판에 널리 응용되어 온 기술이다. 무전해 도금이란 외부에서 전기를 가하지 않고도 용액내에 존재하는 물질들의 자발적인 산화 환원반응에 의하여 구리막이 형성되는 것을 말하며, 도금액은 CuSO4 와 같은 구리의 양이온을 포함하는 물질, 포말디하이드(Formaldehyde; HCHO)와 같은 환원제, 그리고 각 용도(pH 조절, 용액 안정)에 따른 첨가제들로 구성되어 있다.Electroless copper plating has been widely applied to printed circuit boards since the 1960s. Electroless plating refers to the formation of a copper film by spontaneous redox reaction of materials present in a solution without applying electricity from the outside. The plating solution is a material containing a cation of copper, such as CuSO 4 , formaldehyde (HCHO). Reducing agent such as) and additives for each application (pH control, solution stability).

이 경우 도금되어야할 표면에서 자발적인 산화 환원 반응에 의한 도금이 진행되려면 표면이 활성화(activation)되어야 한다. 이를 위해 무전해 도금액에 담그기 전 표면 활성화를 위해 활성화 용기(bath)에 담그어 미리 표면에 미세한 입자의 팔라듐(Pd)과 같은 활성화 입자를 형성시킨다. 따라서, 표면에 형성된 이들 활성화 입자들의 크기 및 밀도에 따라서 도금되는 구리막의 특성이 크게 좌우된다.In this case, the surface must be activated for plating by spontaneous redox reaction on the surface to be plated. To this end, it is immersed in an activation bath for surface activation before immersion in an electroless plating solution to form activated particles such as fine particles of palladium (Pd) on the surface in advance. Therefore, the characteristics of the copper film to be plated largely depend on the size and density of these activation particles formed on the surface.

한편, 인쇄회로기판에 응용되는 경우에는 도금되는 구리막의 디멘젼(dimension)이 대략 수십∼수백㎛정도로 크기 때문에 구리막의 특성이 회로에 미치는 영향은 상대적으로 미약하다. 그러나, 서브미크론 이하의 초고집적회로(ULSI)에 적용할 경우에는 도금되는 구리막의 특성이 매우 중요하게 된다.On the other hand, when applied to a printed circuit board, since the dimension of the copper film to be plated is about tens to hundreds of micrometers, the influence of the characteristics of the copper film on the circuit is relatively small. However, when applied to an ultra high integrated circuit (ULSI) of submicron or less, the characteristics of the copper film to be plated are very important.

또한, 초고집적회로에 적용할 경우에는 유전막으로의 구리의 확산을 방지하기 위하여 배리어메탈을 먼저 증착한 후 이들 표면위에 도금을 해야 하는데, 이는 배리어메탈로 사용되는 TiN, WN, TaN 등의 재료들은 전도체임에도 불구하고 구리 무전해 도금을 위해서는 표면의 활성화가 필요하게 된다.In addition, when applied to ultra-high integrated circuits, barrier metals must be deposited first and then plated on these surfaces in order to prevent diffusion of copper into the dielectric film. This is because materials such as TiN, WN, and TaN used as barrier metals are used. Despite being a conductor, surface electroactivation is required for copper electroless plating.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 구리배선 제조 방법을 설명하기 위한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method for manufacturing a copper wiring of a semiconductor device according to the prior art.

반도체 기판(11)상에 형성된 게이트전극, 비트라인 등의 하부 구조물(12)상에 제 1 절연막(14)을 형성한 후, 제 1 절연막(14)을 패터닝하여 하부 구조물(12)과 전기적으로 연결되는 제 1 구리막(13)을 형성한다.After forming the first insulating film 14 on the lower structure 12 such as a gate electrode, a bit line, and the like formed on the semiconductor substrate 11, the first insulating film 14 is patterned to electrically connect with the lower structure 12. The first copper film 13 to be connected is formed.

그리고, 제 1 절연막(14)을 평탄화하여 제 1 구리막(13) 표면을 노출시킨 후, 제 1 구리막(13)과 제 1 절연막(14)상에 제 2 절연막(15)을 형성한다.After the first insulating film 14 is planarized to expose the surface of the first copper film 13, the second insulating film 15 is formed on the first copper film 13 and the first insulating film 14.

다음으로, 제 2 절연막(15)을 식각하여 듀얼 다마신 패턴(16)을 형성한다. 여기서, 듀얼 다마신 패턴(16)은 홀(hole) 패턴과 라인(line) 패턴을 동시에 형성하기 위한 패턴이다.Next, the second insulating layer 15 is etched to form a dual damascene pattern 16. Here, the dual damascene pattern 16 is a pattern for simultaneously forming a hole pattern and a line pattern.

다음으로, 듀얼 다마신 패턴(16)을 포함한 전면에 배리어메탈(17)을 증착한후, 배리어메탈(17) 표면을 활성화시키고, 연속해서 무전해 구리 도금을 행하여 배리어메탈(17)의 전 표면상에 제 2 구리막(18)을 형성시킨다.Next, after depositing the barrier metal 17 on the front surface including the dual damascene pattern 16, the surface of the barrier metal 17 is activated, and electroless copper plating is successively performed to thereby form the entire surface of the barrier metal 17. The second copper film 18 is formed on it.

그런데, 구리배선은 금속고유의 성질인 저항이 낮아 소자의 저항으로 인한 타임 딜레이(Time Delay) 문제를 개선할 수 있고, 금속 및 유전층 막의 층수를 줄일 수 있다는 장점이 있는 것에 반하여 다른 금속에 비해 쉽게 산화되는 단점이 있다.However, copper wiring has low resistance, which is a property of metal, which can improve the time delay caused by device resistance, and can reduce the number of layers of metal and dielectric layers. It has the disadvantage of being oxidized.

한편, 전술한 바와 같은 종래의 구리배선 제조 방법에 의하면 듀얼 다마신 패턴(16)의 형성시에 제 1 구리막(13)이 노출되면 도 1b에 나타낸 바와 같이 그 노 출면에 구리 산화막(CuOx)이 생성되는 문제점이 있었다.On the other hand, according to the conventional copper wiring manufacturing method as described above, if the first copper film 13 is exposed when the dual damascene pattern 16 is formed, the copper oxide film CuOx is exposed on the exposed surface thereof as shown in FIG. 1B. There was a problem being generated.

한편, 구리 산화막의 제거를 위해 H2 가스를 이용하는 공정이 공지되어 있으나 만족할만한 제거 효율 및 특성을 갖지 못한다.On the other hand, a process using H 2 gas for removing the copper oxide film is known, but does not have satisfactory removal efficiency and characteristics.

본 발명은 이와 같은 종래의 문제점을 해결하기 위하여 제안한 것으로, 구리배선에 의한 구리 산화막 생성을 억제하는 새로운 방지 기술이 채용된 반도체 소자의 구리배선 제조 방법을 제공하는 데 그 목적이 있다.The present invention has been proposed to solve such a conventional problem, and an object thereof is to provide a method for manufacturing a copper wiring of a semiconductor device employing a new prevention technique for suppressing the production of a copper oxide film by the copper wiring.

이와 같은 목적을 실현하기 위한 본 발명에 따른 구리배선 제조 방법은, 절연막을 식각하여 제 1 구리막의 소정 표면을 노출시키는 절연막 패턴을 형성하는 단계와, 메틸 레디칼(CH3)과 아세톤(CH3COCH3)이 혼합된 수용액을 사용하여 노출된 상기 제 1 구리막을 세정하여 구리 산화막의 생성을 억제하는 단계와, 상기 절연막 패턴상에 배리어메탈을 형성하는 단계와, 상기 배리어메탈상에 제2 구리막을 형성하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a copper wiring according to the present invention includes etching an insulating film to form an insulating film pattern exposing a predetermined surface of the first copper film, methyl radical (CH 3 ) and acetone (CH 3 COCH). 3 ) cleaning the exposed first copper film using an aqueous solution mixed with the same) to suppress formation of a copper oxide film, forming a barrier metal on the insulating film pattern, and forming a second copper film on the barrier metal. Forming a step.

이하, 본 발명의 바람직한 실시 예를 첨부된 도면들을 참조하여 상세히 설명한다. 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

도 2는 본 발명에 따른 반도체 소자의 구리배선 제조 방법을 설명하기 위한 공정 흐름도이다. 본 발명에 따른 구리배선 제조 방법을 도 1 및 도 2를 참조하여 설명하기로 한다.2 is a flowchart illustrating a method for manufacturing a copper wiring of a semiconductor device according to the present invention. A method of manufacturing a copper wiring according to the present invention will be described with reference to FIGS. 1 and 2.

반도체 기판(11)상에 형성된 게이트전극, 비트라인 등의 하부 구조물(12)상에 제 1 절연막(14)을 형성한 후(101), 제 1 절연막(14)을 패터닝하여 하부 구조물(12)과 전기적으로 연결되는 제 1 구리막(13)을 형성한다(103).After forming the first insulating film 14 on the lower structure 12 such as a gate electrode, a bit line, etc. formed on the semiconductor substrate 11, the first insulating film 14 is patterned to form the lower structure 12. A first copper film 13 electrically connected to the first copper film 13 is formed (103).

그리고, 제 1 절연막(14)을 평탄화하여 제 1 구리막(13) 표면이 드러날때까지 화학적 기계 연마하여 평탄화시킨 후, 제 1 구리막(13)과 제 1 절연막(14)상에 제 2 절연막(15)을 형성한다(105).Then, the first insulating film 14 is planarized and chemically polished and planarized until the surface of the first copper film 13 is exposed, and then the second insulating film is formed on the first copper film 13 and the first insulating film 14. (15) is formed (105).

다음으로, 제 2 절연막(15)을 식각하여 제 1 구리막(13)의 소정 표면을 노출시키는 제 2 절연막 패턴, 즉 듀얼 다마신 패턴(16)을 형성한다(107). 이때, 듀얼 다마신 패턴은 제 1 구리막(13)과 제 2 구리막을 연결하는 홀패턴과 제 2 구리막의 라인패턴을 동시에 형성하기 위한 것으로, 싱글 다마신 패턴일 수도 있다.Next, the second insulating film 15 is etched to form a second insulating film pattern, that is, a dual damascene pattern 16 exposing a predetermined surface of the first copper film 13 (107). In this case, the dual damascene pattern is used to simultaneously form a hole pattern connecting the first copper layer 13 and the second copper layer and a line pattern of the second copper layer, and may be a single damascene pattern.

여기서, 제 1 구리막(13)이 노출되어 구리 산화막(CuOx)을 생성할 수 있으므로 메틸 레디칼(CH3)과 아세톤(CH3COCH3)이 혼합된 수용액을 사용하여 노출된 제 1 구리막(13)을 세정하여 구리 산화막의 생성을 억제한다.Here, since the first copper film 13 may be exposed to generate a copper oxide film CuOx, the first copper film exposed using an aqueous solution in which methyl radical (CH 3 ) and acetone (CH 3 COCH 3 ) are mixed ( 13) is washed to suppress the formation of the copper oxide film.

제 1 구리막(13)의 세정 공정은 온도를 300K∼400K로 맞추고, 공정시간은 30min∼60min으로 설정하며, 건조 시간(Dry Time)은 60sec∼120sec로 실시한다.In the cleaning process of the first copper film 13, the temperature is set to 300K to 400K, the process time is set to 30min to 60min, and the dry time is performed to 60sec to 120sec.

아울러, 구리 산화막은 세정 공정을 통해 그 생성이 억제되나 연속하는 열처리 공정을 통해 구리 산화막의 생성을 보다 효과적으로 억제할수도 있다. 열처리 공정의 조건은 H2 유량이 200∼300sccm인 수소분위기에서 수행하며, 열처리 온도를 700K∼800K로 맞추고, 열처리 시간 2Hr∼3Hr으로 설정한다(109).In addition, the production of the copper oxide film is suppressed through the cleaning process, but the production of the copper oxide film may be more effectively suppressed through the continuous heat treatment process. The conditions of the heat treatment process are performed in a hydrogen atmosphere having a H 2 flow rate of 200 to 300 sccm, the heat treatment temperature is set to 700K to 800K, and the heat treatment time is set to 2Hr to 3Hr (109).

다음으로, 듀얼 다마신 패턴(16)을 포함한 전면에 배리어메탈(17)을 증착한다(111). 이때, 배리어메탈(17)로는 Ta, TaN, TaC, WN, TiW, WBN 및 WC로 이루어진 그룹중에서 선택된 하나를 이용하며, 이들 배리어메탈(17)은 물리기상증착법(PVD) 또는 화학기상증착법(CVD)을 통해 증착한다.Next, the barrier metal 17 is deposited on the entire surface including the dual damascene pattern 16 (111). In this case, as the barrier metal 17, one selected from the group consisting of Ta, TaN, TaC, WN, TiW, WBN and WC is used, and these barrier metals 17 are physical vapor deposition (PVD) or chemical vapor deposition (CVD). To be deposited).

다음으로, 제 1 구리막(13)상에 무전해 구리도금을 행하여 제 2 구리막(18)을 형성한다(113).Next, electroless copper plating is performed on the first copper film 13 to form a second copper film 18 (113).

지금까지는 본 발명을 예시적으로 설명한 것에 불과한 것으로, 본 발명의 기술이 당업자에 의하여 용이하게 변형 실시될 가능성이 자명하다. 이러한 변형된 실시 예들은 본 발명의 특허청구범위에 기재된 기술사상에 당연히 포함되는 것으로 해석되어야 할 것이다.So far, the present invention has been described by way of example only, and it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be construed as naturally included in the technical spirit described in the claims of the present invention.

전술한 바와 같이 본 발명은 구리배선에 의한 구리 산화막 생성을 억제하는 새로운 방지 기술이 채용하여 구리 산화막의 억제 효율이 상승하며, 이로써 구리 산화막으로 인한 반도체 소자의 특성을 향상시킬 수 있다.As described above, the present invention employs a new prevention technology that suppresses the formation of a copper oxide film by copper wiring, thereby increasing the suppression efficiency of the copper oxide film, thereby improving the characteristics of the semiconductor device due to the copper oxide film.

Claims (4)

절연막을 식각하여 제 1 구리막의 소정 표면을 노출시키는 절연막 패턴을 형성하는 단계와,Etching the insulating film to form an insulating film pattern exposing a predetermined surface of the first copper film; 메틸 레디칼(CH3)과 아세톤(CH3COCH3)이 혼합된 수용액을 사용하여 노출된 상기 제 1 구리막을 세정하여 구리 산화막의 생성을 억제하는 단계와,Cleaning the exposed first copper film using an aqueous solution of methyl radical (CH 3 ) and acetone (CH 3 COCH 3 ) to inhibit the formation of a copper oxide film; 상기 절연막 패턴상에 배리어메탈을 형성하는 단계와,Forming a barrier metal on the insulating film pattern; 상기 배리어메탈상에 제2 구리막을 형성하는 단계Forming a second copper film on the barrier metal 를 포함하는 반도체 소자의 구리 배선 제조 방법.Copper wiring manufacturing method of a semiconductor element containing. 제 1항에 있어서,The method of claim 1, 상기 세정 단계는, 온도를 300K∼400K로 맞추고, 공정시간은 30min∼60min으로 설정하며, 건조 시간(Dry Time)은 60sec∼120sec로 실시하는 것In the washing step, the temperature is set to 300K to 400K, the process time is set to 30min to 60min, and the dry time is performed to 60sec to 120sec. 을 특징으로 하는 반도체 소자의 구리 배선 제조 방법.The copper wiring manufacturing method of a semiconductor element characterized by the above-mentioned. 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 상기 세정 후 열처리 공정을 통해 구리 산화막의 생성 억제성을 향상시키는 것To improve the inhibition of the production of the copper oxide film through the heat treatment step after the cleaning 을 특징으로 하는 반도체 소자의 구리 배선 제조 방법.The copper wiring manufacturing method of a semiconductor element characterized by the above-mentioned. 제 3항에 있어서,The method of claim 3, wherein 상기 열처리 공정은 H2 유량이 200∼300sccm인 수소분위기에서 수행하며, 열처리 온도를 700K∼800K로 맞추고, 열처리 시간 2Hr∼3Hr으로 설정하는 것The heat treatment process is carried out in a hydrogen atmosphere having a H 2 flow rate of 200 ~ 300sccm, the heat treatment temperature is set to 700K ~ 800K, the heat treatment time is set to 2Hr ~ 3Hr 을 특징으로 하는 반도체 소자의 구리 배선 제조 방법.The copper wiring manufacturing method of a semiconductor element characterized by the above-mentioned.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980018040A (en) * 1996-02-29 1998-06-05 나까네 히사시 Manufacturing method of multilayer wiring board

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