KR940016499A - Method of forming barrier metal layer of semiconductor device - Google Patents

Method of forming barrier metal layer of semiconductor device Download PDF

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Publication number
KR940016499A
KR940016499A KR1019920027046A KR920027046A KR940016499A KR 940016499 A KR940016499 A KR 940016499A KR 1019920027046 A KR1019920027046 A KR 1019920027046A KR 920027046 A KR920027046 A KR 920027046A KR 940016499 A KR940016499 A KR 940016499A
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KR
South Korea
Prior art keywords
barrier metal
metal layer
layer
depositing
forming
Prior art date
Application number
KR1019920027046A
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Korean (ko)
Inventor
김헌도
조경수
Original Assignee
김주영
현대전자산업 주식회사
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Application filed by 김주영, 현대전자산업 주식회사 filed Critical 김주영
Priority to KR1019920027046A priority Critical patent/KR940016499A/en
Publication of KR940016499A publication Critical patent/KR940016499A/en

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Abstract

본 발명은 고집적 반도체소자의 제조공정중 서브 마이크를 콘택홀을 하층 실리콘기판 또는 도전층에 콘택하는 금속배선에 관한 것으로 기존의 스퍼터링 장비 안 혹은 밖에서 후처리되는 대신 배리어 금속증착시 산소가 포함되지 않은 배리어금속층과 포함된 층으로 2단계 증착함으로 해서 공정단순화를 통한 공정시간단축, 배리어금속내에 들어가는 산소량 및 산소가 포함된 배리어금속의 두께조절을 통해 충분한 배리어 효과를 얻을 수 있는 기술에 관한 것이다.The present invention relates to a metal wiring for contacting a sub microphone with a contact hole to a lower silicon substrate or a conductive layer during the manufacturing process of a highly integrated semiconductor device, and does not include oxygen during deposition of a barrier metal instead of being post-treated in or outside existing sputtering equipment. The present invention relates to a technology capable of obtaining a sufficient barrier effect by reducing the process time through process simplification, the amount of oxygen entering the barrier metal, and the thickness of the barrier metal containing oxygen by two-step deposition into the barrier metal layer and the included layer.

Description

반도체소자의 배리어금속층 형성방법Method of forming barrier metal layer of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도는 본 발명에 따라 제1A도의 공정후 스터퍼링장치안에서 다른증착 챔버로 이동하여 산소가 포함된 배리어 금속층을 증착한 상태의 단면도, 제2B도 및 제2C도는 제2A도의 공정후 각각 알루미늄 합금층, 반사방지층을 그리고 티타늄층, 알루미늄 합금층, 반사방지층을 연속적으로 증착한 상태의 단면도.Figure 2A is a cross-sectional view of the deposition of a barrier metal layer containing oxygen by moving to another deposition chamber in the post-processing stuffing apparatus of FIG. Sectional view showing a layer, an antireflection layer, and a titanium layer, an aluminum alloy layer, and an antireflection layer successively deposited.

Claims (3)

실리콘기판 혹은 도전층 상부에 콘택홀이 형성된 절연층을 형성하고 상기 콘택홀을 통하여 기판에 접속하는 금속배선을 형성한후 그 상부에 배리어금속층을 형성하는 방법에 있어서, 실리콘기판(1) 상부에 절연층(2)을 형성한후 콘택홀을 형성하는 단계와, 전체구조 상부에 티타늄층을 일정두께 증착하는 단계와, 예정된 일정두께의 배리어금속층을 산소포함없이 증착하는 단계와, 예정된 일정두께의 배리어금속층을 증착한 후 연속으로 산소가 포함된 배리어금속층을 증착하는 단계와, 예정된 일정두께의 티타늄층, 알루미늄합금층, 반사방지층을 순차적으로 증착하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 배리어금속층 형성방법.A method of forming an insulating layer having a contact hole formed on a silicon substrate or a conductive layer, forming a metal wiring for connecting to the substrate through the contact hole, and then forming a barrier metal layer thereon. Forming a contact hole after the insulating layer 2 is formed, depositing a titanium layer on the entire structure at a predetermined thickness, depositing a barrier metal layer having a predetermined thickness without oxygen, and depositing a predetermined thickness And depositing a barrier metal layer containing oxygen continuously after depositing the barrier metal layer, and sequentially depositing a titanium layer, an aluminum alloy layer, and an antireflection layer having a predetermined thickness. Metal layer formation method. 제 1 항에 있어서, 산소가 포함안된 일정두께의 배리어금속층은 TiN 또는 TiW인 것을 특징으로 하는 반도체소자의 배리어금속층 형성방법.The method of forming a barrier metal layer of a semiconductor device according to claim 1, wherein the barrier metal layer having a predetermined thickness containing no oxygen is TiN or TiW. 제 1 항에 있어서, 산소가 포함된 배리어금속층은 TiN 또는 TiWO인 것을 특징으로 하는 반도체소자의 배리어금속층 형성방법.The method of claim 1, wherein the barrier metal layer containing oxygen is TiN or TiWO. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027046A 1992-12-31 1992-12-31 Method of forming barrier metal layer of semiconductor device KR940016499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027046A KR940016499A (en) 1992-12-31 1992-12-31 Method of forming barrier metal layer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027046A KR940016499A (en) 1992-12-31 1992-12-31 Method of forming barrier metal layer of semiconductor device

Publications (1)

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KR940016499A true KR940016499A (en) 1994-07-23

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KR1019920027046A KR940016499A (en) 1992-12-31 1992-12-31 Method of forming barrier metal layer of semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100401498B1 (en) * 2001-01-11 2003-10-17 주식회사 하이닉스반도체 Method of forming barrier layers in semiconductor devices
KR100476702B1 (en) * 2000-12-28 2005-03-16 주식회사 하이닉스반도체 Method of forming a copper wiring in a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476702B1 (en) * 2000-12-28 2005-03-16 주식회사 하이닉스반도체 Method of forming a copper wiring in a semiconductor device
KR100401498B1 (en) * 2001-01-11 2003-10-17 주식회사 하이닉스반도체 Method of forming barrier layers in semiconductor devices

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