KR100411811B1 - 반도체패키지 - Google Patents
반도체패키지 Download PDFInfo
- Publication number
- KR100411811B1 KR100411811B1 KR10-2001-0017449A KR20010017449A KR100411811B1 KR 100411811 B1 KR100411811 B1 KR 100411811B1 KR 20010017449 A KR20010017449 A KR 20010017449A KR 100411811 B1 KR100411811 B1 KR 100411811B1
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- semiconductor chip
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- semiconductor package
- passive element
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/927—Different doping levels in different parts of PN junction to produce shaped depletion layer
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
- (정정) 대략 판상(板狀)의 수지층 상,하면에 다수의 도전성 회로패턴이 형성된 섭스트레이트;상기 섭스트레이트의 상면 중앙에 형성된 회로패턴에 솔더로 접속된 다수의 수동소자;상기 다수의 수동소자를 덮는 접착수단;상기 접착수단위에 접착된 반도체칩;상기 반도체칩과 섭스트레이트 상면의 회로패턴을 상호 전기적으로 접속하는 다수의 도전성 와이어;상기 반도체칩 및 도전성 와이어가 외부환경으로부터 보호되도록 봉지재로 봉지되어 형성된 봉지부; 및,상기 섭스트레이트 하면에 형성된 회로패턴에 융착된 다수의 도전성볼을 포함하여 이루어진 반도체패키지.
- 제1항에 있어서, 상기 수동소자의 외주연에는, 상기 수동소자의 두께보다 두꺼운 비전도성 댐이 더 형성된 것을 특징으로 하는 반도체패키지.
- (삭제)
- (정정) 제1항에 있어서, 상기 접착수단은 비전도성 에폭시(Epoxy), 비전도성 폴리이미드(Polyimide) 또는 비전도성 양면 접착 테이프중 어느 하나인 것을 특징으로 하는 반도체패키지.
- (정정) 대략 판상(板狀)으로서, 상면에는 일정 깊이의 요부(凹部)가 형성되고, 상기 요부의 바닥면, 상면 및 하면에는 다수의 도전성 회로패턴이 형성된 섭스트레이트;상기 섭스트레이트의 요부 바닥면에 형성된 회로패턴에 솔더로 접속되어 있되, 상기 요부의 깊이보다 작은 두께를 가지며 접속된 다수의 수동소자;상기 요부를 덮도록 접착수단으로 접착된 반도체칩;상기 반도체칩과 섭스트레이트 상면의 회로패턴을 상호 전기적으로 접속하는 다수의 도전성 접속수단;상기 반도체칩 및 도전성 접속수단이 외부환경으로부터 보호되도록 봉지재로 봉지되어 형성된 봉지부; 및,상기 섭스트레이트 하면에 형성된 회로패턴에 융착된 다수의 도전성볼을 포함하여 이루어진 반도체패키지.
- (삭제)
- 제5항에 있어서, 상기 섭스트레이트는 요부의 바닥면에서 상기 섭스트레이트의 하면까지 관통하는 일정 직경의 관통공이 더 형성된 것을 특징으로 하는 반도체패키지.
- (정정) 제5항 또는 제7항에 있어서, 상기 전기적 접속수단은 도전성 범프인 것을 특징으로 하는 반도체패키지.
- 제1항에 있어서, 상기 반도체칩의 상면에는 또다른 반도체칩이 도전성 범프에 의해 접속된 것을 특징으로 하는 반도체패키지.
- (정정) 중앙에 일정크기의 관통공이 형성된 수지층을 중심으로, 그 상,하면에 다수의 도전성 회로패턴이 형성된 섭스트레이트;상기 섭스트레이트의 관통공 내측에 어레이된 다수의 수동소자;상기 섭스트레이트의 관통공 내측에서 상기 수동소자의 상면에 접착수단으로 접착된 반도체칩;상기 반도체칩과 섭스트레이트 상면의 회로패턴을 상호 전기적으로 접속하는 다수의 도전성 와이어;상기 섭스트레이트의 관통공, 수동소자, 반도체칩, 도전성 와이어가 봉지재로 봉지되어 있되, 상기 수동소자의 하면은 봉지재 외부로 노출되도록 형성된 봉지부; 및,상기 섭스트레이트 하면에 형성된 회로패턴과 상기 봉지부 외측으로 노출된 수동소자의 하면에 융착된 다수의 도전성패드를 포함하여 이루어진 반도체패키지.
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Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6998721B2 (en) * | 2002-11-08 | 2006-02-14 | Stmicroelectronics, Inc. | Stacking and encapsulation of multiple interconnected integrated circuits |
US20040212081A1 (en) * | 2003-04-08 | 2004-10-28 | Carberry Patrick J. | Process for fabricating a power hybrid module |
US6833619B1 (en) * | 2003-04-28 | 2004-12-21 | Amkor Technology, Inc. | Thin profile semiconductor package which reduces warpage and damage during laser markings |
US6853064B2 (en) * | 2003-05-12 | 2005-02-08 | Micron Technology, Inc. | Semiconductor component having stacked, encapsulated dice |
US7019394B2 (en) * | 2003-09-30 | 2006-03-28 | Intel Corporation | Circuit package and method of plating the same |
US7008820B2 (en) | 2004-06-10 | 2006-03-07 | St Assembly Test Services Ltd. | Chip scale package with open substrate |
US20060051912A1 (en) * | 2004-09-09 | 2006-03-09 | Ati Technologies Inc. | Method and apparatus for a stacked die configuration |
JP2006216911A (ja) * | 2005-02-07 | 2006-08-17 | Renesas Technology Corp | 半導体装置およびカプセル型半導体パッケージ |
JPWO2006095852A1 (ja) * | 2005-03-10 | 2008-08-21 | 京セラ株式会社 | 電子部品モジュール及びその製造方法 |
US7622325B2 (en) * | 2005-10-29 | 2009-11-24 | Stats Chippac Ltd. | Integrated circuit package system including high-density small footprint system-in-package |
US7342308B2 (en) * | 2005-12-20 | 2008-03-11 | Atmel Corporation | Component stacking for integrated circuit electronic package |
US7791192B1 (en) * | 2006-01-27 | 2010-09-07 | Xilinx, Inc. | Circuit for and method of implementing a capacitor in an integrated circuit |
US8026129B2 (en) * | 2006-03-10 | 2011-09-27 | Stats Chippac Ltd. | Stacked integrated circuits package system with passive components |
DE102006022748B4 (de) * | 2006-05-12 | 2019-01-17 | Infineon Technologies Ag | Halbleiterbauteil mit oberflächenmontierbaren Bauelementen und Verfahren zu seiner Herstellung |
US20080054490A1 (en) * | 2006-08-31 | 2008-03-06 | Ati Technologies Inc. | Flip-Chip Ball Grid Array Strip and Package |
US20080093723A1 (en) * | 2006-10-19 | 2008-04-24 | Myers Todd B | Passive placement in wire-bonded microelectronics |
US8169067B2 (en) * | 2006-10-20 | 2012-05-01 | Broadcom Corporation | Low profile ball grid array (BGA) package with exposed die and method of making same |
KR100850897B1 (ko) * | 2007-01-22 | 2008-08-07 | 주식회사 네패스 | 수동소자가 매립된 반도체 장치 및 그 제조 방법 |
US7798703B2 (en) * | 2007-05-09 | 2010-09-21 | Infineon Technologies Ag | Apparatus and method for measuring local surface temperature of semiconductor device |
SG148054A1 (en) * | 2007-05-17 | 2008-12-31 | Micron Technology Inc | Semiconductor packages and method for fabricating semiconductor packages with discrete components |
JP5168284B2 (ja) * | 2007-08-24 | 2013-03-21 | 日本電気株式会社 | スペーサ及びその製造方法 |
US7566966B2 (en) * | 2007-09-05 | 2009-07-28 | Stats Chippac Ltd. | Integrated circuit package-on-package system with anti-mold flash feature |
US8222079B2 (en) * | 2007-09-28 | 2012-07-17 | International Business Machines Corporation | Semiconductor device and method of making semiconductor device |
US8183675B2 (en) * | 2007-11-29 | 2012-05-22 | Stats Chippac Ltd. | Integrated circuit package-on-package system with anti-mold flash feature |
US7781261B2 (en) * | 2007-12-12 | 2010-08-24 | Stats Chippac Ltd. | Integrated circuit package system with offset stacking and anti-flash structure |
US8536692B2 (en) * | 2007-12-12 | 2013-09-17 | Stats Chippac Ltd. | Mountable integrated circuit package system with mountable integrated circuit die |
US7985628B2 (en) * | 2007-12-12 | 2011-07-26 | Stats Chippac Ltd. | Integrated circuit package system with interconnect lock |
US8084849B2 (en) * | 2007-12-12 | 2011-12-27 | Stats Chippac Ltd. | Integrated circuit package system with offset stacking |
US8659154B2 (en) * | 2008-03-14 | 2014-02-25 | Infineon Technologies Ag | Semiconductor device including adhesive covered element |
US20090243069A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with redistribution |
US9955582B2 (en) * | 2008-04-23 | 2018-04-24 | Skyworks Solutions, Inc. | 3-D stacking of active devices over passive devices |
US9293385B2 (en) * | 2008-07-30 | 2016-03-22 | Stats Chippac Ltd. | RDL patterning with package on package system |
KR101011269B1 (ko) * | 2009-02-20 | 2011-01-27 | (주)씨엔에스 정보통신 | 다중렌즈를 갖는 돔형 카메라 |
US8357564B2 (en) * | 2010-05-17 | 2013-01-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die |
US8288201B2 (en) | 2010-08-25 | 2012-10-16 | Stats Chippac, Ltd. | Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die |
JP2012129464A (ja) * | 2010-12-17 | 2012-07-05 | Toshiba Corp | 半導体装置およびその製造方法 |
JP6122290B2 (ja) | 2011-12-22 | 2017-04-26 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 再配線層を有する半導体パッケージ |
US20130264721A1 (en) * | 2012-04-05 | 2013-10-10 | Infineon Technologies Ag | Electronic Module |
KR101666757B1 (ko) * | 2015-07-13 | 2016-10-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US10199356B2 (en) | 2017-02-24 | 2019-02-05 | Micron Technology, Inc. | Semiconductor device assembles with electrically functional heat transfer structures |
US10090282B1 (en) * | 2017-06-13 | 2018-10-02 | Micron Technology, Inc. | Semiconductor device assemblies with lids including circuit elements |
JP7013991B2 (ja) * | 2018-03-26 | 2022-02-01 | セイコーエプソン株式会社 | センサーユニット、移動体測位装置、携帯型電子機器、電子機器、移動体および表示装置 |
US11355470B2 (en) * | 2020-02-27 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and methods of manufacturing semiconductor devices |
KR20220026189A (ko) | 2020-08-25 | 2022-03-04 | 삼성전자주식회사 | 반도체 패키지 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05136330A (ja) * | 1991-11-15 | 1993-06-01 | Nec Corp | 半導体装置 |
JPH07307412A (ja) * | 1994-05-10 | 1995-11-21 | Sumitomo Metal Ind Ltd | バイパス用コンデンサ搭載積層パッケージ |
KR20000008455A (ko) * | 1998-07-14 | 2000-02-07 | 윤종용 | 칩 캐패시터 부착형 세라믹 패키지 |
JP2000349225A (ja) * | 1999-03-30 | 2000-12-15 | Ngk Spark Plug Co Ltd | コンデンサ付属配線基板、配線基板、及びコンデンサ |
KR20010067180A (ko) * | 1999-09-16 | 2001-07-12 | 윌리엄 비. 켐플러 | 저역 통과 필터와 일체로 되어 있는 반도체 패키지 |
Family Cites Families (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3880493A (en) * | 1973-12-28 | 1975-04-29 | Burroughs Corp | Capacitor socket for a dual-in-line package |
US4143385A (en) * | 1976-09-30 | 1979-03-06 | Hitachi, Ltd. | Photocoupler |
US4626958A (en) * | 1985-01-22 | 1986-12-02 | Rogers Corporation | Decoupling capacitor for Pin Grid Array package |
US4754366A (en) * | 1985-01-22 | 1988-06-28 | Rogers Corporation | Decoupling capacitor for leadless surface mounted chip carrier |
US4783646A (en) * | 1986-03-07 | 1988-11-08 | Kabushiki Kaisha Toshiba | Stolen article detection tag sheet, and method for manufacturing the same |
JPH01245588A (ja) * | 1988-03-28 | 1989-09-29 | Nec Corp | 配線基板 |
US5200364A (en) * | 1990-01-26 | 1993-04-06 | Texas Instruments Incorporated | Packaged integrated circuit with encapsulated electronic devices |
US5272590A (en) * | 1990-02-12 | 1993-12-21 | Hernandez Jorge M | Integrated circuit package having an internal cavity for incorporating decoupling capacitor |
EP0473796A4 (en) | 1990-03-15 | 1994-05-25 | Fujitsu Ltd | Semiconductor device having a plurality of chips |
JPH0462866A (ja) * | 1990-06-25 | 1992-02-27 | Seiko Epson Corp | 表面実装部品の実装方法 |
US5095402A (en) * | 1990-10-02 | 1992-03-10 | Rogers Corporation | Internally decoupled integrated circuit package |
JPH04179264A (ja) | 1990-11-14 | 1992-06-25 | Hitachi Ltd | 樹脂封止型半導体装置 |
JPH05136323A (ja) | 1991-11-13 | 1993-06-01 | Nec Corp | 集積回路装置 |
US5309324A (en) * | 1991-11-26 | 1994-05-03 | Herandez Jorge M | Device for interconnecting integrated circuit packages to circuit boards |
JPH06132469A (ja) * | 1992-10-15 | 1994-05-13 | Toshiba Corp | 集積回路素子及び該素子を有する電子機器装置 |
JPH06132472A (ja) * | 1992-10-20 | 1994-05-13 | Mitsubishi Electric Corp | Icパッケージ |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5474958A (en) | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
WO1995005676A1 (en) | 1993-08-13 | 1995-02-23 | Irvine Sensors Corporation | Stack of ic chips as substitute for single ic chip |
DE69527473T2 (de) | 1994-05-09 | 2003-03-20 | Nec Corp | Halbleiteranordnung bestehend aus einem Halbleiterchip, der mittels Kontakthöckern auf der Leiterplatte verbunden ist und Montageverfahren |
JP3267049B2 (ja) * | 1994-05-25 | 2002-03-18 | 株式会社村田製作所 | エアブリッジ配線を有するスパイラルインダクタの製造方法 |
KR0134648B1 (ko) * | 1994-06-09 | 1998-04-20 | 김광호 | 노이즈가 적은 적층 멀티칩 패키지 |
TW271496B (ko) * | 1994-06-09 | 1996-03-01 | Samsung Electronics Co Ltd | |
US5600175A (en) * | 1994-07-27 | 1997-02-04 | Texas Instruments Incorporated | Apparatus and method for flat circuit assembly |
JPH08148603A (ja) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | ボールグリッドアレイ型半導体装置およびその製造方法 |
US5583376A (en) * | 1995-01-03 | 1996-12-10 | Motorola, Inc. | High performance semiconductor device with resin substrate and method for making the same |
US5622588A (en) | 1995-02-02 | 1997-04-22 | Hestia Technologies, Inc. | Methods of making multi-tier laminate substrates for electronic device packaging |
US5783870A (en) * | 1995-03-16 | 1998-07-21 | National Semiconductor Corporation | Method for connecting packages of a stacked ball grid array structure |
JPH08316372A (ja) * | 1995-05-16 | 1996-11-29 | Toshiba Corp | 樹脂封止型半導体装置 |
JP3565454B2 (ja) * | 1995-08-02 | 2004-09-15 | 大日本印刷株式会社 | 樹脂封止型半導体装置 |
US5739581A (en) | 1995-11-17 | 1998-04-14 | National Semiconductor Corporation | High density integrated circuit package assembly with a heatsink between stacked dies |
US6013948A (en) | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US5674785A (en) | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
US5723907A (en) | 1996-06-25 | 1998-03-03 | Micron Technology, Inc. | Loc simm |
JP2817717B2 (ja) * | 1996-07-25 | 1998-10-30 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JPH1084074A (ja) * | 1996-09-09 | 1998-03-31 | Mitsubishi Electric Corp | 半導体パッケージ |
US5874770A (en) * | 1996-10-10 | 1999-02-23 | General Electric Company | Flexible interconnect film including resistor and capacitor layers |
US6127724A (en) * | 1996-10-31 | 2000-10-03 | Tessera, Inc. | Packaged microelectronic elements with enhanced thermal conduction |
US5847445A (en) * | 1996-11-04 | 1998-12-08 | Micron Technology, Inc. | Die assemblies using suspended bond wires, carrier substrates and dice having wire suspension structures, and methods of fabricating same |
US5841686A (en) * | 1996-11-22 | 1998-11-24 | Ma Laboratories, Inc. | Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate |
JP3266815B2 (ja) | 1996-11-26 | 2002-03-18 | シャープ株式会社 | 半導体集積回路装置の製造方法 |
JPH10173085A (ja) | 1996-12-06 | 1998-06-26 | Toshiba Corp | 電子モジュール及び電子モジュールの製造方法 |
JP4108779B2 (ja) * | 1996-12-27 | 2008-06-25 | ローム株式会社 | 回路チップ搭載カードおよび回路チップモジュール |
US5894108A (en) | 1997-02-11 | 1999-04-13 | National Semiconductor Corporation | Plastic package with exposed die |
US6160705A (en) | 1997-05-09 | 2000-12-12 | Texas Instruments Incorporated | Ball grid array package and method using enhanced power and ground distribution circuitry |
TW449844B (en) | 1997-05-17 | 2001-08-11 | Hyundai Electronics Ind | Ball grid array package having an integrated circuit chip |
FR2765399B1 (fr) * | 1997-06-27 | 2001-12-07 | Sgs Thomson Microelectronics | Dispositif semi-conducteur a moyen d'echanges a distance |
US5963429A (en) * | 1997-08-20 | 1999-10-05 | Sulzer Intermedics Inc. | Printed circuit substrate with cavities for encapsulating integrated circuits |
US5835355A (en) | 1997-09-22 | 1998-11-10 | Lsi Logic Corporation | Tape ball grid array package with perforated metal stiffener |
US5952611A (en) | 1997-12-19 | 1999-09-14 | Texas Instruments Incorporated | Flexible pin location integrated circuit package |
JP3013831B2 (ja) * | 1998-01-26 | 2000-02-28 | 日本電気株式会社 | Mmicパッケージ |
US6034427A (en) | 1998-01-28 | 2000-03-07 | Prolinx Labs Corporation | Ball grid array structure and method for packaging an integrated circuit chip |
US6172419B1 (en) | 1998-02-24 | 2001-01-09 | Micron Technology, Inc. | Low profile ball grid array package |
JP3514361B2 (ja) * | 1998-02-27 | 2004-03-31 | Tdk株式会社 | チップ素子及びチップ素子の製造方法 |
JP3609935B2 (ja) * | 1998-03-10 | 2005-01-12 | シャープ株式会社 | 高周波半導体装置 |
US6184463B1 (en) | 1998-04-13 | 2001-02-06 | Harris Corporation | Integrated circuit package for flip chip |
US5903052A (en) | 1998-05-12 | 1999-05-11 | Industrial Technology Research Institute | Structure for semiconductor package for improving the efficiency of spreading heat |
KR20000011585A (ko) * | 1998-07-28 | 2000-02-25 | 윤덕용 | 반도체소자및그제조방법 |
DE19852968C1 (de) * | 1998-11-17 | 2000-03-30 | Micronas Intermetall Gmbh | Halbleiterbauelement |
US6127833A (en) | 1999-01-04 | 2000-10-03 | Taiwan Semiconductor Manufacturing Co. | Test carrier for attaching a semiconductor device |
US6400576B1 (en) * | 1999-04-05 | 2002-06-04 | Sun Microsystems, Inc. | Sub-package bypass capacitor mounting for an array packaged integrated circuit |
US6215193B1 (en) * | 1999-04-21 | 2001-04-10 | Advanced Semiconductor Engineering, Inc. | Multichip modules and manufacturing method therefor |
JP3398721B2 (ja) | 1999-05-20 | 2003-04-21 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ及びその製造方法 |
JP3339838B2 (ja) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | 半導体装置およびその製造方法 |
TW417839U (en) * | 1999-07-30 | 2001-01-01 | Shen Ming Tung | Stacked memory module structure and multi-layered stacked memory module structure using the same |
US6122171A (en) | 1999-07-30 | 2000-09-19 | Micron Technology, Inc. | Heat sink chip package and method of making |
JP2001177345A (ja) * | 1999-12-15 | 2001-06-29 | Murata Mfg Co Ltd | 圧電発振器 |
US6538210B2 (en) * | 1999-12-20 | 2003-03-25 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
US6291264B1 (en) * | 2000-07-31 | 2001-09-18 | Siliconware Precision Industries Co., Ltd. | Flip-chip package structure and method of fabricating the same |
US6546620B1 (en) * | 2000-06-29 | 2003-04-15 | Amkor Technology, Inc. | Flip chip integrated circuit and passive chip component package fabrication method |
US6452278B1 (en) * | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
TW503538B (en) * | 2000-12-30 | 2002-09-21 | Siliconware Precision Industries Co Ltd | BGA semiconductor package piece with vertically integrated passive elements |
US6545347B2 (en) * | 2001-03-06 | 2003-04-08 | Asat, Limited | Enhanced leadless chip carrier |
US6608375B2 (en) * | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
KR20030018204A (ko) * | 2001-08-27 | 2003-03-06 | 삼성전자주식회사 | 스페이서를 갖는 멀티 칩 패키지 |
US6635970B2 (en) * | 2002-02-06 | 2003-10-21 | International Business Machines Corporation | Power distribution design method for stacked flip-chip packages |
-
2001
- 2001-04-02 KR KR10-2001-0017449A patent/KR100411811B1/ko active IP Right Grant
-
2002
- 2002-03-25 US US10/107,656 patent/US6995448B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05136330A (ja) * | 1991-11-15 | 1993-06-01 | Nec Corp | 半導体装置 |
JPH07307412A (ja) * | 1994-05-10 | 1995-11-21 | Sumitomo Metal Ind Ltd | バイパス用コンデンサ搭載積層パッケージ |
KR20000008455A (ko) * | 1998-07-14 | 2000-02-07 | 윤종용 | 칩 캐패시터 부착형 세라믹 패키지 |
JP2000349225A (ja) * | 1999-03-30 | 2000-12-15 | Ngk Spark Plug Co Ltd | コンデンサ付属配線基板、配線基板、及びコンデンサ |
KR20010067180A (ko) * | 1999-09-16 | 2001-07-12 | 윌리엄 비. 켐플러 | 저역 통과 필터와 일체로 되어 있는 반도체 패키지 |
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US20020140085A1 (en) | 2002-10-03 |
US6995448B2 (en) | 2006-02-07 |
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