JPS6448297A - Dram controller - Google Patents

Abstract

PURPOSE:To execute access request processing operation in correspondence to a request signal by displaying an access request input signal condition with a second register and storing a succeeding access request input signal to be added into an access condition with a first register. CONSTITUTION:A first logic signal, in which an access request input signal Sai and the output signal of a second register 2 are operated, is added through a gate 3 to a J terminal of a first register 1. A second logic signal, in which the access request input signal Sai and the output signal of the second register 2 are operated, is added through a gate 4 to a K terminal. Then, a clock CLK is added to a clock terminal. The logic signal, in which the access request input signal Sai and the output signal of the first register 1 are operated, is added through a gate 5 to the J terminal of the second register 2 and an access ending signal Sae is added from a DRAM control circuit to the K terminal. Thus, even while the access request processing operation is executed, the access request processing operation can be securely executed in correspondence to the succeeding access request signal.