JPS57150038A - Address designating circuit - Google Patents
Address designating circuitInfo
- Publication number
- JPS57150038A JPS57150038A JP3488981A JP3488981A JPS57150038A JP S57150038 A JPS57150038 A JP S57150038A JP 3488981 A JP3488981 A JP 3488981A JP 3488981 A JP3488981 A JP 3488981A JP S57150038 A JPS57150038 A JP S57150038A
- Authority
- JP
- Japan
- Prior art keywords
- register
- address
- memory
- signal
- contents
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 125000004122 cyclic group Chemical group 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To eliminate an address modifying command field under an arithmetic instruction, by combining an address holding register, a variable length cyclic shift register and an arithmetic logic operation unit. CONSTITUTION:A CPU sets first the address modifying command equivalent to the number of stages of an initial shift register SR9 of the address of a memory 4 at a register 8 and the SR9 by an initial value set request signal 7 via a data bus 3. After this, a memory access request signal 6 becomes genuine every time the CPU executes an ordinary arithmetic instruction, and an access is given to the memory 4 with the contents of the register 8 used as an address. At the same time, the contents of the register 8 is modified by an arithmetic logic operation unit 10, and this value is set to the register 8 by the memory access signal 7. At the same time, the register 8 is cyclically shifted by a stage by the signal 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3488981A JPS57150038A (en) | 1981-03-11 | 1981-03-11 | Address designating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3488981A JPS57150038A (en) | 1981-03-11 | 1981-03-11 | Address designating circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57150038A true JPS57150038A (en) | 1982-09-16 |
JPS6346858B2 JPS6346858B2 (en) | 1988-09-19 |
Family
ID=12426717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3488981A Granted JPS57150038A (en) | 1981-03-11 | 1981-03-11 | Address designating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57150038A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02213722A (en) * | 1989-02-15 | 1990-08-24 | Aichi Tokei Denki Co Ltd | Turbine type gas meter |
-
1981
- 1981-03-11 JP JP3488981A patent/JPS57150038A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6346858B2 (en) | 1988-09-19 |
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