JPS5494839A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5494839A
JPS5494839A JP215378A JP215378A JPS5494839A JP S5494839 A JPS5494839 A JP S5494839A JP 215378 A JP215378 A JP 215378A JP 215378 A JP215378 A JP 215378A JP S5494839 A JPS5494839 A JP S5494839A
Authority
JP
Japan
Prior art keywords
access
signal
line
clock signal
line address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP215378A
Other languages
Japanese (ja)
Inventor
Keiichi Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP215378A priority Critical patent/JPS5494839A/en
Publication of JPS5494839A publication Critical patent/JPS5494839A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To reduce the access time, by utilizing the page mode operation, in the memory unit having access with the interleave system. CONSTITUTION:When the line address signal has continuously access to the same word, it can be enough to give the row address signal and the line address clock signal only, and the access time and the cycle time can be reduced. The operation to utilize it is the page mode operation. When the line address signal for previous access mrmorized in the register 6 is in agreement with the line access signal, the multiplexer 11 is selected with the comparison circuit 7 and the line access signal is fed to the memory element 1, the gate 8 is closed, the line access clock signal is blocked, the multiplexer 9 is selected to the delay circuit 10, and the line address clock signal is given to the memory element 1.
JP215378A 1978-01-11 1978-01-11 Memory unit Pending JPS5494839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP215378A JPS5494839A (en) 1978-01-11 1978-01-11 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP215378A JPS5494839A (en) 1978-01-11 1978-01-11 Memory unit

Publications (1)

Publication Number Publication Date
JPS5494839A true JPS5494839A (en) 1979-07-26

Family

ID=11521401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP215378A Pending JPS5494839A (en) 1978-01-11 1978-01-11 Memory unit

Country Status (1)

Country Link
JP (1) JPS5494839A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0348111A2 (en) * 1988-06-24 1989-12-27 Advanced Micro Devices, Inc. A method of accessing data in memory
EP0366359A2 (en) * 1988-10-12 1990-05-02 Advanced Micro Devices, Inc. Reducing power consumption in on-chip memory devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0348111A2 (en) * 1988-06-24 1989-12-27 Advanced Micro Devices, Inc. A method of accessing data in memory
EP0366359A2 (en) * 1988-10-12 1990-05-02 Advanced Micro Devices, Inc. Reducing power consumption in on-chip memory devices

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