JPS5752949A - Debugging equipment for logical operation circuit - Google Patents

Debugging equipment for logical operation circuit

Info

Publication number
JPS5752949A
JPS5752949A JP55128881A JP12888180A JPS5752949A JP S5752949 A JPS5752949 A JP S5752949A JP 55128881 A JP55128881 A JP 55128881A JP 12888180 A JP12888180 A JP 12888180A JP S5752949 A JPS5752949 A JP S5752949A
Authority
JP
Japan
Prior art keywords
input
signal
terminal
condition
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55128881A
Other languages
Japanese (ja)
Inventor
Yuji Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Corp
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Corp, Olympus Optical Co Ltd filed Critical Olympus Corp
Priority to JP55128881A priority Critical patent/JPS5752949A/en
Publication of JPS5752949A publication Critical patent/JPS5752949A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To store condition changes of input signals, by installing a gate which passes clocks having high frequencies which can follow the condition change of input signals, when the present condition and the condition of one clock before of input signals do not coincide when they are compared. CONSTITUTION:Actuating signals of a circuit to be measured 1 are supplied as input signals to a debugging equipment shown in the upper part of the diagram to a terminal A of a comparator 16 through a terminal 11 and an input buffer 12, and, at the same time, transferred to a register for memory 13 by a start signal from a clock controlling circuit 17, and then, information stored in the register before that is supplied to another terminal B. When both signals do not coincide, an AND gate 18 is turned on by the no-coincidence signal and a clock signal having a high frequency which can completely follow the speed of condition change of the output signal of the controlling circuit 17 and the input signal input through a terminal 19, and the content of the register 13 is successively stored in an internal memory 14 by using this clock signal as a shift pulse.
JP55128881A 1980-09-17 1980-09-17 Debugging equipment for logical operation circuit Pending JPS5752949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55128881A JPS5752949A (en) 1980-09-17 1980-09-17 Debugging equipment for logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55128881A JPS5752949A (en) 1980-09-17 1980-09-17 Debugging equipment for logical operation circuit

Publications (1)

Publication Number Publication Date
JPS5752949A true JPS5752949A (en) 1982-03-29

Family

ID=14995656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55128881A Pending JPS5752949A (en) 1980-09-17 1980-09-17 Debugging equipment for logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5752949A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4636919A (en) * 1985-03-20 1987-01-13 Hitachi, Ltd. Multilayer printed circuit board
JPH0717163U (en) * 1993-09-03 1995-03-28 二鷹産業株式会社 Graveyard flower stand

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4636919A (en) * 1985-03-20 1987-01-13 Hitachi, Ltd. Multilayer printed circuit board
JPH0717163U (en) * 1993-09-03 1995-03-28 二鷹産業株式会社 Graveyard flower stand

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