JPS63128642A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63128642A JPS63128642A JP61274764A JP27476486A JPS63128642A JP S63128642 A JPS63128642 A JP S63128642A JP 61274764 A JP61274764 A JP 61274764A JP 27476486 A JP27476486 A JP 27476486A JP S63128642 A JPS63128642 A JP S63128642A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- groove
- well
- mask
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 abstract description 11
- 150000004767 nitrides Chemical class 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置、特に第１導電型半導体基板力に第２
導電型ウエルを形成する半導体装置の製造方法は、公知
の如く、ウェル分離のための溝を形成した後に、ウェル
を形成していた。Conventional semiconductor devices, especially the first conductivity type semiconductor substrate force and the second conductivity type semiconductor device.
In a well-known method of manufacturing a semiconductor device in which a conductive well is formed, the well is formed after trenches for well isolation are formed.
しかし、前生の従来技術ではレジストパターンをマスク
にイオン注入しウェルを形成するため、マスク合わせの
余裕を見込んで、分離のための溝の幅はある程度広くし
なければならず、そのことが素子の高度な微細化を妨げ
る要因となっていた。However, in the previous conventional technology, wells were formed by implanting ions using a resist pattern as a mask, so the width of the groove for isolation had to be widened to some extent to allow for margin for mask alignment. This has been a factor that hinders the advanced miniaturization of .
そこで本発明はこのような問題点を解決するもので、そ
の目的とすることは、ウェル形成後セル７アラインでウ
ェル分離用溝を形成することで、溝幅を縮少し、素子の
高度な微細化を容易にする半導体装置の裂遣方法ｔ−提
供することにある。Therefore, the present invention is intended to solve these problems.The purpose of the present invention is to form a well isolation groove in cell 7 alignment after well formation, thereby reducing the groove width and making it possible to improve the precision of the device. An object of the present invention is to provide a method for tearing apart a semiconductor device that facilitates the production of semiconductor devices.
本発明の半導体装置の製造方法は、第１導電型半導体基
板内に第２導電型ウエルを形成する半導体装置において
、ウェルに対してセル７アラインでウェル分離用溝を形
成すること’ｔ％倣とする。A method for manufacturing a semiconductor device of the present invention includes forming a well isolation groove in a cell 7 alignment with respect to a well in a semiconductor device in which a second conductivity type well is formed in a first conductivity type semiconductor substrate. shall be.
以下第１図（ａ）〜（１））により詳細に実施例を説明
する。The embodiment will be described in detail below with reference to FIGS. 1(a) to (1)).
工程１・・・第１図（ａ）
Ｐ型半導体基板１０１上に第１の酸化膜１０２を５００
０〜７０００に化学的気相成長法で形成し、レジストパ
ターンをマスクに前記第１の酸化膜の一部をエツチング
によシ除去する。次に窒化膜を３０００〜６０００Ａ化
学的気相成長法で形成し之後に、リアクティブイオンで
全面エツチングすることで前記第１の酸化膜１０２の側
壁に窒化膜１０３を形成する。次に前記第１の酸化膜１
０２、窒化ｇ１０３をマスクにＮ型不純物１０４をイオ
ン住人する。Step 1...FIG. 1(a) A first oxide film 102 is deposited on a P-type semiconductor substrate 101 with a thickness of 500 mm.
0 to 7000 by chemical vapor deposition, and a part of the first oxide film is removed by etching using a resist pattern as a mask. Next, a nitride film is formed using a 3000 to 6000A chemical vapor deposition method, and then the entire surface is etched using reactive ions to form a nitride film 103 on the sidewalls of the first oxide film 102. Next, the first oxide film 1
02, N-type impurity 104 is ionized using nitride G103 as a mask.
工程２・・・第１図（１））
前記＠１の酸化膜１０２、窒化膜１０３をマスクに前記
半導体基板の一部に熱酸化法で選択的に第２の酸化膜１
０５ｔ−３０００〜５０００Ａ形成（尚、この時第１の
酸化膜１０２も１０００〜２０００Ｘ膜厚は増加する。Step 2...FIG. 1 (1)) Using the oxide film 102 and nitride film 103 of @1 as a mask, a second oxide film 1 is selectively formed on a part of the semiconductor substrate by thermal oxidation.
05t-3000-5000A formation (At this time, the thickness of the first oxide film 102 also increases by 1000-2000X.
）
工程３・・・第１図（Ｃ）
Ｉ！ｉＩ記窒化膜１０３を熱リン酸で除去した後、前記
第１の酸化膜１０２、第２の酸化［１０５を、マスクに
前記半導体基板１０１の一部をリアクティブイオンでエ
ツチングしウェル分離用溝１ｏ６ｔ″２〜４μ形成する
。) Process 3...Figure 1 (C) I! After removing the nitride film 103 with hot phosphoric acid, a part of the semiconductor substrate 101 is etched with reactive ions using the first oxide film 102 and the second oxide film 105 as a mask to form well isolation grooves. Form 1o6t''2-4μ.
工程４・・・第１図（ｄ）
熱酸化法によシ前記１１１１１ｏ６内部に２００〜３０
０Ａの第３の酸化膜１０７を形成した後、全面に多結晶
シリコン１０８ｔ−化学的気相成長法で３〜５μ形成し
、エッチパックにょシ溝１０６外部の多結晶シリコン１
０８を除去する。Step 4...Figure 1(d) By thermal oxidation method, 200 to 30
After forming the third oxide film 107 of 0A, 108t of polycrystalline silicon 108t is formed on the entire surface by 3 to 5μ by chemical vapor deposition, and the polycrystalline silicon 108 outside the etch pack groove 106 is
Remove 08.
工程５・・・第１図（θ）
１０００Ｃ〜ｌ１００Ｃでドライブインすることにより
１〜３μの深さのＮウェル１０９′ｌｋ形成する。Step 5...FIG. 1 (θ) By driving in at 1000C to 1100C, an N well 109'lk with a depth of 1 to 3μ is formed.
以上述べたように発明によれば、ウェルに対してセル７
アラインでウェル分離用溝が形成できるため、溝幅を縮
少することができる。これにょシ高度の微細化を容易に
行なえるという効果を有する。As described above, according to the invention, the cell 7
Since the well isolation groove can be formed by alignment, the groove width can be reduced. This has the effect of easily achieving a high degree of miniaturization.
ａＩＪ１図（ａ）〜（６）は本発明の半導体装置の製造
工程を表わす主要断面図。
１０１・・・・・・Ｐ型半導体基板
１０２・・・・・・第１の酸化膜
１０３・・・・・・窒化膜
１０４・・・・・・Ｎ型不純物
１０５・・・・・・第２の酸化膜
１０６・・・・・・（ウェル分離用）溝１０７・・・・
・・第３の酸化膜
１０８・・・・・・多結晶シリコン
１０９・・・・・・Ｎウェル
以 上aIJ1 Figures (a) to (6) are main sectional views showing the manufacturing process of the semiconductor device of the present invention. 101...P-type semiconductor substrate 102...First oxide film 103...Nitride film 104...N-type impurity 105...Nth 2 oxide film 106... (well isolation) groove 107...
...Third oxide film 108...Polycrystalline silicon 109...N well or more
Claims (1)
る半導体装置において、前記ウェルに対してセルフアラ
インでウェル分離用溝を形成することを特徴とする半導
体装置の製造方法。1. A method of manufacturing a semiconductor device in which a second conductivity type well is formed in a first conductivity type semiconductor substrate, characterized in that a well isolation groove is formed in self-alignment with respect to the well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61274764A JPS63128642A (en) | 1986-11-18 | 1986-11-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61274764A JPS63128642A (en) | 1986-11-18 | 1986-11-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63128642A true JPS63128642A (en) | 1988-06-01 |
Family
ID=17546249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61274764A Pending JPS63128642A (en) | 1986-11-18 | 1986-11-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63128642A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0323649A (en) * | 1989-06-21 | 1991-01-31 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| KR970053410A (en) * | 1995-12-22 | 1997-07-31 | 김주용 | Device Separation Method of Semiconductor Device |
-
1986
- 1986-11-18 JP JP61274764A patent/JPS63128642A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0323649A (en) * | 1989-06-21 | 1991-01-31 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| KR970053410A (en) * | 1995-12-22 | 1997-07-31 | 김주용 | Device Separation Method of Semiconductor Device |
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