JPH03284855A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03284855A JPH03284855A JP8658090A JP8658090A JPH03284855A JP H03284855 A JPH03284855 A JP H03284855A JP 8658090 A JP8658090 A JP 8658090A JP 8658090 A JP8658090 A JP 8658090A JP H03284855 A JPH03284855 A JP H03284855A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- single crystal
- forming
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 239000007790 solid phase Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 239000002784 hot electron Substances 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- 230000004913 activation Effects 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 4
- -1 arsenic ions Chemical class 0.000 abstract 1
- 239000010408 film Substances 0.000 description 26
- 238000001312 dry etching Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置とその製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same.
従来の技術
近年、半導体の単一基板に多数の機能素子を組み込む集
積回路技術が発達している。集積回路における高集積度
は素子パターンルールを細くしていくことによって実現
されている。しかし、パターンルールが1μmより細く
なるような素子を集積する場合、パターンルールの減少
につれて、素子の閾値電圧が変化する短チヤネル効果、
狭チャネル効果または素子内部の電界が大きくなり、電
子が高エネルギーを持つホットエレクトロン効果により
、素子耐圧が低下したり、素子寿命が減少することが知
られている。BACKGROUND OF THE INVENTION In recent years, integrated circuit technology has been developed that incorporates a large number of functional elements onto a single semiconductor substrate. High degree of integration in integrated circuits is achieved by narrowing element pattern rules. However, when integrating devices with pattern rules that are thinner than 1 μm, short channel effects occur where the threshold voltage of the device changes as the pattern rules decrease.
It is known that the narrow channel effect or the hot electron effect, in which the electric field inside the device increases and electrons have high energy, lowers the device breakdown voltage and shortens the device life.
このような問題を解決し、集積回路の高集積化を実現す
るために新しい構造を持つ素子の開発が進められている
。In order to solve these problems and achieve higher integration of integrated circuits, the development of elements with new structures is underway.
このような例として、サラランディング・ゲート・トラ
ンジスタ(Surrounding GateN、0K
ABE、A、NITAYANA、に、H[EDA、F、
HORIGUCHI andF、M^5UOKA、I
EDM Tech、Dig、、pp2 2 2 −2
2 3 。An example of this is a Surrounding Gate transistor (Surrounding GateN, 0K
ABE, A, NITAYANA, H[EDA, F,
HORIGUCHI and F, M^5UOKA, I
EDM Tech, Dig, pp2 2 2 -2
2 3.
1988) 。1988).
第3図にSGTの断面構造図を示す。この素子の製造方
法はシリコン基板1にウェル層2を形成した後、ドライ
エツチングを用いて凸型にシリコン基板1をエツチング
し、イオン注入を行ってソース3.ドレイン4を形成す
る。次に、ゲート酸化膜5を堆積した後、多結晶シリコ
ン6を堆積し凸型の側面以外の多結晶シリコン6を除去
することによってゲート形成が行われる。FIG. 3 shows a cross-sectional structural diagram of the SGT. The method for manufacturing this device is to form a well layer 2 on a silicon substrate 1, then etch the silicon substrate 1 into a convex shape using dry etching, and perform ion implantation to form a source 3. A drain 4 is formed. Next, after depositing a gate oxide film 5, a gate is formed by depositing polycrystalline silicon 6 and removing the polycrystalline silicon 6 other than the side surfaces of the convex shape.
発明が解決しようとする課題
従来技術または従来の素子においては、高集積化をはか
ることによって短チヤネル効果、狭チャネル効果やホッ
トエレクトロン効果が生じ、素子の電気的特性が劣化す
ると言う問題点がある。また、従来提案されたSGTは
凸型のエツチングで完全に垂直な側壁が形成されなけれ
ばソース3゜ドレイン4形成時のイオンが側壁に注入さ
れ、素子特性を劣化させるため、完全に垂直な側壁を持
つように制御できるエツチング装置が必要である。しか
し、現在では、このようなエツチングを行うことは困難
で、安定性や信頼性の面からも問題がある。また、ゲー
ト電極に多結晶シリコン6が用いられるが、多結晶シリ
コン6を堆積した後、側壁部にだけ多結晶シリコン6を
残す方法にはドライエツチングが用いられる。しかし、
ドライエツチングの制御が良くないと多結晶シリコン6
の形状が場所によって異なったり、ソース3゜ドレイン
4の拡散領域から離れてしまったりして素子の特性が悪
くなる。凸型のエツチングではソース3部、ゲート側壁
部はドライエツチングによってプラズマにさらされるた
め結晶欠陥等による素子特性の劣化を生じるなどの問題
点がある。Problems to be Solved by the Invention In prior art or conventional devices, there is a problem in that short channel effects, narrow channel effects, and hot electron effects occur due to high integration, which deteriorates the electrical characteristics of the device. . In addition, in conventionally proposed SGTs, if perfectly vertical sidewalls are not formed by convex etching, ions from forming the source 3 and drain 4 will be implanted into the sidewalls, degrading the device characteristics. An etching device that can be controlled so that the However, at present, it is difficult to carry out such etching, and there are also problems in terms of stability and reliability. Further, although polycrystalline silicon 6 is used for the gate electrode, dry etching is used to leave the polycrystalline silicon 6 only on the side walls after depositing the polycrystalline silicon 6. but,
If dry etching is not well controlled, polycrystalline silicon 6
The shape of the source 3 may vary depending on the location, or the source 3 may be separated from the drain 4 diffusion region, resulting in poor device characteristics. In convex etching, the source 3 and gate sidewalls are exposed to plasma during dry etching, which causes problems such as deterioration of device characteristics due to crystal defects and the like.
課題を解決するための手段
本発明は上記課題を解決するために、シリコン基板上に
半導体膜を形成し、エツチングした溝部分に溝幅の半分
以下の膜厚の単結晶シリコンを成長し、半導体膜側壁に
不純物層を形成後、酸化性被膜の形成およびゲート電極
を形成し、さらに酸化性被膜の所定領域をエツチングし
、導電性配線を形成する。Means for Solving the Problems In order to solve the above problems, the present invention forms a semiconductor film on a silicon substrate, grows single-crystal silicon in the etched groove portion to a thickness less than half the width of the groove, and forms a semiconductor film on a silicon substrate. After forming an impurity layer on the sidewalls of the film, an oxidizing film and a gate electrode are formed, and a predetermined region of the oxidizing film is etched to form conductive wiring.
作用
本発明は基板をエツチングすることがなく、素子は溝側
壁にソース、ドレインを形成するため実効チャネル長が
見掛は上長くなり、短チヤネル効果、狭チャネル効果や
ホットエレクトロン効果の低減が図れる。さらに本発明
の構造の素子形成は現在、半導体製造部門において用い
られている装置で形成できるためコストが低(済みまた
、製造上、素子特性上安定で信頼性の高い素子が形成で
きる。Function: The present invention does not require etching of the substrate, and the source and drain of the device are formed on the trench sidewalls, so the effective channel length is apparently longer, and short channel effects, narrow channel effects, and hot electron effects can be reduced. . Furthermore, since the device having the structure of the present invention can be formed using equipment currently used in the semiconductor manufacturing sector, the cost is low, and the device can be manufactured with stability and high reliability in terms of manufacturing and device characteristics.
実施例
第1図は本発明の一実施例における半導体装置の製造方
法を示す断面工程図である。Embodiment FIG. 1 is a cross-sectional process diagram showing a method of manufacturing a semiconductor device in an embodiment of the present invention.
N型(100)シリコン基板7上に、例えば2μm厚の
NSG (Non−doped 5ilicate G
lass)膜8を減圧CVDで堆積する。この後、ホト
リソグラフィーを用いて例えば2μm幅の領域を開けた
レジストパターン9を形成した後、レジストパターン9
をマスクにフレオン系ドライエツチングによってNSC
膜8をエツチングする(第1図a)。For example, 2 μm thick NSG (Non-doped G) is deposited on the N-type (100) silicon substrate 7.
lass) film 8 is deposited by low pressure CVD. After that, a resist pattern 9 is formed using photolithography, for example, with a 2 μm wide area opened, and then the resist pattern 9 is
NSC using Freon dry etching as a mask.
The membrane 8 is etched (FIG. 1a).
つぎにレジストパターン9を除去した後、厚さ0.6μ
mのシリコン単結晶をエピタキシャル成長させる。この
エピタキシャル成長膜はボロン濃度をたとえば4 X
1016/cI11として形成した。ここでエピタキシ
ャル成長によるシリコン膜は下地シリコン基板7が露出
した領域内では単結晶シリコン10となり、NSCSC
上では多結晶シリコン11となる。次にシリコン基板7
全面にレジスト12を回転塗布してシリコン基板7表面
を平坦化する。この後反応性イオンエツチングを用いて
エピタキシャル成長によって堆積した多結晶シリコン1
1が表面に露出するまでエッチバックを行う。この後リ
ンと砒素のイオン注入を行い活性化することによってN
SCSC膜壁側壁結晶シリコン10の縦方向に高濃度P
形層19と低濃度P形層13からなるLDD (Lig
htly Doped Drain)構造を形成する(
第1図b)。この後、レジスト12を除去した後、CV
Dで熱酸化を行ってシリコン基板7全面にたとえば厚さ
400人の酸化膜14を形成する。さらに多結晶シリコ
ン15を1.1μmの厚さに堆積した後、シリコン基板
7上全面にレジストを塗布しシリコン基板7上を平坦化
する。次に、単結晶シリコン10で囲まれたくぼみ領域
16をレジストでマスクするように露光、現象し、レジ
ストパターンを形成する。この時、くぼみ領域16のレ
ジストマスク形成の精度はここでは±1.0μm程度あ
れば十分である。この後、フレオン系ガスを用いてレジ
ストパターンをマスクに多結晶シリコン15を除去し、
レジストパターンを除去する(第1図C)。この多結晶
シリコン15はゲート電極として用いられる。Next, after removing the resist pattern 9, the thickness is 0.6 μm.
A silicon single crystal of m is epitaxially grown. This epitaxially grown film has a boron concentration of, for example, 4
1016/cI11. Here, the epitaxially grown silicon film becomes single crystal silicon 10 in the area where the base silicon substrate 7 is exposed, and the NSCSC
The upper layer becomes polycrystalline silicon 11. Next, silicon substrate 7
A resist 12 is spin coated over the entire surface to flatten the surface of the silicon substrate 7. Polycrystalline silicon 1 was then deposited by epitaxial growth using reactive ion etching.
Etch back until 1 is exposed on the surface. After this, by ion implantation of phosphorus and arsenic and activation, N
High concentration of P in the vertical direction of the SCSC film sidewall crystalline silicon 10
LDD (Lig
htly Doped Drain) to form a structure (
Figure 1 b). After that, after removing the resist 12, the CV
In step D, thermal oxidation is performed to form an oxide film 14 with a thickness of, for example, 400 mm over the entire surface of the silicon substrate 7. Further, after depositing polycrystalline silicon 15 to a thickness of 1.1 μm, a resist is applied to the entire surface of the silicon substrate 7 to flatten the surface of the silicon substrate 7. Next, the recessed region 16 surrounded by the single crystal silicon 10 is exposed and developed so as to be masked with a resist, thereby forming a resist pattern. At this time, it is sufficient that the accuracy of forming the resist mask for the recessed region 16 is about ±1.0 μm. After that, the polycrystalline silicon 15 is removed using a Freon gas using the resist pattern as a mask.
The resist pattern is removed (FIG. 1C). This polycrystalline silicon 15 is used as a gate electrode.
この後、NSCSC上に形成された多結晶シリコン11
はNSC膜8g4壁の単結晶シリコン10に形成された
ソース、ドレイン拡散層の電極となっているため、多結
晶シリコン11上のコンタクトになる部分の酸化膜14
を除去し、アルミニウム18等の導電性膜配線を形成す
る(第1図d)。After this, polycrystalline silicon 11 formed on the NSCSC
are the electrodes of the source and drain diffusion layers formed in the single crystal silicon 10 on the wall of the NSC film 8g4.
is removed, and a conductive film wiring made of aluminum 18 or the like is formed (FIG. 1d).
なお、本実施例ではNSC膜を用いた場合について説明
したが、HTO膜や窒化シリコン膜等の半導体膜、およ
びこれらの半導体膜を積層した構造のものを用いること
もできる。In this embodiment, a case has been described in which an NSC film is used, but a semiconductor film such as an HTO film or a silicon nitride film, or a structure in which these semiconductor films are stacked may also be used.
また、本発明ではソース、ドレインの拡散層を形成する
ためにイオン注入を用いているが不純物を含んだ半導体
膜からの固相拡散を利用することによって拡散層を形成
することもできる。この場合の構造を説明するための断
面図を第2図に示す。Further, in the present invention, ion implantation is used to form the source and drain diffusion layers, but the diffusion layers can also be formed by utilizing solid phase diffusion from a semiconductor film containing impurities. A sectional view for explaining the structure in this case is shown in FIG.
シリコン基板22上にたとえば5000A厚の薄(、−
s熱酸化膜20を減圧CVDを用いて堆積し、その上に
たとえばリン8wt%含む回転塗布ガラス(以下SOG
と記す: 5pin−On−Glass) 21を2μ
mの厚さに塗布する。5OG21は塗布後、400℃、
1時間のベークによって焼き固められる。この後、5O
G21 、熱酸化膜20の所定領域をエツチングし、次
にエピタキシャル成長させる。以下第1図の工程断面図
にしたがって製造される。For example, a thin film (, -
A thermal oxide film 20 is deposited using low pressure CVD, and a spin coated glass (hereinafter referred to as SOG) containing, for example, 8 wt% phosphorus is deposited thereon.
Written as: 5pin-On-Glass) 21 is 2μ
Apply to a thickness of m. 5OG21 is heated to 400℃ after application.
It is hardened by baking for 1 hour. After this, 5O
G21, a predetermined region of the thermal oxide film 20 is etched, and then epitaxially grown. Hereinafter, it is manufactured according to the process sectional view shown in FIG.
ここで用いた薄い熱酸化膜20はこの上に積層する不純
物を含んだ半導体膜である5OG21からシリコン基板
22に不純物が拡散し、隣接素子と導通しないように設
けられている。また、配線となる多結晶シリコン11に
も不純物が拡散することが不都合な場合には、5OG2
1上にさらに酸化シリジン膜を形成するような3層構造
にすることが必要である。The thin thermal oxide film 20 used here is provided so as to prevent impurities from diffusing into the silicon substrate 22 from the 5OG 21 layered thereon, which is a semiconductor film containing impurities, and conduction with adjacent elements. In addition, if it is inconvenient that impurities diffuse into the polycrystalline silicon 11 that becomes the wiring, 5OG2
It is necessary to form a three-layer structure in which a silidine oxide film is further formed on top of the first layer.
なお、ここでは不純物を含んだ半導体膜とじてリンを含
有した5OG21を用いているが、リン以外に砒素やボ
ロンを含んだ5OG21もあり、導電形も選択できる。Here, 5OG21 containing phosphorus is used as the impurity-containing semiconductor film, but 5OG21 containing arsenic or boron other than phosphorus is also available, and the conductivity type can also be selected.
また、ここでは工程が簡単になることから5OG21を
用いたが、ボロンやリンを含む酸化シリコン膜(例えば
BPSG。In addition, although 5OG21 was used here because it simplifies the process, a silicon oxide film containing boron or phosphorus (for example, BPSG) may also be used.
BSG、PSG等)を用いることもできる。BSG, PSG, etc.) can also be used.
拡散層の形成では、固相拡散によって拡散層を形成する
こともできるが、固相拡散とイオン注入を併合して用い
ることもでき、これによってLDD構造の拡散層が容易
に形成できる。In forming the diffusion layer, it is possible to form the diffusion layer by solid-phase diffusion, but it is also possible to use a combination of solid-phase diffusion and ion implantation, whereby a diffusion layer with an LDD structure can be easily formed.
発明の効果
以上のように本発明は単結晶を成長させることによって
、素子の実効チャネル長を見掛は上長くすることができ
るため、短チヤネル効果、狭チャネル効果やホットエレ
クトロン効果の低減が図れる。Effects of the Invention As described above, the present invention can apparently increase the effective channel length of a device by growing a single crystal, thereby reducing short channel effects, narrow channel effects, and hot electron effects. .
また、製造工程は既存の装置を用いることで十分である
ことから、コスト的にも安価で安定した製造が可能で、
本発明の製造方法で形成した素子は信頼性が高く、さら
に微細な素子形成が可能であることから高集積化が図れ
る。In addition, since the manufacturing process suffices to use existing equipment, it is possible to achieve stable manufacturing at low cost.
Elements formed by the manufacturing method of the present invention have high reliability, and since it is possible to form finer elements, higher integration can be achieved.
第1図は本発明の一実施例における半導体装置の製造方
法を示す工程断面図、第2図は本発明の他の実施例にお
ける半導体装置の断面図、第3図は従来の半導体装置の
断面図である。FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. It is a diagram.
Claims (3)
けた上記半導体基板が露出する領域に成長させた上記領
域幅の半分以下の膜厚の単結晶半導体と、上記半導体膜
側壁部の上記単結晶半導体部に形成したソースとドレイ
ンと、上記単結晶半導体で囲まれた領域内に沿って形成
したゲート酸化膜と、上記ゲート酸化膜上に形成したゲ
ート電極とを備えた半導体装置。(1) A predetermined region of the semiconductor film on the semiconductor substrate is removed, and a single crystal semiconductor with a film thickness of half or less of the width of the region is grown in the region where the semiconductor substrate is exposed, and the side wall portion of the semiconductor film is A semiconductor device comprising: a source and a drain formed in the single crystal semiconductor portion; a gate oxide film formed along a region surrounded by the single crystal semiconductor; and a gate electrode formed on the gate oxide film.
体膜を形成し、所定領域をエッチングする工程と、露出
した上記半導体基板の主面上に上記所定領域幅の半分以
下の膜厚の一導電型単結晶半導体を成長させる工程と、
上記所定領域の上記半導体膜側壁部の上記単結晶半導体
に反対導電型不純物層を形成する工程と、上記単結晶半
導体上に酸化性被膜を形成する工程と、上記酸化性被膜
上にゲート電極を形成する工程と、上記酸化性被膜の所
定領域をエッチングし、導電性配線を形成する工程とを
備えた半導体装置の製造方法。(2) forming at least one layer of semiconductor film on the main surface of the semiconductor substrate and etching a predetermined region; and forming a film on the exposed main surface of the semiconductor substrate with a film thickness of less than half the width of the predetermined region. A step of growing a single conductivity type single crystal semiconductor;
forming an opposite conductivity type impurity layer on the single crystal semiconductor on the side wall of the semiconductor film in the predetermined region; forming an oxidizing film on the single crystal semiconductor; and forming a gate electrode on the oxidizing film. A method for manufacturing a semiconductor device, comprising: forming a conductive wiring; and etching a predetermined region of the oxidizing film to form a conductive wiring.
場合に半導体膜中の不純物の固相拡散によって形成する
請求項2記載の半導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 2, wherein when forming the impurity layer of one conductivity type and the opposite conductivity type, the impurity layer is formed by solid phase diffusion of impurities in the semiconductor film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8658090A JPH03284855A (en) | 1990-03-30 | 1990-03-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8658090A JPH03284855A (en) | 1990-03-30 | 1990-03-30 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03284855A true JPH03284855A (en) | 1991-12-16 |
Family
ID=13890943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8658090A Pending JPH03284855A (en) | 1990-03-30 | 1990-03-30 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03284855A (en) |
-
1990
- 1990-03-30 JP JP8658090A patent/JPH03284855A/en active Pending
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